Freescale Semiconductor, Inc. Application Note AN2533/D Rev. 0, 5/2003 Standard Space Vector Modulation – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) Freescale Semiconductor, Inc... By Milan Brejl, Ph.D. Functional Overview Standard Space Vector Modulation – 3 outputs version – XOR version (svmStd3Xor) is a version of the Standard Space Vector Modulation – 3 output version (svmStd3) function that uses two TPU channels to generate one PWM output channel. The TPU channel outputs are connected to an XOR gate whos output is the required PWM signal. See Figure 1. An advantage of this solution is the full range 0% to 100% of PWM duty-cycle ratios. There is no MPW (minimum pulse width) parameter to limit the edge duty-cycle ratios in this version, unlike in the svmStd3. A disadvantage is that the number of assigned TPU channels is doubled. A1 XOR A2 B1 XOR B2 C1 XOR C2 Figure 1. Functionality of XOR version – illustration The function set consists of 5 TPU functions: • Standard Space Vector Modulation – 3 outputs version – XOR version – R channels (svmStd3Xor_R) • Standard Space Vector Modulation – 3 outputs version – XOR version – T channels (svmStd3Xor_T) © Freescale Semiconductor, Inc., 2004. All rights reserved. For More Information On This Product, Go to: www.freescale.com © Motorola, Inc., 2003 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... AN2533/D • Synchronization Signal for Standard Space Vector Modulation – 3 outputs version – XOR version (svmStd3Xor_sync) • Resolver Reference Signal for Standard Space Vector Modulation – 3 outputs version – XOR version (svmStd3Xor_res) • Fault Input for Standard Space Vector Modulation – 3 outputs version – XOR version (svmStd3Xor_fault) The svmStd3Xor function generates 3 pairs of XOR gate input signals. The XOR gate outputs then produce a 3-channel 3-phase center-aligned PWM signal. The generated signals control external hardware, which outputs pair of transistor signals (top and bottom) with dead-time inserted. The Synchronization Signal for the svmStd3Xor function can be used to generate one or more adjustable signals for a wide range of uses, that are synchronized to the PWM, and track changes in the PWM period. The Resolver Reference Signal for the svmStd3Xor function can be used to generate one or more 50% duty-cycle adjustable signals that are also synchronized to the PWM. The Fault Input for the svmStd3Xor function is a TPU input function that sets all XOR gate outputs low when the input signal goes low. Function Set Configuration None of the TPU functions in the Standard Space Vector Modulation – 3 outputs version – XOR version TPU function set can be used separately. The svmStd3Xor_R and svmStd3Xor_T functions have to be used together. The svmStd3Xor_R runs on pins A1, B1, C1, and the svmStd3Xor_T runs on pins A2, B2, C2 – see Figure 1. One or more channels running Synchronization Signal for svmStd3Xor as well as Resolver Reference Signals for svmStd3Xor functions can be added to the svmStd3Xor_R and svmStd3Xor_T functions. They can run with different settings on each channel. The function Fault Input for svmStd3Xor can also be added to the svmStd3Xor_R and svmStd3Xor_T functions. It is recommended to use it on channel 15, and to set the hardware option that disables all TPU output pins when the channel 15 input signal is low (DTPU bit = 1). This ensures that the hardware reacts quickly to a pin fault state. Note that it is not only the svmStd3Xor_R and svmStd3Xor_T channels, but all TPU output channels, including the synchronization signals, that are disabled in this configuration. Table 1 shows the configuration options and restrictions. 2 Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Function Set Configuration Table 1. svmStd3Xor TPU function set configuration options and restrictions Optional/ How many Mandatory channels svmStd3Xor_R mandatory 3 svmStd3Xor_T mandatory 3 svmStd3Xor_sync optional 1 or more svmStd3Xor_res optional 1 or more TPU function Freescale Semiconductor, Inc... svmStd3Xor_fault optional 1 Assignable channels any 3 channels any 3 channels any channels any channels any, recommended is 15 and DTPU bit set Table 2 shows an example of configuration. Table 2. Example of configuration Channel 0 1 2 3 4 5 13 14 15 TPU function svmStd3Xor_R svmStd3Xor_T svmStd3Xor_R svmStd3Xor_T svmStd3Xor_R svmStd3Xor_T svmStd3Xor_sync svmStd3Xor_res svmStd3Xor_fault Priority middle middle middle middle middle middle low low high Table 3 shows the TPU function code sizes. Table 3. TPU function code sizes. TPU function svmStd3Xor_R svmStd3Xor_T svmStd3Xor_sync svmStd3Xor_res svmStd3Xor_fault Configuration Order Code size 216 µ instructions + 8 entries = 224 long words 3 µ instructions + 8 entries = 11 long words 26 µ instructions + 8 entries = 34 long words 38 µ instructions + 8 entries = 46 long words 9 µ instructions + 8 entries = 17 long words The CPU configures the TPU as follows. 1. Disables the channels by clearing the two channel priority bits on each channel used (not necessary after reset). 2. Selects the channel functions on all used channels by writing the function numbers to the channel function select bits. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. AN2533/D 3. Initializes function parameters. The parameters T, prescaler, SQRT3, CPU14 and sync_presc_addr must be set before initialization. If an svmStd3Xor_sync channel or an svmStd3Xor_res channel is used, then its parameters must also be set before initialization. Freescale Semiconductor, Inc... 4. Issues an HSR (Host Service Request) type %10 to one of the svmStd3Xor_R channels to initialize all svmStd3Xor_R and svmStd3Xor_T channels. Issues an HSR type %10 to the svmStd3Xor_sync channels, svmStd3Xor_res channels and svmStd3Xor_fault channel, if used. 5. Enables servicing by assigning high, middle or low priority to the channel priority bits. All svmStd3Xor_R and svmStd3Xor_T channels must be assigned the same priority to ensure correct operation. The CPU must ensure that the svmStd3Xor_sync or svmStd3Xor_res channels are initialized after the initialization of the svmStd3Xor_R and svmStd3Xor_T channels: – – – NOTE: assign a priority to the svmStd3Xor_R and svmStd3Xor_T channels to enable their initialization if a Synchronization Signal or a Resolver Reference Signal channel is used, wait until the HSR bits are cleared to indicate that initialization of the svmStd3Xor_R and svmStd3Xor_T channels has completed and assign a priority to the svmStd3Xor_sync or svmStd3Xor_res channels to enable their initialization A CPU routine that configures the TPU can be generated automatically using the MPC500_Quick_Start Graphical Configuration Tool. Detailed Function Description Standard Space Vector Modulation – 3 outputs version – XOR version – R channels (svmStd3Xor_R) and Standard Space Vector Modulation – 3 outputs version – XOR version – T channels (svmStd3Xor_T) 4 The svmStd3Xor_R and svmStd3Xor_T TPU functions work together to generate 3 pairs of XOR gate inputs. The XOR gate outputs then produce a 3channel 3-phase center-aligned PWM signal. Unlike the svmStd, the generated signals are not top-bottom pairs with dead-times but only top-like signals without dead-times. In order to charge the bootstrap transistors, the PWM signals start to run 1.6ms after their initialization (at 20MHz TCR1 clock). The functions generate signals corresponding to Reference Voltage Vector Amplitude of 0 (50% duty-cycle) until the first reloaded values are processed. The CPU controls the PWM output by setting the TPU parameters. The Stator Reference Voltage Vector components uá and uâ have to be adjusted during run time. The PWM period T and the prescaler – the number of PWM periods per reload of new values – are also read at each reload, so these parameters can be changed during run time. The CPU notifies the TPU that the new reload Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description values are prepared by setting the LD_OK parameter. The TPU notifies the CPU that the reload values have been read and new values can be written by clearing the LD_OK parameter. The TPU writes the parameter Sector that indicates the current Stator Reference Voltage Vector position in sector 1 to 6. The following figures show the input Stator Reference Voltage Vector components uá and uâ, corresponding sectors and output PWM signal duty cycle ratios: amplitude 0.5 0 -0.5 -1 alpha beta 0 60 120 180 240 300 360 angle Standard Space Vector Modulation Technique duty cycle ratios Freescale Semiconductor, Inc... Components of the Stator Reference Voltage Vector 1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 Phase A Phase B Phase C 60 120 180 240 300 360 angle Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6 Figure 2. Standard Space Vector Modulation Technique The following equations describe how the Space Vector Modulation PWM signal high-times htA, htB, htC and transition times ttrans of each channel are calculated: U β = T ⋅ uβ U α = T ⋅ uα Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. AN2533/D X =Uβ Y= Z= U β + Uα 3 2 U β − Uα 3 Freescale Semiconductor, Inc... Sector: 6 2 = < =! ; ;! = ; V. IV. III. VI. <! ;! I. =! II. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description Host Interface Written By CPU Written by both CPU and TPU Written By TPU Not Used Table 4. svmStd3Xor_T Control Bits Freescale Semiconductor, Inc... 3 2 1 Name Channel Function Select 0 1 0 Channel Priority 1 0 Host Service Bits (HSR) 1 Options svmStd3Xor_T function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 – Channel Disabled 01 – Low Priority 10 – Middle Priority 11 – High Priority 00 – No Host Service Request 01 – Not used 10 – Not used 11 – Not used 0 Host Sequence Bits (HSQ) xx – Not used Channel Interrupt Enable x – Not used Channel Interrupt Status x – Not used 0 0 Table 5. svmStd3Xor_R Control Bits Name 3 2 1 0 Channel Function Select 1 0 Channel Priority 1 0 Host Service Bits (HSR) Options svmStd3Xor_R function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 – Channel Disabled 01 – Low Priority 10 – Middle Priority 11 – High Priority 00 – No Host Service Request 01 – Not used 10 – Initialization 11 – Stop Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. AN2533/D Table 5. svmStd3Xor_R Control Bits Name 1 0 Host Sequence Bits (HSQ) xx – Not used Channel Interrupt Enable 0 – Channel Interrupt Disabled 1 – Channel Interrupt Enabled Channel Interrupt Status 0 – Interrupt Not Asserted 1 – Interrupt Asserted 0 0 Freescale Semiconductor, Inc... Options TPU function svmStd3Xor_R generates an interrupt when the current values of Ualfa, Ubeta, T and prescaler have been read by TPU and indicates to the CPU that it can write new variables. The CPU program can either wait for this interrupt to occur, or poll the LD_OK bit to check it has cleared. The interrupt is generated at each reload by one of the R channels. The T channels do not generate any interrupts. Table 6. svmStd3Xor_T and svmStd3Xor_R Parameter RAM Phase A 2 channel Phase A 1 channel Channel 8 Parameter 15 14 13 12 11 10 9 8 7 6 5 0 htA 1 x2_chan_A x1a_chan_A 2 x1b_chan_A 3 4 Ualfa Ubeta 5 6 7 fault_pinstate 0 Ttime_A2 T_copy 1 2 prsc_copy UA 3 LD_OK 4 5 Sector 6 7 4 Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 3 2 1 0 Freescale Semiconductor, Inc. AN2533/D Detailed Function Description Table 6. svmStd3Xor_T and svmStd3Xor_R Parameter RAM Phase C 2 channel Phase C 1 channel Phase B 2 channel Freescale Semiconductor, Inc... Phase B 1 channel Channel Parameter 15 14 13 12 11 10 9 8 7 6 5 0 htB x2_chan_B 1 2 x1a_chan_B x1b_chan_B 3 T 4 5 prescaler 6 7 0 Ttime_B2 dec 1 2 UA3 UB 3 SQRT3 4 5 sync_presc_addr 6 7 0 htC x2_chan_C 1 x1a_chan_C 2 3 x1b_chan_C CPU14 4 5 6 7 0 Ttime_C2 1 state center_time 2 3 4 5 6 7 4 3 2 1 0 Table 7. svmStd3Xor_T and svmStd3Xor_R parameter description Parameter Ualfa, Ubeta T prescaler Format Description Parameters written by CPU Stator Reference Voltage Vector 16-bit fractional components PWM period in number of TCR1 16-bit unsigned integer TPU cycles The number of PWM periods per 16-bit unsigned integer reload of new values Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. AN2533/D Table 7. svmStd3Xor_T and svmStd3Xor_R parameter description Freescale Semiconductor, Inc... Parameter Format Description Time of 14 IMB clocks in TCR1 CPU14 16-bit unsigned integer clocks. sqrt(3)/2 = 0.866 = $6EDA SQRT3 16-bit fractional constant address of synchronization channel prescaler parameter: $X4, sync_presc_addr 8-bit unsigned integer where X is synchronization channel number. $0 if no synchronization channel is used. Parameters written by both TPU and CPU 0 ... CPU can update variables LD_OK 1-bit 1 ... TPU can read variables CPU sets 1, TPU sets 0 Parameters written by TPU The position of Stator Reference Sector 16-bit unsigned integer Voltage Vector in a sector. The Sector can be 1, 2, 3, 4, 5 or 6 If fault channel is used, state of fault pin: fault_pinstate 0 or 1 0 ... low 1 ... high Other parameters are just for TPU function inner use. Performance Table 8. svmStd3Xor_T State Statistics State ST SF Max IMB Clock Cycles 2 2 RAM Accesses by TPU 1 0 Table 9. svmStd3Xor_R State Statistics State INIT STOP SFR0 SFR C5 SFC0 SFC 10 Max IMB Clock Cycles 92 82 6 40 16 6 56 RAM Accesses by TPU 25 4 1 14 4 1 11 Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description NOTE: Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) C5 A1 SFR0 C5 Phase A SF Freescale Semiconductor, Inc... A2 SFC0 B1 ST SF SFR0 C5 ST C5 Phase B SF ST B2 C1 SFR SF SFR C5 SFC SFC SFC SFC ST C5 flag1 = 1 Phase C SF C2 flag0 = 1 ST SF center_time not a reload period center_time a reload period T T ST link service request Figure 3. svmStd3Xor_T and svmStd3Xor_R timing NOTE: The R channel with the momentary earliest transition within the PWM period is marked by a flag1 and runs the SFR and SFC states. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. AN2533/D SF Freescale Semiconductor, Inc... SF ST ST ST SF ST flag0 = 1 link Figure 4. svmStd3Xor_T state diagram and 3 cases of timing NOTE: 12 Which case happens is determined by the time when the link comes. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description SFR SFC 4th-time C5 3-times Freescale Semiconductor, Inc... INIT STOP HSR = 10 HSR = 11 SFC0 C5 SFR0 flag1 = 0 flag1 = 1 – channel with momentary longest high-time Figure 5. svmStd3Xor_R state diagram Synchronization signal for Standard Space Vector Modulation – 3 outputs version – XOR version (svmStd3Xor_sync) The svmStd3Xor_sync TPU function uses information obtained from svmStd3Xor_R and svmStd3Xor_T functions, the actual PWM center times and the PWM periods. This allows a signal to be generated, which tracks the changes in the PWM period and is always synchronized with the PWM. The synchronization signal is a positive pulse generated repeatedly after the prescaler or presc_copy PWM periods (see next paragraph). The low to high transition of the pulse can be adjusted by a parameter, either negative or positive, to go a number of TCR1 TPU cycles before or after the PWM period center time. The pulse width pw is another synchronization signal parameter. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. AN2533/D move > 0 prescaler = 1 pw |move| center_time center_time T T move < 0 prescaler = 2 Freescale Semiconductor, Inc... pw |move| center_time center_time center_time T T T Figure 6. Synchronization signal adjustment examples Synchronized Change of PWM Prescaler And Synchronization Signal Prescaler The svmStd3Xor_sync TPU function actually uses the presc_copy parameter instead of the prescaler parameter. The prescaler parameter holds the prescaler value that is copied to the presc_copy by the svmStd3Xor_bottom function at the time the PWM parameters are reloaded. This ensures that new prescaler values for the PWM signals, as well as the synchronization signal, are applied at the same time. Write the synchronization signal prescaler parameter address to the sync_presc_addr parameter to enable this mechanism. Write 0 to disable it, and remember to set the synchronization signal presc_copy parameter instead of the prescaler parameter in this case. Host Interface Written By CPU Written by both CPU and TPU Written By TPU Not Used Table 10. svmStd3Xor_sync Control Bits Name 3 2 1 0 Channel Function Select 1 0 Channel Priority 14 Options svmStd3Xor_sync function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 – Channel Disabled 01 – Low Priority 10 – Middle Priority 11 – High Priority Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description Table 10. svmStd3Xor_sync Control Bits Name 1 0 Host Service Bits (HSR) 1 0 Host Sequence Bits (HSQ) xx – Not used Channel Interrupt Enable 0 – Channel Interrupt Disabled 1 – Channel Interrupt Enabled Channel Interrupt Status 0 – Interrupt Not Asserted 1 – Interrupt Asserted 0 0 TPU function svmStd3Xor_sync generates an interrupt after each low to high transition. Table 11. svmStd3Xor_sync Parameter RAM Channel Synchronization channel Freescale Semiconductor, Inc... Options 00 – No Host Service Request 01 – Not used 10 – Initialization 11 – Not used Parameter 15 14 13 12 11 10 9 8 7 6 0 move 1 pw prescaler 2 presc_copy 3 4 time dec 5 T_copy 6 5 4 3 2 1 0 7 Table 12. svmStd3Xor_sync parameter description Parameter move pw Format Description Parameters written by CPU The number of TCR1 TPU cycles to forego (negative) or come after 16-bit signed integer (positive) the PWM period center time Synchronization pulse width in 16-bit unsigned integer number of TCR1 TPU cycles. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. AN2533/D Table 12. svmStd3Xor_sync parameter description Freescale Semiconductor, Inc... Parameter Description The number of PWM periods per synchronization pulse prescaler 16-bit unsigned integer – use in case of synchronized prescalers change The number of PWM periods per synchronization pulse presc_copy 16-bit unsigned integer – use in case of asynchronized prescalers change Parameters written by TPU Other parameters are just for TPU function inner use. Performance Format There is one limitation. The absolute value of parameter move has to be less than a quarter of the PWM period T. move < T 4 Table 13. svmStd3Xor_sync State Statistics State INIT S1 S2 S3 NOTE: S1 Max IMB Clock Cycles 12 12 8 16 RAM Accesses by TPU 5 6 3 7 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) S2 S3 S1 center_time center_time center_time T T T Figure 7. svmStd3Xor_sync timing 16 Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com S2 Freescale Semiconductor, Inc. AN2533/D Detailed Function Description HSR = 10 Freescale Semiconductor, Inc... INIT S1 S3 S2 Figure 8. svmStd3Xor_sync state diagram Resolver Reference Signal for Standard Space Vector Modulation – 3 outputs version – XOR version (svmStd3Xor_res) The svmStd3Xor_res TPU function uses information read from the svmStd3Xor_R and svmStd3Xor_T functions, the actual PWM center times and the PWM periods. This allows a signal to be generated, which tracks the changes of the PWM period and is always synchronized with the PWM. The resolver reference signal is a 50% duty-cycle signal with a period equal to prescaler or synchronization channel presc_copy PWM periods (see next paragraph). The low to high transition of the pulse can be adjusted by a parameter, either negative or positive, to go a number of TCR1 TPU cycles before or after the PWM period center time. move > 0 prescaler = 1 |move| center_time center_time T T center_time center_time center_time T T T move < 0 prescaler = 2 |move| Figure 9. Resolver reference signal adjustment examples Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. AN2533/D Synchronized Change of PWM Prescaler And Resolver Reference Signals Prescaler The svmStd3Xor_res TPU function can inherit the Synchronization Signal prescaler that is synchronously changed with the PWM prescaler. Write the synchronization signals presc_copy parameter address to the presc_addr parameter to enable this mechanism. Write 0 to disable it, and in this case set the prescaler parameter to directly specify prescaler value. Freescale Semiconductor, Inc... Host Interface Written By CPU Written by both CPU and TPU Written By TPU Not Used Table 14. svmStd3Xor_res Control Bits Name 3 2 1 0 Channel Function Select 1 0 Channel Priority 1 0 Host Service Bits (HSR) 1 Options svmStd3Xor_res function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 – Channel Disabled 01 – Low Priority 10 – Middle Priority 11 – High Priority 00 – No Host Service Request 01 – Not used 10 – Initialization 11 – Not used 0 Host Sequence Bits (HSQ) xx – Not used Channel Interrupt Enable x – Not used Channel Interrupt Status x – Not used 0 0 18 Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description Table 15. svmStd3Xor_res Parameter RAM Freescale Semiconductor, Inc... Resolver Channel Parameter 15 14 13 12 11 10 9 8 7 6 0 move 1 2 presc_addr 3 prescaler time 4 dec 5 6 T_copy 7 5 4 3 2 1 0 Table 16. svmStd3Xor_res parameter description Parameter move presc_addr prescaler Format Description Parameters written by CPU The number of TCR1 TPU cycles to forego (negative) or come after 16-bit signed integer (positive) the PWM period center time $00X6, where X is a number of Synchronization Signal channel, to inherit Sync. channel prescaler or 16-bit unsigned integer $0000 to enable direct specification of prescaler value in prescaler parameter The number of PWM periods per synchronization pulse – use when apresc_addr = 0 Parameters written by TPU 1, 2, 4, 6, 8, 10, 12, 14, ... Other parameters are just for TPU function inner use. Performance There is one limitation. The absolute value of parameter move has to be less than a quarter of the PWM period T. move < T 4 Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 19 Freescale Semiconductor, Inc. AN2533/D Table 17. svmStd3Xor_res State Statistics State INIT S1 S3 Freescale Semiconductor, Inc... NOTE: Max IMB Clock Cycles 12 26 18 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) S3 S1 RAM Accesses by TPU 5 9 7 S1 center_time center_time center_time T T T Figure 10. svmStd3Xor_res timing HSR = 10 INIT S1 S3 Figure 11. svmStd3Xor_res state diagram Fault Input for Standard Space Vector Modulation – 3 outputs version – XOR version (svmStd3Xor_fault) 20 The svmStd3Xor_fault is an input TPU function that monitors the pin, and if a high to low transition occurs, immediately sets all PWM channels low and cancels all further transitions on them. The PWM channels, as well as the synchronization and resolver reference signal channels (if used), have to be initialized again to start them running. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description The function returns the actual pinstate as a value of 0 (low) or 1 (high) in the parameter fault_pinstate. The parameter is placed on the A1 channel to keep the fault channel parameter space free. Host Interface Written By CPU Written by both CPU and TPU Written By TPU Not Used Freescale Semiconductor, Inc... Table 18. svmStd3Xor_fault Control Bits Name 3 2 1 0 Channel Function Select 1 0 Channel Priority 1 0 Host Service Bits (HSR) 1 Options svmStd3Xor_fault function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 – Channel Disabled 01 – Low Priority 10 – Middle Priority 11 – High Priority 00 – No Host Service Request 01 – Not used 10 – Initialization 11 – Not used 0 Host Sequence Bits (HSQ) xx – Not used Channel Interrupt Enable 0 – Channel Interrupt Disabled 1 – Channel Interrupt Enabled Channel Interrupt Status 0 – Interrupt Not Asserted 1 – Interrupt Asserted 0 0 TPU function svmStd3Xor_fault generates an interrupt when a high to low transition appears. Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 21 Freescale Semiconductor, Inc. AN2533/D Table 19. svmStd3Xor_fault Parameter RAM Freescale Semiconductor, Inc... Fault input Channel Parameter 15 14 13 12 11 10 9 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 Table 20. svmStd3Xor_fault parameter description Parameter fault_pinstate Format Description Parameters written by TPU State of fault pin: 0 or 1 0 ... low 1 ... high Performance Table 21. svmStd3Xor_fault State Statistics State INIT FAULT NO_FAULT NOTE: 22 Max IMB Clock Cycles 8 88 4 RAM Accesses by TPU 2 5 1 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2533/D Detailed Function Description ) NO_FAULT FAULT Figure 12. svmStd3Xor_fault timing. HSR = 10 Freescale Semiconductor, Inc... INIT FAULT NO_FAULT Figure 13. svmStd3Xor_fault state diagram Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) For More Information On This Product, Go to: www.freescale.com 23 Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com Freescale Semiconductor, Inc... E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. 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