Standard SVM with Dead-Time Correction - XOR version

Freescale Semiconductor, Inc.
Application Note
AN2531/D
Rev. 0, 5/2003
Standard Space Vector
Modulation with Dead-Time
Correction – XOR version
TPU Function Set
(svmStdDtXor)
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By Milan Brejl, Ph.D.
Functional Overview
The Standard Space Vector Modulation with Dead-Time Correction – XOR
version (svmStdDtXor) is a version of the Standard Space Vector Modulation
with Dead-Time Correction (svmStdDt) function that uses two TPU channels to
generate one PWM output channel. The TPU channel outputs are connected
to an XOR gate whos output is the required PWM signal. See Figure 1. An
advantage of this solution is the full range 0% to 100% of PWM duty-cycle
ratios. There is no MPW (minimum pulse width) parameter to limit the edge
duty-cycle ratios in this version, unlike in the svmStdDt. A disadvantage is that
the number of assigned TPU channels is doubled.
AT1
XOR
Phase A - top
XOR
Phase A - bottom
XOR
Phase B - top
XOR
Phase B - bottom
XOR
Phase C - top
XOR
Phase C - bottom
AT2
AB1
AB2
BT1
BT2
BB1
BB2
CT1
CT2
CB1
CB2
Figure 1. Functionality of XOR version – illustration
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The dead-time correction technique requires knowledge of the instantaneous
direction of phase currents. In the case of positive phase current the top
channel high-time is equal to the calculated high-time and the bottom channel
has to control the dead-time. In case of negative phase current the bottom
channel low-time is equal to the calculated high-time and the top channel has
to control the dead-time. See Figure 2.
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calculated
high-time
In case of positive current:
top channel
bottom channel
DT
DT
In case of negative current:
top channel
bottom channel
DT
DT
Figure 2. Dead-Time Correction Technique
The function set consists of 5 TPU functions:
•
Standard Space Vector Modulation with Dead-Time Correction – XOR
version – R channels (svmStdDtXor_R)
•
Standard Space Vector Modulation with Dead-Time Correction – XOR
version – T channels (svmStdDtXor_T)
•
Synchronization Signal for Standard Space Vector Modulation with
Dead-Time Correction – XOR version (svmStdDtXor_sync)
•
Resolver Reference Signal for Standard Space Vector Modulation with
Dead-Time Correction – XOR version (svmStdDtXor_res)
•
Fault Input for Standard Space Vector Modulation with Dead-Time
Correction – XOR version (svmStdDtXor_fault)
The svmStdDtXor_R and svmStdDtXor_T TPU functions work together to
generate 6 pairs of XOR gate inputs. The XOR gate outputs then produce a 6channel 3-phase center-aligned PWM signal with dead-time between the top
and bottom channels. The Synchronization Signal for the svmStdDtXor
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Function Set Configuration
function can be used to generate one or more adjustable signals for a wide
range of uses, that are synchronized to the PWM, and track changes in the
PWM period. The Resolver Reference Signal for the svmStdDtXor function can
be used to generate one or more 50% duty-cycle adjustable signals that are
also synchronized to the PWM. The Fault Input for the svmStdDtXor function is
a TPU input function that sets all XOR gate outputs low when the input signal
goes low.
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Function Set Configuration
None of the TPU functions in the Standard Space Vector Modulation with
Dead-Time Correction – XOR version TPU function set can be used
separately. The svmStdDtXor_R and svmStdDtXor_T functions have to be
used together. The svmStdDtXor_R runs on pins AB1, BB1, CB1 – see Figure
1. The svmStdDtXor_T runs on the other pins. One or more channels running
Synchronization Signal for svmStdDtXor as well as Resolver Reference
Signals for svmStdDtXor functions can be added to the svmStdDtXor_R and
svmStdDtXor_T functions. They can run with different settings on each
channel. The function Fault Input for svmStdDtXor can also be added to the
svmStdDtXor_R and svmStdDtXor_T functions. It is recommended to use it on
channel 15, and to set the hardware option that disables all TPU output pins
when the channel 15 input signal is low (DTPU bit = 1). This ensures that the
hardware reacts quickly to a pin fault state. Note that it is not only the PWM
channels, but all TPU output channels, including the synchronization signals,
that are disabled in this configuration.
Table 1 shows the configuration options and restrictions.
Table 1. svmStdDtXor TPU function set configuration options and
restrictions
TPU function
svmStdDtXor_R
svmStdDtXor_T
svmStdDtXor_sync
svmStdDtXor_res
svmStdDtXor_fault
Optional/ How many
Mandatory channels
mandatory
3
mandatory
9
optional
1 or more
optional
1 or more
optional
1
Assignable channels
any 3 channels
any 9 channels
any channels
any channels
any, recommended is 15 and
DTPU bit set
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Table 2 shows an example of configuration.
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Table 2. Example of configuration
Channel
0
1
2
3
4
5
6
7
8
9
10
11
13
14
15
TPU function
svmStdDtXor_T
svmStdDtXor_T
svmStdDtXor_R
svmStdDtXor_T
svmStdDtXor_T
svmStdDtXor_T
svmStdDtXor_R
svmStdDtXor_T
svmStdDtXor_T
svmStdDtXor_T
svmStdDtXor_R
svmStdDtXor_T
svmStdDtXor_sync
svmStdDtXor_res
svmStdDtXor_fault
Priority
middle
middle
middle
middle
middle
middle
middle
middle
middle
middle
middle
middle
low
low
high
Table 3 shows the TPU function code sizes.
Table 3. TPU function code sizes
TPU function
svmStdDtXor_R
svmStdDtXor_T
svmStdDtXor_sync
svmStdDtXor_res
svmStdDtXor_fault
Configuration Order
Code size
300 µ instructions + 8 entries = 308 long words
3 µ instructions + 8 entries = 11 long words
26 µ instructions + 8 entries = 34 long words
38 µ instructions + 8 entries = 46 long words
9 µ instructions + 8 entries = 17 long words
The CPU configures the TPU as follows.
1. Disables the channels by clearing the two channel priority bits on each
channel used (not necessary after reset).
2. Selects the channel functions on all used channels by writing the
function numbers to the channel function select bits.
3. Initializes function parameters. The parameters T, prescaler, DT,
SQRT3, CPU14 and sync_presc_addr must be set before initialization.
If an svmStdDtXor_sync channel or an svmStdDtXor_res channel is
used, then its parameters must also be set before initialization.
4. Issues an HSR (Host Service Request) type %10 to one of the
svmStdDtXor_R channels to initialize all svmStdDtXor_R and
svmStdDtXor_T channels. Issues an HSR type %10 to the
4
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Detailed Function Description
svmStdDtXor_sync channels, svmStdDtXor_res channels and
svmStdDtXor_fault channel, if used.
5. Enables servicing by assigning a high, middle or low priority to the
channel priority bits. All svmStdDtXor_R and svmStdDtXor_T channels
must be assigned the same priority to ensure correct operation. The
CPU must ensure that the svmStdDtXor_sync or svmStdDtXor_res
channels are initialized after the initialization of the StdDtXor_R and
svmStdDtXor_T channels:
–
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–
–
NOTE:
assign a priority to the StdDtXor_R and svmStdDtXor_T channels to
enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the StdDtXor_R and svmStdDtXor_T channels has
completed and
assign a priority to the svmStdDtXor_sync or svmStdDtXor_res
channels to enable their initialization
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
Detailed Function Description
Standard Space
Vector Modulation
with Dead-Time
Correction – XOR
version – R channels
(svmStdDtXor_R)
and Standard Space
Vector Modulation
with Dead-Time
Correction – XOR
version – T channels
(svmStdDtXor_T)
The svmStdDtXor_R and svmStdDtXor_T TPU functions work together to
generate 6 pairs of XOR gate inputs. The XOR gate outputs then produce a 6channel 3-phase center-aligned PWM signal with dead-time between the top
and bottom channels. In order to charge the bootstrap transistors, the PWM
signals start to run 1.6ms after their initialization (at 20MHz TCR1 clock). The
functions generate signals corresponding to Reference Voltage Vector
Amplitude of 0 (50% duty-cycle) until the first reloaded values are processed.
The CPU controls the PWM output by setting the TPU parameters. The Stator
Reference Voltage Vector components uá and uâ have to be adjusted during
run time. The PWM period T and the prescaler – the number of PWM periods
per reload of new values – are also read at each reload, so these parameters
can be changed during run time. Conversely, dead-time (DT) is not supposed
to be changed during run time. The phase currents currentA, currentB and
currentC are read by the TPU asynchronously to PWM parameters reload.
They are read in the last part of the edge-time calculation to reflect the latest
state of the phase currents. The CPU notifies the TPU that the new reload
values are prepared by setting the LD_OK parameter. The TPU notifies the
CPU that the reload values have been read and new values can be written by
clearing the LD_OK parameter.
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The TPU writes the parameter Sector, which indicates the current Stator
Reference Voltage Vector position in sector 1 to 6.
The following figures show the input Stator Reference Voltage Vector
components uá and uâ, corresponding sectors and output PWM signal duty
cycle ratios:
amplitude
Components of the Stator Reference Voltage Vector
1
0.5
0
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-0.5
-1
alpha
beta
0
60
120
180
240
300
360
angle
duty cycle ratios
Standard Space Vector Modulation Technique
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0 0
Phase A
Phase B
Phase C
60
120
180
240
300
360
angle
Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6
Figure 3. Standard Space Vector Modulation Technique
The following equations describe how the Space Vector Modulation PWM
signal high-times htA, htB, htC and transition times ttrans of each channel are
calculated:
U β = T ⋅ uβ
U α = T ⋅ uα
X =Uβ
Y=
Z=
6
U β + Uα 3
2
U β − Uα 3
2
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Detailed Function Description
<
=! ; ;!
=
; V.
IV.
III.
VI.
<! ;!
=! I.
II.
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Sector:
=
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Phase A:
Positive current
Negative current
– T1 channel
– T1 channel
t trans = center_time −
ht A
2
– T2 channel
t trans
ht
= center_time + A
2
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– B1 channel
ttrans
ht
= center_time − A − DT
2
– B2 channel
ttrans
ht
= center_time + A + DT
2
t trans = center_time −
ht A
+ DT
2
– T2 channel
t trans = center_time +
ht A
− DT
2
– B1 channel
t trans = center_time −
ht A
2
– B2 channel
t trans = center_time +
ht A
2
Phase B and Phase C similarly with htB and htC substituted to htA.
8
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Detailed Function Description
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 4. svmStdDtXor_T Control Bits
Name
3
2
1
0
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Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
svmStdDtXor_T function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Not used
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
0
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Table 5. svmStdDtXor_R Control Bits
Name
3
2
1
0
Channel Function Select
1
0
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Channel Priority
1
0
Host Service Bits (HSR)
1
Options
svmStdDtXor_R function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Stop
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
0
TPU function svmStdDtXor_R generates an interrupt when the current values
of Ualfa, Ubeta, T and prescaler have been read by the TPU and indicates to
the CPU that it can write new variables. The CPU program can either wait for
this interrupt to occur, or poll the LD_OK bit to check it has cleared. The
interrupt is generated at each reload by one of the R channels. The T channels
do not generate any interrupts.
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Detailed Function Description
Table 6. svmStdDtXor_T and svmStdDtXor_R Parameter RAM
Phase A
T2 channel
Phase A
B1 channel
Phase A
B2 channel
Phase B
T1 channel
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Phase A
T1 channel
Channel
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
Ttime_AT1
T_copy
1
prsc_copy
2
3
UA
Ualfa
4
Ubeta
5
6
7
fault_pinstate
0
Ttime_AT2
min_ht
1
max_ht
2
3
UB
LD_OK
4
Sector
5
6
7
0
htA
1
B2_chan_A
T1_chan_A
2
T2_chan_A
3
4
B1a_chan_A
B1b_chan_A
5
currentA
6
7
0
Ttime_AB2
state
1
2
center_time
dec
3
T
4
5
prescaler
6
7
0
Ttime_BT1
UA3
1
2
3
4
SQRT3
sync_presc_addr
5
6
7
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3
2
1
0
11
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Table 6. svmStdDtXor_T and svmStdDtXor_R Parameter RAM
Phase C
T2 channel
Phase C
T1 channel
Phase B
B2 channel
Phase B
B1 channel
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Phase B
T2 channel
Channel
12
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
Ttime_BT2
1
2
3
4
DT
5
CPU14
6
7
0
htB
B2_chan_B
1
2
T1_chan_B
T2_chan_B
3
B1a_chan_B
4
5
B1b_chan_B
currentB
6
7
0
Ttime_BB2
1
2
3
4
5
6
7
0
Ttime_CT1
1
2
3
4
5
6
7
0
Ttime_CT2
1
2
3
4
5
6
7
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3
2
1
0
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Detailed Function Description
Table 6. svmStdDtXor_T and svmStdDtXor_R Parameter RAM
Phase C
B2 channel
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Phase C
B1 channel
Channel
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
htC
B2_chan_C
1
2
T1_chan_C
T2_chan_C
3
B1a_chan_C
4
5
B1b_chan_C
currentC
6
7
0
Ttime_CB2
1
2
3
4
5
6
7
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3
2
1
0
13
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Table 7. svmStdDtXor_T and svmStdDtXor_R parameter description
Format
Description
Parameters written by CPU
Stator Reference Voltage Vector
Ualfa, Ubeta
16-bit fractional
components
0 ... positive current on phase A
currentA
0 or 1
1 ... negative current on phaseA
0 ... positive current on phase B
currentB
0 or 1
1 ... negative current on phaseB
0 ... positive current on phase C
currentC
0 or 1
1 ... negative current on phaseC
PWM period in number of TCR1
T
16-bit unsigned integer
TPU cycles
The number of PWM periods per
prescaler
16-bit unsigned integer
reload of new values
Dead-time in number of TCR1
DT
16-bit unsigned integer
TPU cycles
Time of 14 IMB clocks in TCR1
CPU14
16-bit unsigned integer
clocks.
sqrt(3)/2 = 0.866 = $6EDA
SQRT3
16-bit fractional
constant
address of synchronization
channel prescaler parameter:
$X4,
sync_presc_addr 8-bit unsigned integer
where X is synchronization
channel number.
$0 if no synchronization channel
is used.
Parameters written by both TPU and CPU
0 ... CPU can update variables
LD_OK
1-bit
1 ... TPU can read variables
CPU sets 1, TPU sets 0
Parameters written by TPU
The position of Stator Reference
Sector
16-bit unsigned integer
Voltage Vector in a sector. The
Sector can be 1, 2, 3, 4, 5 or 6
If fault channel is used, state of
fault pin:
fault_pinstate
0 or 1
0 ... low
1 ... high
Other parameters are just for TPU function inner use.
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Parameter
14
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Detailed Function Description
Performance
Table 8. svmStdDtXor_T State Statistics
State
ST
SF
Max IMB Clock Cycles
2
2
RAM Accesses by TPU
1
0
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Table 9. svmStdDtXor_R State Statistics
State
INIT
STOP
SFR0
SFR
C5
SFC0
SFC
NOTE:
Max IMB Clock Cycles
154
166
6
44
44
6
56
RAM Accesses by TPU
35
4
1
16
15
1
11
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
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SF ST
AT1
SF
SF
AT2
ST
ST
SF
ST
Phase A
C5
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AB1
SFR0
AB2
SF
BT1
SF ST
C5
ST
SF
SF
ST
BT2
ST
ST
SF
ST
Phase B
SFC0
BB1
SFR0
C5
C5
ST
BB2
SF
CT1
SF
ST
SF
SF
CT2
ST
ST
ST
SF
ST
Phase C
CB1
SFR
SFR
C5
flag1 = 1
SF
CB2
flag0 = 1
SFC SFC SFC SFC
C5
ST
SF
center_time
not a reload period
center_time
a reload period
T
T
ST
link service request
Figure 4. svmStdDtXor_T and svmStdDtXor_R timing
NOTE:
16
The R channel with the momentary earliest transition within the PWM period is
marked by a flag1 and runs the SFR and SFC states.
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Detailed Function Description
SF
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SF
ST
ST
ST
SF
ST
flag0 = 1
link
Figure 5. svmStdDtXor_T state diagram and 3 cases of timing
Which case happens is determined by the time when the link comes.
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SFR
SFC
4th-time
C5
3-times
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INIT
STOP
HSR = 10
HSR = 11
SFC0
C5
SFR0
flag1 = 0
flag1 = 1 – channel with momentary longest high-time
Figure 6. svmStdDtXor_R state diagram
Synchronization
signal for Standard
Space Vector
Modulation with
Dead-Time
Correction – XOR
version
(svmStdDtXor_sync)
18
The svmStdDtXor_sync TPU function uses information obtained from
StdDtXor_R and svmStdDtXor_T functions, the actual PWM center times and
the PWM periods. This allows a signal to be generated, which tracks the
changes in the PWM period and is always synchronized with the PWM. The
synchronization signal is a positive pulse generated repeatedly after the
prescaler or presc_copy PWM periods (see next paragraph). The low to high
transition of the pulse can be adjusted by a parameter, either negative or
positive, to go a number of TCR1 TPU cycles before or after the PWM period
center time. The pulse width pw is another synchronization signal parameter.
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Detailed Function Description
.
move > 0
prescaler = 1
pw
|move|
center_time
center_time
T
T
move < 0
prescaler = 2
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pw
|move|
center_time
center_time
center_time
T
T
T
Figure 7. Synchronization signal adjustment examples
Synchronized Change
of PWM Prescaler
And Synchronization
Signal Prescaler
The svmStdDtXor_sync TPU function actually uses the presc_copy parameter
instead of the prescaler parameter. The prescaler parameter holds the
prescaler value that is copied to the presc_copy by the svmStdDtXor_bottom
function at the time the PWM parameters are reloaded. This ensures that new
prescaler values for the PWM signals, as well as the synchronization signal, are
applied at the same time. Write the synchronization signal prescaler parameter
address to the sync_presc_addr parameter to enable this mechanism. Write 0
to disable it, and remember to set the synchronization signal presc_copy
parameter instead of the prescaler parameter in this case.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 10. svmStdDtXor_sync Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
Options
svmStdDtXor_sync function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
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Table 10. svmStdDtXor_sync Control Bits
Name
1
0
Host Service Bits (HSR)
1
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
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Options
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
TPU function svmStdDtXor_sync generates an interrupt after each low to high
transition.
Table 11. svmStdDtXor_sync Parameter RAM
Synchronization channel
Channel
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
pw
1
prescaler
2
3
presc_copy
time
4
dec
5
6
T_copy
5
4
3
2
1
0
7
Table 12. svmStdDtXor_sync parameter description
Parameter
move
pw
20
Format
Description
Parameters written by CPU
The number of TCR1 TPU cycles to
forego (negative) or come after
16-bit signed integer
(positive) the PWM period center
time
Synchronization pulse width in
16-bit unsigned integer
number of TCR1 TPU cycles.
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Detailed Function Description
Table 12. svmStdDtXor_sync parameter description
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Parameter
Description
The number of PWM periods per
synchronization pulse
prescaler
16-bit unsigned integer
– use in case of synchronized
prescalers change
The number of PWM periods per
synchronization pulse
presc_copy
16-bit unsigned integer
– use in case of asynchronized
prescalers change
Parameters written by TPU
Other parameters are just for TPU function inner use.
Performance
Format
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
move <
T
4
Table 13. svmStdDtXor_sync State Statistics
State
INIT
S1
S2
S3
NOTE:
S1
Max IMB Clock Cycles
12
12
8
16
RAM Accesses by TPU
5
6
3
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S2
S3
S1
center_time
center_time
center_time
T
T
T
S2
Figure 8. svmStdDtXor_sync timing
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HSR = 10
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INIT
S1
S3
S2
Figure 9. svmStdDtXor_sync state diagram
Resolver Reference
Signal for Standard
Space Vector
Modulation with
Dead-Time
Correction – XOR
version
(svmStdDtXor_res)
The svmStdDtXor_res TPU function uses information read from the
StdDtXor_R and svmStdDtXor_T functions, the actual PWM center times and
the PWM periods. This allows a signal to be generated, which tracks the
changes of the PWM period and is always synchronized with the PWM. The
resolver reference signal is a 50% duty-cycle signal with a period equal to
prescaler or synchronization channel presc_copy PWM periods (see next
paragraph). The low to high transition of the pulse can be adjusted by a
parameter, either negative or positive, to go a number of TCR1 TPU cycles
before or after the PWM period center time.
move > 0
prescaler = 1
|move|
center_time
center_time
T
T
center_time
center_time
center_time
T
T
T
move < 0
prescaler = 2
|move|
Figure 10. Resolver reference signal adjustment examples
22
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Detailed Function Description
Synchronized Change
of PWM Prescaler
And Resolver
Reference Signals
Prescaler
The svmStdDtXor_res TPU function can inherit the Synchronization Signal
prescaler that is synchronously changed with the PWM prescaler. Write the
synchronization signals presc_copy parameter address to the presc_addr
parameter to enable this mechanism. Write 0 to disable it, and in this case set
the prescaler parameter to directly specify prescaler value.
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Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 14. svmStdDtXor_res Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
svmStdDtXor_res function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
0
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Table 15. svmStdDtXor_res Parameter RAM
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
1
2
presc_addr
3
prescaler
time
4
dec
5
6
T_copy
7
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Resolver
Channel
5
4
3
2
1
0
Table 16. svmStdDtXor_res parameter description
Parameter
move
presc_addr
Format
Description
Parameters written by CPU
The number of TCR1 TPU cycles to
forego (negative) or come after
16-bit signed integer
(positive) the PWM period center
time
$00X6, where X is a number of
Synchronization Signal channel, to
inherit Sync. channel prescaler
or
16-bit unsigned integer
$0000 to enable direct specification
of prescaler value in prescaler
parameter
The number of PWM periods per
synchronization pulse
– use when apresc_addr = 0
Parameters written by TPU
Other parameters are just for TPU function inner use.
prescaler
Performance
1, 2, 4, 6, 8, 10, 12, 14, ...
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
move <
T
4
Table 17. svmStdDtXor_res State Statistics
State
INIT
24
Max IMB Clock Cycles
12
RAM Accesses by TPU
5
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Table 17. svmStdDtXor_res State Statistics
State
S1
S3
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NOTE:
Max IMB Clock Cycles
26
18
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S3
S1
RAM Accesses by TPU
9
7
S1
center_time
center_time
center_time
T
T
T
Figure 11. svmStdDtXor_res timing
HSR = 10
INIT
S1
S3
Figure 12. svmStdDtXor_res state diagram
Fault Input for
Standard Space
Vector Modulation
with Dead-Time
Correction – XOR
version
(svmStdDtXor_fault)
The svmStdDtXor_fault is an input TPU function that monitors the pin, and if a
high to low transition occurs, immediately sets all PWM channels low and
cancels all further transitions on them. The PWM channels, as well as the
synchronization and resolver reference signal channels (if used), have to be
initialized again to start them running.
The function returns the actual pinstate as a value of 0 (low) or 1 (high) in the
parameter fault_pinstate. The parameter is placed on the AT1 channel to keep
the fault channel parameter space free.
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Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 18. svmStdDtXor_fault Control Bits
Name
3
2
1
0
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Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
svmStdDtXor_fault function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
0
TPU function svmStdDtXor_fault generates an interrupt when a high to low
transition appears.
Table 19. svmStdDtXor_fault Parameter RAM
Fault input
Channel
26
Parameter 15 14 13 12 11 10 9
0
1
2
3
4
5
6
7
8
7
6
Standard SVM with Dead-Time Correction – XOR version (svmStdDtXor)
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5
4
3
2
1
0
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Detailed Function Description
Table 20. svmStdDtXor_fault parameter description
Parameter
fault_pinstate
Format
Description
Parameters written by TPU
State of fault pin:
0 or 1
0 ... low
1 ... high
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Performance
Table 21. svmStdDtXor_fault State Statistics
State
INIT
FAULT
NO_FAULT
NOTE:
Max IMB Clock Cycles
8
172
4
RAM Accesses by TPU
2
5
1
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
NO_FAULT
FAULT
Figure 13. svmStdDtXor_fault timing
HSR = 10
INIT
FAULT
NO_FAULT
Figure 14. svmStdDtXor_fault state diagram
Standard SVM with Dead-Time Correction – XOR version (svmStdDtXor)
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AN2531/D
Rev. 0
5/2003
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