BLDC Motor version I TPU Function Set

Freescale Semiconductor, Inc.
Application Note
AN2520/D
Rev. 0, 5/2003
BLDC Motor version I TPU
Function Set (BLDCm)
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By Milan Brejl, Ph.D.
Functional Overview
BLDC Motor version I (BLDCm) TPU function drives a Brush less DC Motor by
decoding the Hall sensor signals and generating 3-phase complementaryswitched center-aligned PWM signals. The state of the incoming Hall sensor
signals is decoded into a position of the motion control system. Based on this,
two of three phases generate the PWM signal while the third phase is switched
off (see Figure 1). This way the TPU drives the motor independently of CPU.
The CPU just sets a dc parameter in range (–1,1), which determines both the
speed and the direction.
The function set consists of 5 TPU functions:
•
3-phase Hall Sensor Decoder for BLDC Motor (BLDCm_3HD)
•
BLDC Motor (BLDCm)
•
Synchronization Signal for BLDC Motor (BLDCm_sync)
•
Resolver Reference Signal for BLDC Motor (BLDCm_res)
•
Fault Input for BLDC Motor (BLDCm_fault)
Q1
Q2
Q3
Q4
Q5
Q6
Phase A
Phase B
Phase C
Fault input signal
Synchronization signal
Resolver reference signal
Figure 1. Signals processed by BLDCm TPU function set
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The BLDCm_3HD function receives the Hall Sensor signals and controls the
commutation of 3 PWM phases. The BLDCm TPU functions generate a 6channel 3-phase center-aligned PWM signal with dead-time between the top
and bottom channels. One of the phases is always switched off while the other
two generate the PWM signal. The Synchronization Signal for BLDCm function
can be used to generate one or more adjustable signals for a wide range of
uses, which are synchronized to the PWM, and track changes in the PWM
period. The Resolver Reference Signal for the BLDCm function can be used to
generate one or more 50% duty-cycle adjustable signals that are also
synchronized to the PWM.The Fault Input for BLDCm function is a TPU input
function that sets all PWM outputs low when the input signal goes low. See
Figure 1.
Function Set Configuration
None of the TPU functions in the BLDC Motor TPU function set can be used
separately. The BLDCm_3HD and BLDCm functions have to be used together.
The BLDCm_3HD is used on 3 input channels. The BLDCm on 6 output
channels, and within each phase, the top channel has to be assigned on a
lower TPU channel than the bottom channel. One or more channels running the
Synchronization Signal for BLDCm as well as Resolver Reference Signals for
BLDCm functions can be added. They can run with different settings on each
channel. The function Fault Input for BLDCm can also be added. It is
recommended to use it on channel 15, and to set the hardware option that
disables all TPU output pins when the channel 15 input signal is low (DTPU bit
= 1). This ensures that the hardware reacts quickly to a pin fault state. Note that
it is not only the PWM channels, but all TPU output channels, including the
synchronization signals, that are disabled in this configuration.
Table 1 shows the configuration options and restrictions.
Table 1. BLDCm TPU function set configuration options and restrictions
BLDCm_3HD
Optional/
Mandatory
mandatory
BLDCm
mandatory
TPU function
2
BLDCm_sync
BLDCm_res
optional
optional
BLDCm_fault
optional
How many
Assignable channels
channels
3
any 3 channels
any 6 channels,
Q1 on a lower TPU channel than Q2,
6
Q3 on a lower TPU channel than Q4,
Q5 on a lower TPU channel than Q6
1 or more any channels
1 or more any channels
any, recommended is 15 and DTPU bit
1
set
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Function Set Configuration
Table 2 shows an example of configuration.
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Table 2. Example of configuration
Channel
0
1
2
3
4
5
6
7
8
10
15
TPU function
BLDCm
BLDCm
BLDCm
BLDCm
BLDCm
BLDCm
BLDCm_3HD
BLDCm_3HD
BLDCm_3HD
BLDCm_sync
BLDCm_fault
Priority
high
high
high
high
high
high
high
high
high
low
high
Table 3 shows the TPU function code sizes.
Table 3. TPU function code sizes.
TPU function
BLDCm_3HD
BLDCm
BLDCm_sync
BLDCm_res
BLDCm_fault
Configuration Order
Code size
61 µ instructions + 8 entries = 69 long words
213 µ instructions + 8 entries = 221 long words
26 µ instructions + 8 entries = 34 long words
38 µ instructions + 8 entries = 46 long words
9 µ instructions + 8 entries = 17 long words
The CPU configures the TPU as follows.
1. Disables the channels by clearing the two channel priority bits on each
channel used (not necessary after reset).
2. Selects the channel functions on all used channels by writing the
function numbers to the channel function select bits.
3. Initializes function parameters. The parameters PinAddrPrev_A,
PinAddrNext_A, PinAddrPrev_B, PinAddrNext_B, T, DT, MPW and
sync_presc_addr must be set before initialization. If a BLDCm_sync
channel or a BLDCm_res channel is used, then also its parameters must
be set before initialization.
4. Issues an HSR (Host Service Request) type %10 to all BLDCm_3HD
channels, to initialize them, and to one of the BLDCm_bottom channels
to initialize all PWM channels. Issues an HSR type %10 to the
BLDCm_sync channels, BLDCm_res channels and BLDCm_fault
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channel, if used.
5. Enables servicing by assigning a high, middle or low priority to the
channel priority bits. All Hall sensor channels, as well as all PWM
channels, must be assigned the same priority to ensure correct
operation. The CPU must ensure that BLDCm_bottom (which actually
initializes all PWM channels) is initialized after the initialization of
BLDCm_3HD, and that the BLDCm_sync or BLDCm_res function is
initialized even after the initialization of BLDCm_bottom:
–
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–
–
–
–
NOTE:
assign a priority to the Phase A, Phase B and Phase C Hall sensor
channels to enable their initialization
wait until the HSR bits are cleared to indicate that initialization of
these channels has completed
assign a priority to the PWM channels to enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the PWM channels has completed and
assign a priority to the BLDCm_sync or BLDCm_res channel to
enable its initialization
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
Detailed Function Description
3-phase Hall Sensor
Decoder for BLDC
Motor
(BLDCm_3HD)
The BLDCm_3HD operates on three channels and processes the incoming
Hall sensor signals. As a result of this processing, the Sector parameter gets a
value that reflects the position of a motion system in one of six sectors. The
state of the Hall sensor signals and the corresponding Sector value is listed in
Table 4.
Table 4. Hall sensor signal states and corresponding Sector value
Phase A
1
1
0
0
0
1
0
1
Phase B
0
1
1
1
0
0
0
1
Phase C
0
0
0
1
1
1
0
1
Sector
4
6
2
3
1
5
0
7
A Sector value of 0 or 7 indicates an illegal state of the Hall sensor signals.
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Detailed Function Description
The Sector value history determines the direction of the motion system. The
Direction parameter can be assigned a value of 0 or 1. See Table 5.
Table 5. Sector value sequence and corresponding Direction value
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Sector value sequence
4, 6, 2, 3, 1, 5, 4, ...
4, 5, 1, 3, 2, 6, 4, ...
Direction
0
1
The Period value is calculated each time the sector is changed. The Period
value is the TCR time of last revolution. It is measured from the last edge of
similar type (low-high / high-low), on the same channel, to the current edge –
see Figure 2. This method eliminates inaccuracies in the Hall sensor signals.
The Period parameter does not contain a valid value during the first revolution
after initialization, or after a change of direction.
Phase A
Phase B
Phase C
Sector
3
Direction
Revolution
Counter
1
Period
2
6
4
5
1
3
2
6
4
-1
5
1
3
2
6
4
-1
Period
3
2
6
4
-1
Period
Period
Period
1
-1
Period
Period
5
Period
Period
Period
Period
Period
Period
Period
Period
Period
Period
Period
Figure 2. Hall sensor signals and corresponding values
2 function modes are provided:
•
TCR1 clock selected
•
TCR2 clock selected
The selected mode is determined by the HSQ bit 1. The user has to select the
same mode on all channels.
The function provides interpolation support. The parameters LastEdgeT and
ActualT are updated on a Host Service Request HSR = 11. LastEdgeT then
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has the value of the last incoming edge time in TCR clocks and ActualT has the
current value of the TCR clock.
The CPU program should use 32-bit reads to ensure coherency of the two
parameters. This applies to coherent reads of LastEdgeT and ActualT as well
as the Sector and TCR_VALUE, which is necessary for interpolation
calculations.
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Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 6. BLDCm_3HD Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
0
Host Sequence Bits (HSQ)
0
Options
BLDCm_3HD function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Get LastEdgeT and ActualT
x0 – Phase A or Phase B
x1 – Phase C
0x – TCR1 clock selected
1x – TCR2 clock selected
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
TPU function BLDCm_3HD generates an interrupt each time the Sector is
changed.
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Detailed Function Description
Table 7. BLDCm_3HD Parameter RAM
Phase B
Phase C
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Phase A
Channel
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
1
2
3
PinAdrPrev_A
PinAdrNext_A
4
PINSTATE_A
5
6
EdgeT_LH_A
EdgeT_HL_A
7
0
LastEdgeT
ActualT
1
2
3
PinAdrPrev_B
PinAdrNext_B
4
PINSTATE_B
5
6
EdgeT_LH_B
EdgeT_HL_B
7
0
Direction
1
RC
TCR_VALUE
2
Sector
3
4
Period
PINSTATE_C
5
EdgeT_LH_C
6
7
EdgeT_HL_C
4
3
2
1
0
Table 8. BLDCm_3HD parameter description
Parameter
PinAdrPrev_A
PinAdrNext_A
PinAdrPrev_B
PinAdrNext_B
RC
LastEdgeT
Format
Description
Parameters written by CPU
$00XA, where X is a number
16-bit unsigned integer
of Phase C channel
$00XA, where X is a number
16-bit unsigned integer
of Phase B channel
$00XA, where X is a number
16-bit unsigned integer
of Phase A channel
$00XA, where X is a number
16-bit unsigned integer
of Phase C channel
Parameters written by both TPU and CPU
16-bit signed integer
Revolution Counter value
Parameters written by TPU
16-bit unsigned integer
TCR time of last transition *
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Table 8. BLDCm_3HD parameter description
Parameter
ActualT
Format
16-bit unsigned integer
Direction
0 or 1
TCR_VALUE
16-bit unsigned integer
Sector
4, 6, 2, 3, 1 or 5
Period
16-bit unsigned integer
Description
Actual TCR time *
Direction
0 – Sector sequence
4, 6, 2, 3, 1, 5, 4, ...
1 – Sector sequence
4, 5, 1, 3, 2, 6, 4, ...
TCR time of last transition
Sector: position in one of six
sectors
Period: time of last revolution
in TCR clocks.
The actual state of the pin is
$0001 – high,
$0000 – low
PINSTATE_A
PINSTATE_B
$0000 or $0001
PINSTATE_C
EdgeT_LH_A
TCR time of last low-high
EdgeT_LH_B
16-bit unsigned integer
transition
EdgeT_LH_C
EdgeT_HL_A
TCR time of last high-low
EdgeT_HL_B
16-bit unsigned integer
transition
EdgeT_HL_C
* The parameter values are entered by TPU on Host Service Request 11 (Get
LastEdgeT and ActualT).
Performance
Table 9. BLDCm_3HD State Statistics
State
INIT
GET_TIME
LH1
HL1
LH2
HL2
NOTE:
8
Max IMB Clock Cycles
22
8
28
28
32
32
RAM Accesses by TPU
5
3
12
12
13
13
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
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Detailed Function Description
Phase A
HL1
LH1
Phase B
Phase C
HL1
LH1
HL2
HL1
LH1
LH2
HL1
LH1
HL2
HL1
LH1
GET
TIME
LH2
HL1
LH1
HL2
HL1
LH1
LH2
LH1
HL1
LH1
HL2
LH2
HL2
HSR 11
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Figure 3. BLDCm_3HD timing
LH2
H L2
G E T _ T IM E
IN IT
LH1
H SR = 10
H S R = 11
H L1
Figure 4. BLDCm_3HD state diagram
Noise Immunity
The input signals can be disturbed by an impulse noise. The TPU hardware
rejects short input pulses of less than a configurable number of IMB clocks.
Longer pulses are processed by the TPU. Furthermore the function itself uses
a pin history to reject short error pulses that are long enough to get through the
hardware filter, but not long enough to last from the actual transition time to the
time that the TPU services the channel. Even longer error pulses are counted
on both edges, resulting in a short-time error of the Sector value.
BLDC Motor
(BLDCm)
The BLDCm TPU function generates a 6-channel, 3-phase PWM signal, with
dead-time between the top and bottom channels. In order to charge the
bootstrap transistors, the PWM signals start to run 1.6ms after their initialization
(at 20MHz TCR1 clock). The functions generate signals corresponding to value
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of 0 for duty-cycle ratio dc until the first dc value is processed. This accures for
at least one PWM period.
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One of the phases is always switched off while the other two generate the PWM
signal. Which phase is switched off, depends on which one of the six sectors
the rotor is positioned in. The position is decoded from the Hall sensor signals.
The CPU controls the PWM output by setting the TPU parameters. The dutycycle ratio dc and PWM period T can be adjusted during run time. Conversely,
dead-time (DT) and minimum pulse width (MPW) are not supposed to be
changed during run time. The duty-cycle ratio dc can gain a value in the range
(–1, 1). The sign controls the motion system direction, while the absolute value
controls the amplitude of the applied voltage.
The following figures show the input dc value and corresponding output PWM
signals (valid for sector 4, direction 0):
dc = - 0.5
dc = 0
dc = 0.5
PWM period
PWM period
PWM period
center-time
center-time
DT
DT
DT
center-time
DT
DT
DT
Q1
Q2
DT
DT
DT
DT
DT
DT
Q3
Q4
motor
voltage
Figure 5. Unipolar switching
The following equations describe how the PWM signal transition times T1p,
T2p, B1p, B2p, T1m, T2m, B1m, B2m are calculated, and how they are
assigned to each channel transition time tLH and tHL based on BLDCm
commutation rules:
Tdc
10
α
= T ⋅ dc
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Detailed Function Description
T + Tdc
2
T − Tdc
Y =
2
X=
Y − DT
2
Y + DT
D =
2
X − DT
2
X + DT
B=
2
C =
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A=
T1p = center _ time − A
B1p = center _ time − B
T2p = center _ time + A
B2p = center _ time + B
T1m = center _ time − C
B1m = center _ time − D
T2m = center _ time + C
B2m = center _ time + D
Table 10. Assignment of the calculated transition times to each channel transition times tLH and
tHL based on the BLDCm commutation rules
Sector
Channel
4
6
Q1
t LH = T1p
t LH = T1p
t HL = T2p
t HL = T2p
Q2
t LH = B2p
t LH = B2p
t HL = B1p
t HL = B1p
Q3
t LH = T1m
Q4
t LH = B2p
t HL = T2m
t HL = B1p
2
OFF
OFF
3
1
t LH = T1m
t LH = T1m
t HL = T2m
t HL = T2m
t LH = B2p
t LH = B2p
t HL = B1p
t HL = B1p
OFF
t LH = T1p
t LH = T1p
t HL = T2p
t HL = T2p
OFF
t LH = B2p
t LH = B2p
t HL = B1p
t HL = B1p
Q5
OFF
t LH = T1m
t LH = T1m
t HL = T2m
t HL = T2m
Q6
OFF
t LH = B2p
t LH = B2p
t HL = B1p
t HL = B1p
5
OFF
OFF
OFF
t LH = T1m
OFF
t LH = B2p
t HL = T2m
t HL = B1p
OFF
t LH = T1p
t LH = T1p
t HL = T2p
t HL = T2p
OFF
t LH = B2p
t LH = B2p
t HL = B1p
t HL = B1p
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Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 11. BLDCm Control Bits
Name
3
2
1
0
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Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
BLDCm function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Stop
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
0
Table 12. BLDCm Parameter RAM
Q1
Channel
12
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
LHtime_Q1
1
HLtime_Q1
other_ch_Q1
2
C
3
4
Q120_chans
dc
5
6
7
fault_pinstate
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3
2
1
0
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Detailed Function Description
Table 12. BLDCm Parameter RAM
Q3
Q4
Q5
Q6
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Q2
Channel
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
LHtime_Q2
HLtime_Q2
1
2
Tdc
center_time
3
old_idle_ch
4
5
DT
6
7
0
LHtime_Q3
HLtime_Q3
1
2
other_ch_Q3
D
3
Q340_chans
4
5
T
6
7
0
LHtime_Q4
HLtime_Q4
1
T_copy
2
3
plus_ch
4
5
MPW
6
7
0
LHtime_Q5
1
HLtime_Q5
other_ch_Q5
2
minus_ch
3
4
Q560_chans
5
sync_presc_addr
6
7
0
LHtime_Q6
HLtime_Q6
1
2
L
idle_ch
3
4
5
6
7
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3
2
1
0
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Table 13. BLDCm parameter description
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Parameter
Format
Description
Parameters written by CPU
duty-cycle ratio in the range
dc
16-bit fractional
<–1,1)
PWM period in number of TCR1
T
16-bit unsigned integer
TPU cycles
Dead-time in number of TCR1
DT
16-bit unsigned integer
TPU cycles
Minimum pulse width in number of
MPW
16-bit unsigned integer
TCR1 TPU cycles. See
Performance for details.
address of synchronization
channel prescaler parameter:
$X4,
sync_presc_addr 8-bit unsigned integer
where X is synchronization
channel number.
$0 if no synchronization channel
is used.
Parameters written by TPU
If fault channel is used, state of
fault pin:
fault_pinstate
0 or 1
0 ... low
1 ... high
Other parameters are just for TPU function inner use.
Performance
Table 14. BLDCm State Statistics
State
INIT
STOP
C10
C1
C1ACH
C20
C2
C2STC
LH
HL
Max IMB Clock Cycles
168
38
6
84
50
16
58
58
2
12
RAM Accesses by TPU
47
0
1
14
11
2
22
10
1
2
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
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Detailed Function Description
PWM period
Q1
flag0 set
C1
ACH
C20
C1
ACH
C20
Q2
LH
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Q3
flag0 set
HL
C10
C2
LH
HL
STC
Q4
LH
HL
Q5
C10
flag0 set
C2
STC
Q6
LH
HL
flag1 set
flag2 set
Figure 6. BLDCm timing
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INIT
C1ACH
C2STC
C1
C2
LH
HL
STOP
HSR = 10
HSR = 11
Figure 7. BLDCm state diagram
Minimum Pulse Width
The TPU cannot generate PWM signals with duty cycle ratios very close to 0%
or 100%. It is the case when the dc value is close to 1 or –1. The minimum pulse
width that the TPU can be guaranteed to correctly generate is determined by
the TPU function itself and by the activity on the other channels. When the TPU
function is requested to generate a narrower pulse a collision can occur. To
prevent this, the parameter MPW (minimum pulse width) is introduced. The
TPU function BLDCm limits the narrowest generated pulse widths to MPW. The
CPU program should check the maximum absolute value of dc to avoid this
limitation, or take account of the non-linear performance when dc moves
towards the boundary values and the limitation is exhibited by the TPU. The
maximum absolute value of dc should satisfy:
dc ≤ 1 −
2( MPW + DT )
T
The MPW is written by the CPU. The MPW depends on the whole TPU unit
configuration, especially the lengths of the longest states of other functions,
and their priorities, running on the same TPU. The MPW has to be correctly
calculated at the time the whole TPU unit is configured.
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LH
TST
time slot
sequence
TST
TST
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Detailed Function Description
LH2
C10
MPW
DT
DT
Q1
C10
LH
LH2
Phase A
latency
LH
LH2
TST
time slot
sequence
TST
Figure 8. Worst case timing – case one
TST
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Q2
C10
MPW
DT
DT
Q1
C10
Q2
LH
Phase A
LH2
latency
Figure 9. Worst case timing – case two
BLDC Motor version I TPU Function Set (BLDCm)
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The minimum pulse width can be calculated according to Figure 8 or Figure 9.
These illustrate two possible worst cases of timing in the case when only
compulsory BLDCm functions are running on one TPU (BLDCm and
BLDCm_3HD). The worst case happens when a transition on one of the Hall
sensor signals is detected and processed during the shortest pulse on a PWM
channel. Each state is preceded by the Time Slot Transition (TST), which takes
10 or 14 IMB clock cycles.
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According to the Figure 8 the MPW is 70 IMB clock cycles – DT. According to
Figure 9 the MPW is 58 IMB clock cycles. In summary the MPW parameter
value is equal to 70 IMB clock cycles – DT, and has a minimum value of at least
58 IMB clock cycles.
Note that the MPW, as well as the DT, are not entered into the parameter
RAM in IMB clock cycles, but in TCR1 clock cycles. It is recommended for
the BLDCm function that the TCR1 clock is configured for its maximum speed,
which is the IMB clock divided by 2. In this case the MPW = 35 – DT, with a
minimum value of 29.
When other functions are running concurrently on the same TPU, the longest
state of each function with its time-slot transition can increase the calculated
MPW value. The BLDCm_fault function does not affect the MPW. The
BLDCm_sync, if used, increase the MPW value by 22 (44 IMB clock cycles).
The BLDCm_res, if used, increase the MPW value by 20 (40 IMB clock cycles).
If a lower value than the one calculated, is set for the MPW parameter, the
motion system can run with a higher motor voltage amplitude, but with a risk,
that the dead-time is not maintained.
It is also possible to use the Worst-Case Latency (WCL), which is automatically
calculated by the MPC500_Quick_Start Graphical Configuration Tool. It can
serve as a good approximation of MPW. The calculated WCL is always longer
than the real-case is. Let the WCL be calculated after the configuration of TPU
channels and then find the longest WCL value within all BLDCm PWM
channels. Convert the number, from IMB clock cycles to TCR1 clock cycles, to
get the MPW.
Synchronization
signal for BLDC
Motor
(BLDCm_sync)
18
The BLDCm_sync TPU function uses information obtained from BLDCm PWM
functions, the actual PWM center times and the PWM periods. This allows a
signal to be generated, which tracks the changes in the PWM period and is
always synchronized with the PWM. The synchronization signal is a positive
pulse generated repeatedly after the prescaler or presc_copy PWM periods
(see next paragraph). The low to high transition of the pulse can be adjusted
by a parameter, either negative or positive, to go a number of TCR1 TPU cycles
before or after the PWM period center time. The pulse width pw is another
synchronization signal parameter.
BLDC Motor version I TPU Function Set (BLDCm)
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Detailed Function Description
move > 0
prescaler = 1
pw
|move|
center_time
center_time
T
T
move < 0
prescaler = 2
Freescale Semiconductor, Inc...
pw
|move|
center_time
center_time
center_time
T
T
T
Figure 10. Synchronization signal adjustment examples
Synchronized Change
of PWM Prescaler
And Synchronization
Signal Prescaler
The BLDCm_sync TPU function actually uses the presc_copy parameter
instead of the prescaler parameter. The prescaler parameter holds the
prescaler value that is copied to the presc_copy by the BLDCm_bottom
function at the time the PWM parameters are reloaded. This ensures that new
prescaler values for the PWM signals, as well as the synchronization signal, are
applied at the same time. Write the synchronization signal prescaler parameter
address to the sync_presc_addr parameter to enable this mechanism. Write 0
to disable it, and remember to set the synchronization signal presc_copy
parameter instead of the prescaler parameter in this case.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 15. BLDCm_sync Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
Options
BLDCm_sync function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
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Table 15. BLDCm_sync Control Bits
Name
1
0
Host Service Bits (HSR)
1
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
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Options
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
TPU function BLDCm_sync generates an interrupt after each low to high
transition.
Table 16. BLDCm_sync Parameter RAM
Synchronization channel
Channel
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
1
pw
prescaler
2
presc_copy
3
4
time
dec
5
T_copy
6
5
4
3
2
1
0
7
Table 17. BLDCm_sync parameter description
Parameter
move
pw
20
Format
Description
Parameters written by CPU
The number of TCR1 TPU cycles to
forego (negative) or come after
16-bit signed integer
(positive) the PWM period center
time
Synchronization pulse width in
16-bit unsigned integer
number of TCR1 TPU cycles.
BLDC Motor version I TPU Function Set (BLDCm)
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Detailed Function Description
Table 17. BLDCm_sync parameter description
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Parameter
Description
The number of PWM periods per
synchronization pulse
prescaler
16-bit unsigned integer
– use in case of synchronized
prescalers change
The number of PWM periods per
synchronization pulse
presc_copy
16-bit unsigned integer
– use in case of asynchronized
prescalers change
Parameters written by TPU
Other parameters are just for TPU function inner use.
Performance
Format
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
move <
T
4
Table 18. BLDCm_sync State Statistics
State
INIT
S1
S2
S3
NOTE:
S1
Max IMB Clock Cycles
12
12
8
16
RAM Accesses by TPU
5
6
3
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S2
S3
S1
center_time
center_time
center_time
T
T
T
S2
Figure 11. BLDCm_sync timing
BLDC Motor version I TPU Function Set (BLDCm)
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HSR = 10
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INIT
S1
S3
S2
Figure 12. BLDCm_sync state diagram
Resolver Reference
Signal for BLDC
Motor (BLDCm_res)
The BLDCm_res TPU function uses information read from the BLDCm PWM
functions, the actual PWM center times and the PWM periods. This allows a
signal to be generated, which tracks the changes of the PWM period and is
always synchronized with the PWM. The resolver reference signal is a 50%
duty-cycle signal with a period equal to prescaler or synchronization channel
presc_copy PWM periods (see next paragraph). The low to high transition of
the pulse can be adjusted by a parameter, either negative or positive, to go a
number of TCR1 TPU cycles before or after the PWM period center time.
move > 0
prescaler = 1
|move|
center_time
center_time
T
T
center_time
center_time
center_time
T
T
T
move < 0
prescaler = 2
|move|
Figure 13. Resolver reference signal adjustment examples
22
BLDC Motor version I TPU Function Set (BLDCm)
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Detailed Function Description
Synchronized Change
of PWM Prescaler
And Resolver
Reference Signals
Prescaler
The BLDCm_res TPU function can inherit the Synchronization Signal prescaler
that is synchronously changed with the PWM prescaler. Write the
synchronization signals presc_copy parameter address to the presc_addr
parameter to enable this mechanism. Write 0 to disable it, and in this case set
the prescaler parameter to directly specify prescaler value.
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 19. BLDCm_res Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
BLDCm_res function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
0
Table 20. BLDCm_res Parameter RAM
Channel
Resolver
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Host Interface
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
1
2
presc_addr
3
prescaler
time
4
dec
5
6
T_copy
7
BLDC Motor version I TPU Function Set (BLDCm)
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4
3
2
1
0
23
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Table 21. BLDCm_res parameter description
Parameter
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move
presc_addr
Format
Description
Parameters written by CPU
The number of TCR1 TPU cycles to
forego (negative) or come after
16-bit signed integer
(positive) the PWM period center
time
$00X6, where X is a number of
Synchronization Signal channel, to
inherit Sync. channel prescaler
or
16-bit unsigned integer
$0000 to enable direct specification
of prescaler value in prescaler
parameter
The number of PWM periods per
synchronization pulse
– use when apresc_addr = 0
Parameters written by TPU
Other parameters are just for TPU function inner use.
prescaler
Performance
1, 2, 4, 6, 8, 10, 12, 14, ...
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
move <
T
4
Table 22. BLDCm_res State Statistics
State
INIT
S1
S3
NOTE:
S1
Max IMB Clock Cycles
12
26
18
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S3
S1
center_time
center_time
center_time
T
T
T
Figure 14. BLDCm_res timing
24
RAM Accesses by TPU
5
9
7
BLDC Motor version I TPU Function Set (BLDCm)
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Detailed Function Description
HSR = 10
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INIT
S3
S1
Figure 15. BLDCm_res state diagram
Fault Input for BLDC
Motor
(BLDCm_fault)
The BLDCm_fault is an input TPU function that monitors the pin, and if a high
to low transition occurs, immediately sets all PWM channels low and cancels
all further transitions on them. The PWM channels, as well as the
synchronization and resolver reference signal channels (if used), have to be
initialized again to start them running.
The function returns the actual pinstate as a value of 0 (low) or 1 (high) in the
parameter fault_pinstate. The parameter is placed on the Q1 channel to keep
the fault channel parameter space free.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 23. BLDCm_fault Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
Options
BLDCm_fault function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
BLDC Motor version I TPU Function Set (BLDCm)
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Table 23. BLDCm_fault Control Bits
Name
1
0
Host Service Bits (HSR)
1
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
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Options
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
TPU function BLDCm_fault generates an interrupt when a high to low transition
appears.
Table 24. BLDCm_fault Parameter RAM
Fault input
Channel
Parameter 15 14 13 12 11 10 9
0
1
2
3
4
5
6
7
8
7
6
5
4
3
Table 25. BLDCm_fault parameter description
Parameter
fault_pinstate
26
Format
Description
Parameters written by TPU
State of fault pin:
0 or 1
0 ... low
1 ... high
BLDC Motor version I TPU Function Set (BLDCm)
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1
0
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Detailed Function Description
Performance
Table 26. BLDCm_fault State Statistics
State
INIT
FAULT
NO_FAULT
Freescale Semiconductor, Inc...
NOTE:
Max IMB Clock Cycles
8
44
4
RAM Accesses by TPU
2
1
1
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
NO_FAULT
FAULT
Figure 16. BLDCm_fault timing
HSR = 10
INIT
FAULT
NO_FAULT
Figure 17. BLDCm_fault state diagram
BLDC Motor version I TPU Function Set (BLDCm)
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