4.5 Ω RON, 4-/8-Channel ±5 V,+12 V, +5 V, and +3.3 V Multiplexers ADG1608/ADG1609 FEATURES FUNCTIONAL BLOCK DIAGRAMS 4.5 Ω typical on resistance 1 Ω on-resistance flatness Up to 470 mA continuous current ±3.3 V to ±8 V dual-supply operation 3.3 V to 16 V single-supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead, 3 mm × 3 mm LFCSP ADG1608 S1 D S8 APPLICATIONS A0 A1 A2 EN 08318-001 1-OF-8 DECODER Figure 1. Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements ADG1609 S1A DA S4A S1B DB S4B A0 A1 EN 08318-002 1-OF-4 DECODER Figure 2. GENERAL DESCRIPTION The ADG1608/ADG1609 are monolithic CMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG1608 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, A0, A1, and A2. The ADG1609 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. The low on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distortion is critical. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. PRODUCT HIGHLIGHTS CMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. 1. 2. 3. 4. 5. 6. 8 Ω maximum on resistance over temperature. Minimum distortion: THD + N = 0.04% 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <8 nW. 16-lead TSSOP and 16-lead, 3 mm × 3 mm LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADG1608/ADG1609 TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, S or D ..................................7 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 Functional Block Diagrams ............................................................. 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................9 Product Highlights ........................................................................... 1 Typical Performance Characteristics ........................................... 11 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 14 Specifications..................................................................................... 3 Terminology .................................................................................... 17 ±5 V Dual Supply ......................................................................... 3 Outline Dimensions ....................................................................... 18 12 V Single Supply ........................................................................ 4 Ordering Guide .......................................................................... 18 5 V Single Supply .......................................................................... 4 3.3 V Single Supply ....................................................................... 6 REVISION HISTORY 7/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG1608/ADG1609 SPECIFICATIONS ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) ADG1608 ADG1609 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C VDD to VSS 4.5 5 0.12 0.25 1 1.3 7 8 0.3 0.35 1.7 2 tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD VS = ±4.5 V, IS = −10 mA VS = ±4.5 V, VD = ∓4.5 V; see Figure 26 VS = ±4.5 V, VD = ∓4.5 V; see Figure 26 ±0.5 ±3 nA max nA typ ±0.15 ±0.15 ±0.03 ±0.15 ±2 ±1 ±14 ±7 ±2 ±14 nA max nA max nA typ nA max 2.0 0.8 ±1 4 150 182 106 132 113 144 47 V min V max nA typ μA max pF typ VS = VD = ±4.5 V; see Figure 27 VIN = VGND or VDD 24 −64 −64 0.04 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ 40 71 20 MHz typ MHz typ pF typ VS = 0 V, f = 1 MHz 120 61 pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 153 85 pF typ pF typ VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VDD 230 258 150 160 178 202 0.001 VDD/VSS 1 VS = ±4.5 V, IS = −10 mA; see Figure 25 VDD = ±4.5 V, VSS = ±4.5 V VS = ±4.5 V, IS = −10 mA nA typ ±0.1 ±0.03 30 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) −3 dB Bandwidth ADG1608 ADG1609 CS (Off) CD (Off) ADG1608 ADG1609 CD, CS (On) ADG1608 ADG1609 POWER REQUIREMENTS IDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments VDD = +5.5 V, VSS = −5.5 V ±0.02 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION Unit 1.0 ±3.3/±8 Guaranteed by design, but not subject to production test. Rev. 0 | Page 3 of 20 μA typ μA max V min/max RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 28 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 29 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 RL = 110 Ω, VS = 5 V p-p, f = 20 Hz to 20 kHz; see Figure 35 RL = 50 Ω, CL = 5 pF; see Figure 33 ADG1608/ADG1609 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) ADG1608 ADG1609 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C 0 V to VDD 4 4.5 0.12 0.25 0.9 1.2 ±0.02 ±0.1 ±0.03 ±0.15 ±0.15 ±0.03 ±0.15 6.5 7.5 0.3 0.35 1.6 1.9 ±0.5 ±3 ±2 ±1 ±14 ±7 ±2 ±14 2.0 0.8 ±1 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 4 113 141 80 94 77 93 47 VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 26 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 26 VS = VD = 1 V or 10 V; see Figure 27 VIN = VGND or VDD MHz typ MHz typ pF typ VS = 6 V, f = 1 MHz 117 59 pF typ pF typ VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz 149 84 pF typ pF typ VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 12 V Digital inputs = 0 V or VDD 110 117 140 0.001 300 225 VDD 1 V min V max nA typ μA max pF typ VS = 0 V to 10 V, IS = −10 mA 40 78 19 101 480 ADG1609 nA typ nA max nA typ nA max nA max nA typ nA max VS = 0 V to 10 V, IS = −10 mA; see Figure 25 VDD = 10.8 V, VSS = 0 V VS = 10 V, IS = −10 mA 29 −64 −64 0.04 196 1.0 ADG1608 V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ 172 30 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) −3 dB Bandwidth ADG1608 ADG1609 CS (Off) CD (Off) ADG1608 ADG1609 CD, CS (On) ADG1608 ADG1609 POWER REQUIREMENTS IDD Unit 360 3.3/16 μA typ μA max μA typ μA max μA typ μA max V min/max Guaranteed by design, but not subject to production test. Rev. 0 | Page 4 of 20 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 28 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 29 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 RL = 110 Ω, VS = 5 V p-p, f = 20 Hz to 20 kHz; see Figure 35 RL = 50 Ω, CL = 5 pF; see Figure 33 Digital inputs = 5 V Digital inputs = 5 V ADG1608/ADG1609 5 V SINGLE SUPPLY VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) ADG1608 ADG1609 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°Cto +85°C −40°C to +125°C 0 V to VDD 8.5 10 0.15 0.3 1.7 2.3 ±0.01 ±0.1 ±0.01 ±0.15 ±0.15 ±0.01 ±0.15 12.5 14 0.35 0.4 2.7 3 ±0.5 ±3 ±2 ±1 ±14 ±7 ±2 ±14 2.0 0.8 ±1 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 4 193 251 115 152 140 184 66 nA typ nA max nA typ nA max nA max nA typ nA max V min V max nA typ μA max pF typ 11 −64 −64 0.3 37 72 22 MHz typ MHz typ pF typ 136 68 pF typ pF typ 168 94 pF typ pF typ 0.001 μA typ μA max V min/max 339 171 184 225 259 Test Conditions/Comments VS = 0 V to 4.5 V, IS = −10 mA; see Figure 25 VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = −10 mA VS = 0 V to 4.5 V, IS = −10 mA VDD = 5.5 V, VSS = 0 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 26 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 26 VS = VD = 1 V or 4.5 V; see Figure 27 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 28 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 29 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 34 RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p; see Figure 35 RL = 50 Ω, CL = 5 pF; see Figure 33 VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VDD 1 V Ω typ Ω max Ω typ Ω max Ω typ Ω max ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ 301 37 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) −3 dB Bandwidth ADG1608 ADG1609 CS (Off) CD (Off) ADG1608 ADG1609 CD, CS (On) ADG1608 ADG1609 POWER REQUIREMENTS IDD Unit 1.0 3.3/16 Guaranteed by design, but not subject to production test. Rev. 0 | Page 5 of 20 VDD = 5.5 V Digital inputs = 0 V or VDD ADG1608/ADG1609 3.3 V SINGLE SUPPLY VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) ADG1608 ADG1609 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C Unit 13.5 15 0 V to VDD 16.5 V Ω typ 0.25 5 0.28 5.5 0.3 6.5 Ω typ Ω typ ±0.5 ±3 ±2 ±1 ±14 ±7 ±2 ±14 ±0.01 ±0.1 ±0.01 ±0.15 ±0.15 ±0.01 ±0.15 2.0 0.8 ±1 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 4 312 437 216 309 236 316 104 6 −64 −64 0.5 34 72 23 MHz typ MHz typ pF typ 145 72 pF typ pF typ 173 95 pF typ pF typ 0.001 μA typ μA max V min/max 542 331 344 367 411 VS = 0 V to VDD, IS = −10 mA; see Figure 25, VDD = 3.3 V, VSS = 0 V VS = 0 V to VDD, IS = −10 mA VS = 0 V to VDD, IS = −10 mA VDD = 3.6 V, VSS = 0 V VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 26 VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 26 VS = VD = 0.6 V or 3 V; see Figure 27 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 28 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 29 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 34 RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p; see Figure 35 RL = 50 Ω, CL = 5 pF; see Figure 33 VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VDD 1 V min V max nA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ 498 48 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) −3 dB Bandwidth ADG1608 ADG1609 CS (Off) CD (Off) ADG1608 ADG1609 CD, CS (On) ADG1608 ADG1609 POWER REQUIREMENTS IDD nA typ nA max nA typ nA max nA max nA typ nA max Test Conditions/Comments 1.0 3.3/16 Guaranteed by design, but not subject to production test. Rev. 0 | Page 6 of 20 VDD = 3.6 V Digital inputs = 0 V or VDD ADG1608/ADG1609 CONTINUOUS CURRENT PER CHANNEL, S OR D Table 5. ADG1608 Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = −5 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 5 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 3.3 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) 25°C 85°C 125°C Unit 290 470 180 255 100 120 mA max mA max 213 346 129 185 73 84 mA max mA max 157 252 101 150 63 77 mA max mA max 126 206 87 129 56 73.5 mA max mA max 25°C 85°C 125°C Unit 147 245 98 147 63 77 mA max mA max 157 255 101 150 63 77 mA max mA max 115 189 80 119 52 70 mA max mA max 94 154 66 101 45 63 mA max mA max Table 6. ADG1609 Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = −5 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 5 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 3.3 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) Rev. 0 | Page 7 of 20 ADG1608/ADG1609 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D 2 Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb free 1 2 Rating 18 V −0.3 V to +18 V +0.3 V to −18 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 710 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 112.6°C/W 48.7°C/W 260°C Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. See Table 5 and Table 6. Rev. 0 | Page 8 of 20 ADG1608/ADG1609 A2 VSS 3 GND 13 TOP VIEW (Not to Scale) VDD 12 S5 6 11 S6 S4 7 10 S7 D 8 9 S8 S1 S2 5 S3 10 S5 9 S6 14 A1 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS. 08318-003 14 ADG1608 4 TOP VIEW (Not to Scale) Figure 3. ADG1608 Pin Configuration (TSSOP) 08318-004 15 S3 4 12 GND 11 VDD S7 8 EN 2 S2 3 S8 7 A1 D 6 16 ADG1608 S4 5 A0 1 13 A2 PIN 1 INDICATOR VSS 1 S1 2 15 A0 16 EN PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADG1608 Pin Configuration (LFCSP) Table 8. ADG1608 Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 Mnemonic A0 EN 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/A VSS S1 S2 S3 S4 D S8 S7 S6 S5 VDD GND A2 A1 EP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP Description Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1. Can be an input or an output. Source Terminal 2. Can be an input or an output. Source Terminal 3. Can be an input or an output. Source Terminal 4. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal 8. Can be an input or an output. Source Terminal 7. Can be an input or an output. Source Terminal 6. Can be an input or an output. Source Terminal 5. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Logic Control Input. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 9. ADG1608 Truth Table A2 X1 0 0 0 0 1 1 1 1 1 A1 X1 0 0 1 1 0 0 1 1 A0 X1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 X = don’t care. Rev. 0 | Page 9 of 20 On Switch None 1 2 3 4 5 6 7 8 VSS 3 14 VDD ADG1609 13 TOP VIEW (Not to Scale) S1B 12 S2B S3A 6 11 S3B S4A 7 10 S4B DA 8 9 DB S1A 4 S2A 5 11 S1B 10 S2B 9 S3B 14 A1 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS. 08318-006 GND 12 VDD S4B 8 15 SB 7 EN 2 S3A 4 TOP VIEW (Not to Scale) DA 6 A1 ADG1609 S4A 5 16 08318-005 A0 1 S2A 3 13 GND PIN 1 INDICATOR VSS 1 S1A 2 15 A0 16 EN ADG1608/ADG1609 Figure 6. ADG1609 Pin Configuration (LFCSP) Figure 5. ADG1609 Pin Configuration (TSSOP) Table 10. ADG1609 Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 Mnemonic A0 EN 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/A VSS S1A S2A S3A S4A DA DB S4B S3B S2B S1B VDD GND A1 EP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP Description Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1A. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Source Terminal 3A. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Drain Terminal A. Can be an input or an output. Drain Terminal B. Can be an input or an output. Source Terminal 4B. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 11. ADG1609 Truth Table A1 X1 0 0 1 1 1 A0 X1 0 1 0 1 EN 0 1 1 1 1 On Switch Pair None 1 2 3 4 X = don’t care. Rev. 0 | Page 10 of 20 ADG1608/ADG1609 TYPICAL PERFORMANCE CHARACTERISTICS 7 7 TA = 25°C 5 VDD = +3.3V VSS = –3.3V 4 3 VDD = +5V VSS = –5V 2 VDD = +8V VSS = –8V 1 5 TA = +125°C 4 TA = +85°C TA = +25°C 3 TA = –40°C 2 –8 –6 –4 –2 0 2 4 6 8 SOURCE OR DRAIN VOLTAGE (V) 0 0 2 4 6 Figure 7. On Resistance vs. VD (VS) for Dual Supply 10 12 Figure 10. On Resistance vs. VD (VS) for Different Temperatures, 12 V Single Supply 12 16 TA = 25°C VDD = 3.3V VSS = 0V 14 10 TA = +125°C ON RESISTANCE (Ω) 12 ON RESISTANCE (Ω) 8 SOURCE OR DRAIN VOLTAGE (V) 08318-032 1 08318-029 0 VDD = 12V VSS = 0V 6 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 6 10 VDD = 5V VSS = 0V 8 6 VDD = 16V VSS = 0V VDD = 12V VSS = 0V 4 TA = +85°C 8 TA = +25°C 6 TA = –40°C 4 2 2 6 4 8 12 10 14 16 SOURCE OR DRAIN VOLTAGE (V) 0 VDD = +5V VSS = –5V 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD = 3.3V VSS = 0V 16 6 14 ON RESISTANCE (Ω) TA = +125°C 5 TA = +85°C 4 TA = +25°C 3 TA = –40°C 2 12 TA = +125°C TA = +85°C TA = +25°C TA = –40°C 10 8 6 4 0 –4 –3 –2 –1 0 1 2 3 4 5 SOURCE OR DRAIN VOLTAGE (V) Figure 9. On Resistance vs. VD (VS) for Different Temperatures, ±5 V Dual Supply 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE OR DRAIN VOLTAGE (V) Figure 12. On Resistance vs. VD (VS) for Different Temperatures, 3.3 V Single Supply Rev. 0 | Page 11 of 20 08318-020 2 1 08318-031 ON RESISTANCE (Ω) 1.0 Figure 11. On Resistance vs. VD (VS) for Different Temperatures, 5 V Single Supply 18 7 0.5 SOURCE OR DRAIN VOLTAGE (V) Figure 8. On Resistance vs. VD (VS) for Single Supply 0 –5 0 08318-033 2 0 08318-030 0 VDD = 5V VSS = 0V ADG1608/ADG1609 9 12 VDD = +5V VSS = –5V VBIAS = +4.5V/–4.5V 10 7 LEAKAGE CURRENT (nA) ID (OFF) – + ID, IS (ON) + + IS (OFF) + – 2 0 –2 ID, IS (ON) – – IS (OFF) – + ID (OFF) + – –4 –6 5 3 2 1 0 –1 0 20 40 60 80 100 120 TEMPERATURE (°C) 20 ID, IS (ON) + + ID (OFF) – + IS (OFF) + – IDD (µA) 300 IDD = +5V ISS = –5V IDD = +5V ISS = 0V ID, IS (ON) – – IS (OFF) – + ID (OFF) + – 60 80 100 IDD = +3.3V ISS = 0V 100 120 TEMPERATURE (°C) 0 08318-034 40 0 2 4 10 12 14 30 25 8 CHARGE INJECTION (pC) 7 6 5 ID, IS (ON) + + ID (OFF) – + ID, IS (ON) – – IS (OFF) + – IS (OFF) – + ID (OFF) + – 4 3 2 1 VDD = +12V VSS = 0V VDD = +5V VSS = –5V 20 15 10 VDD = +5V VSS = 0V 5 20 40 60 80 100 120 TEMPERATURE (°C) 08318-036 0 0 –6 –4 –2 0 2 4 VS (V) 6 8 10 Figure 18. Charge Injection vs. Source Voltage Figure 15.ADG1608 Leakage Currents vs. Temperature, 5 V Single Supply Rev. 0 | Page 12 of 20 12 14 08318-026 VDD = +3.3V VSS = 0V 0 –1 8 Figure 17. IDD vs. Logic Level VDD = 5V VSS = 0V VBIAS = 1V/4.5V 9 6 LOGIC (V) Figure 14. ADG1608 Leakage Currents vs. Temperature, 12 V Single Supply 10 120 400 200 20 100 IDD = +12V ISS = 0V 0 0 80 IDD PER CHANNEL TA = 25°C 500 5 –10 60 600 VDD = 12V VSS = 0V VBIAS = 1V/10V –5 LEAKAGE CURRENT (nA) 40 Figure 16. ADG1608 Leakage Currents vs. Temperature, 3.3 V Single Supply 10 LEAKAGE CURRENT (nA) 0 TEMPERATURE (°C) Figure 13. ADG1608 Leakage Currents vs. Temperature, ±5 V Dual Supply 15 ID, IS (ON) + + ID (OFF) – + ID, IS (ON) – – IS (OFF) + – ID (OFF) + – IS (OFF) – + 4 08318-018 4 6 08318-019 6 08318-035 LEAKAGE CURRENT (nA) 8 –8 VDD = 3.3V VSS = 0V VBIAS = 0.6V/3V 8 ADG1608/ADG1609 450 0 TA = 25°C 400 –1 250 200 VDD = +5V, VSS = 0V 150 100 VDD = +5V, VSS = –5V 50 –2 –3 –4 –5 VDD = +12V, VSS = 0V 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) –6 10k TA = 25°C VDD = +5V VSS = –5V –10 10M 100M Figure 22. On Response vs. Frequency 0 TA = 25°C VDD = +5V VSS = –5V TA = 25°C VDD = +5V VSS = –5V –20 –20 –30 ACPSRR (dB) OFF ISOLATION (dB) 1M FREQUENCY (Hz) Figure 19. Transition Time vs. Temperature 0 100k 08318-021 INSERTION LOSS (dB) VDD = +3.3V, VSS = 0V 300 08318-024 TRANSITION TIME (ns) 350 –40 –50 –60 NO DECOUPLING CAPACITORS –40 DECOUPLING CAPACITORS –60 –80 –70 –80 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) –120 08318-023 –100 10k 1k Figure 20. Off Isolation vs. Frequency 0 –10 10k 100k 1M FREQUENCY (Hz) 10M 100M 08318-027 –90 Figure 23. ACPSRR vs. Frequency 0.6 TA = 25°C VDD = +5V VSS = –5V LOAD = 110Ω TA = 25°C 0.5 –20 VDD = +3.3V, VS = 2V p-p 0.4 THD + N (%) –40 –50 –60 0.3 VDD = +5V, VS = 3.5V p-p 0.2 –70 –80 VDD = +5V, VSS = –5V, VS = 5V p-p 0.1 –90 100k 1M 10M 100M FREQUENCY (Hz) 1G Figure 21. Crosstalk vs. Frequency 0 0 5k 10k FREQUENCY (Hz) 15k Figure 24. THD + N vs. Frequency Rev. 0 | Page 13 of 20 20k 08318-028 –100 10k VDD = +12V, VS = 5V p-p 08318-022 CROSSTALK (dB) –30 ADG1608/ADG1609 TEST CIRCUITS V IS (OFF) D A IDS D ID (OFF) VS 08318-007 VS S A VD Figure 25. On Resistance 08318-008 S Figure 26. Off Leakage ID (ON) D NC = NO CONNECT A VD 08318-009 S NC Figure 27. On Leakage 3V ADDRESS DRIVE (VIN) 50% 50% tr < 20ns tf < 20ns VDD VSS VDD VSS A0 0V VIN S1 A1 50Ω A2 tTRANSITION VS1 S2 TO S7 tTRANSITION VS8 S8 90% ADG1608* 2.4V OUTPUT OUTPUT D EN 100Ω GND 35pF 08318-010 90% *SIMILAR CONNECTION FOR ADG1609. Figure 28. Address to Output Switching Times, tTRANSITION 3V ADDRESS DRIVE (VIN) VDD VSS VDD VSS A0 VIN 0V S1 A1 50Ω A2 VS S2 TO S7 S8 80% ADG1608* 80% OUTPUT 2.4V OUTPUT D EN GND 100Ω 35pF *SIMILAR CONNECTION FOR ADG1609. Figure 29. Break-Before-Make Delay, tBBM Rev. 0 | Page 14 of 20 08318-011 tBBM ADG1608/ADG1609 3V 50% VSS VDD VSS A0 50% S1 A1 0V A2 tON (EN) ADG1608* tOFF (EN) 0.9VO 0.9VO OUTPUT 50Ω OUTPUT D EN VIN VS S2 TO S8 35pF 100Ω GND 08318-012 ENABLE DRIVE (VIN) VDD *SIMILAR CONNECTION FOR ADG1609. Figure 30. Enable Delay, tON (EN), tOFF (EN) 3V VDD VSS VDD VSS A0 A1 VIN A2 ADG1608* ΔVOUT QINJ = CL × ΔVOUT S D EN VS GND VOUT CL 1nF VIN *SIMILAR CONNECTION FOR ADG1609. Figure 31. Charge Injection Rev. 0 | Page 15 of 20 08318-013 VOUT RS ADG1608/ADG1609 VDD VSS VDD NETWORK ANALYZER NETWORK ANALYZER VSS S VOUT D VS S2 GND VOUT GND OFF ISOLATION = 20 log VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 32. Off Isolation VDD 0.1µF VSS 0.1µF 0.1µF NETWORK ANALYZER VSS VOUT VS Figure 34. Channel-to-Channel Crosstalk VSS VDD R 50Ω VS 08318-014 RL 50Ω VSS S1 D VDD 0.1µF VDD RL 50Ω 50Ω 50Ω 0.1µF VSS 0.1µF 0.1µF 08318-015 VDD 0.1µF VDD AUDIO PRECISION VSS RS S S 50Ω IN VS D VS V p-p D INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH VIN GND RL 10kΩ Figure 35. THD + Noise Figure 33. Bandwidth Rev. 0 | Page 16 of 20 VOUT 08318-017 GND VOUT 08318-016 RL 50Ω ADG1608/ADG1609 TERMINOLOGY IDD The positive supply current. CIN The digital input capacitance. ISS The negative supply current. tTRANSITION The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. tON (EN) The delay between applying the digital control input and the output switching on. tOFF (EN) The delay between applying the digital control input and the output switching off . Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. Off Isolation A measure of unwanted signal coupling through an off switch. ID, IS (On) The channel leakage current with the switch on. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. VINL The maximum input voltage for Logic 0. Bandwidth The frequency at which the output is attenuated by 3 dB. VINH The minimum input voltage for Logic 1. On Response The frequency response of the on switch. IINL (IINH) The input current of the digital input. Insertion Loss The loss due to the on resistance of the switch. CS (Off) The off switch source capacitance, which is measured with reference to ground. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. CD (Off) The off switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on switch capacitance, which is measured with reference to ground. AC Power Supply Rejection Ratio (ACPSRR) The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. Rev. 0 | Page 17 of 20 ADG1608/ADG1609 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 1.75 1.60 SQ 1.55 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED. 070209-C 3.10 3.00 SQ 2.90 Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model ADG1608BRUZ 1 ADG1608BRUZ-REEL71 ADG1608BCPZ-REEL71 ADG1609BRUZ1 ADG1609BRUZ-REEL71 ADG1609BCPZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 Package Option RU-16 RU-16 CP-16-22 RU-16 RU-16 CP-16-22 Branding S38 S39 ADG1608/ADG1609 NOTES Rev. 0 | Page 19 of 20 ADG1608/ADG1609 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08318-0-7/09(0) Rev. 0 | Page 20 of 20