High Voltage Latch-Up Proof, Quad SPST Switches ADG5412/ADG5413 FUNCTIONAL BLOCK DIAGRAMS Latch-up proof 8 kV human body model (HBM) ESD rating Low on resistance (<10 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range S1 S1 IN1 IN1 D1 D1 S2 S2 IN2 IN2 D2 D2 ADG5412 ADG5413 S3 S3 IN3 APPLICATIONS The ADG5412/ADG5413 contain four independent singlepole/single-throw (SPST) switches. The ADG5412 switches turn on with Logic 1. The ADG5413 has two switches with digital control logic similar to that of the ADG5412; however, the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. D3 D3 Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems GENERAL DESCRIPTION IN3 S4 S4 IN4 IN4 D4 D4 SWITCHES SHOWN FOR A LOGIC 1 INPUT. 09202-001 FEATURES Figure 1. exhibits break-before-make switching action for use in multiplexer applications. PRODUCT HIGHLIGHTS 1. 2. 3. The ADG5412 and ADG5413 do not have a VL pin. The digital inputs are compatible with 3 V logic inputs over the full operating supply range. 4. The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. High switching speed also makes the devices suitable for video signal switching. The ADG5413 5. 6. Trench isolation guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Low RON. Dual-supply operation. For applications where the analog signal is bipolar, the ADG5412/ADG5413 can be operated from dual supplies up to ±22 V. Single-supply operation. For applications where the analog signal is unipolar, the ADG5412/ADG5413 can be operated from a single rail power supply up to 40 V. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 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ADG5412/ADG5413 TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, Sx or Dx ..............................7 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 Functional Block Diagrams ............................................................. 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................9 Product Highlights ........................................................................... 1 Typical Performance Characteristics ........................................... 10 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 14 Specifications..................................................................................... 3 Terminology .................................................................................... 16 ±15 V Dual Supply ....................................................................... 3 Trench Isolation .............................................................................. 17 ±20 V Dual Supply ....................................................................... 4 Applications Information .............................................................. 18 12 V Single Supply ........................................................................ 5 Outline Dimensions ....................................................................... 19 36 V Single Supply ........................................................................ 6 Ordering Guide .......................................................................... 19 REVISION HISTORY 7/10—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG5412/ADG5413 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) 25°C −40°C to +85°C −40°C to +125°C Unit VDD to VSS V Ω typ 9.8 14 16 Ω max Ω typ 0.7 1.2 1.6 0.9 1.1 VS = ±10 V, IS = −10 mA 2 2.2 Ω max Ω typ Ω max nA typ VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VD = m 10 V; see Figure 27 ±0.05 ±0.25 ±0.05 ±0.75 Drain Off Leakage, ID (Off ) ±0.25 ±0.1 ±0.4 ±0.75 ±3.5 ±2 ±12 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±3.5 tOFF Break-Before-Make Time Delay, tD (ADG5413 Only) nA max nA typ VS = ±10 V, VD = m 10 V; see Figure 27 nA max nA typ nA max VS = VD = ±10 V; see Figure 23 VIN = VGND or VDD 2.5 V min V max μA typ μA max pF typ 170 202 120 145 15 ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON VS = ±10 V, IS = −10 mA; see Figure 24 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −10 mA 11 0.35 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID (On), IS (On) Test Conditions/Comments 236 262 170 182 Charge Injection, QINJ 240 6 ns min pC typ Off Isolation −78 dB typ Channel-to-Channel Crosstalk −70 dB typ Total Harmonic Distortion + Noise 0.009 % typ −3 dB Bandwidth 167 MHz typ Insertion Loss −0.7 dB typ CS (Off ) CD (Off ) CD (On), CS (On) 18 18 60 pF typ pF typ pF typ Rev. 0 | Page 3 of 20 ADG5412/ADG5413 Parameter POWER REQUIREMENTS IDD 25°C −40°C to +85°C 45 55 0.001 ISS Unit μA typ μA max μA typ μA max V min/V max 70 1 ±9/±22 VDD/VSS 1 −40°C to +125°C Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) 25°C −40°C to +85°C Unit VDD to VSS V Ω typ 9 15 Ω max Ω typ 0.7 1.5 1.8 0.9 1.1 VS = ±15 V, IS = −10 mA 2.2 2.5 Ω max Ω typ Ω max nA typ VDD = +22 V, VSS = −22 V VS = ±15 V, VD = m 15 V; see Figure 27 ±0.25 ±0.05 ±0.75 Drain Off Leakage, ID (Off ) ±0.25 ±0.1 ±0.75 Channel On Leakage, ID (On), IS (On) ±0.4 ±2 ±3.5 ±3.5 Break-Before-Make Time Delay, tD (ADG5413 Only) nA max nA typ VS = ±15 V, VD = m 15 V; see Figure 27 VS = VD = ±15 V; see Figure 23 nA max 2.0 0.8 V min V max μA typ μA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 31 RL = 300 Ω, CL = 35 pF ns min VS1 = VS2 = 10 V; see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 0.002 2.5 158 187 110 138 12 nA max nA typ ±12 ±0.1 tOFF VS = ±15 V, IS = −10 mA; see Figure 24 VDD = +18 V, VSS = −18 V VS = ±15 V, IS = −10 mA 13 ±0.05 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON Test Conditions/Comments 10 0.35 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH −40°C to +125°C 217 240 154 170 5 Charge Injection, QINJ 310 pC typ Off Isolation −78 dB typ Channel-to-Channel Crosstalk −70 dB typ Rev. 0 | Page 4 of 20 ADG5412/ADG5413 Parameter Total Harmonic Distortion + Noise −40°C to +85°C −40°C to +125°C Unit % typ −3 dB Bandwidth 160 MHz typ Insertion Loss −0.6 dB typ 17 17 60 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS 1 25°C 0.007 50 70 0.001 110 ±9/±22 μA typ μA max μA typ V min/V max Test Conditions/Comments RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) 25°C −40°C to +85°C Unit 0 V to VDD V Ω typ 19 31 Ω max Ω typ 0.8 4.4 5.5 1 1.2 VS = 0 V to 10 V, IS = −10 mA 6.5 7.5 Ω max Ω typ Ω max nA typ VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 ±0.25 ±0.05 ±0.75 Drain Off Leakage, ID (Off ) ±0.25 ±0.1 ±0.75 Channel On Leakage, ID (On), IS (On) ±0.4 ±2 ±3.5 ±3.5 nA max nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 VS = VD = 1 V/10 V; see Figure 23 nA max 2.0 0.8 V min V max μA typ μA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 0.002 2.5 225 296 150 187 nA max nA typ ±12 ±0.1 tOFF VS = 0 V to 10 V, IS = −10 mA; see Figure 24 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA 27 ±0.05 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON Test Conditions/Comments 22 0.4 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH −40°C to +125°C 358 403 222 247 Rev. 0 | Page 5 of 20 ADG5412/ADG5413 Parameter Break-Before-Make Time Delay, tD (ADG5413 Only) 25°C 70 −40°C to +85°C Unit ns typ Test Conditions/Comments RL = 300 Ω, CL = 35 pF 38 VS1 = VS2 = 8 V; see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25 RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD Charge Injection, QINJ 95 ns min pC typ Off Isolation −78 dB typ Channel-to-Channel Crosstalk −70 dB typ Total Harmonic Distortion + Noise 0.07 % typ −3 dB Bandwidth 180 MHz typ Insertion Loss −1.3 dB typ 22 22 58 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 40 65 9/40 VDD 1 −40°C to +125°C μA typ μA max V min/V max GND = 0 V, VSS = 0 V Guaranteed by design; not subject to production test. 36 V SINGLE SUPPLY VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) 25°C −40°C to +85°C −40°C to +125°C Unit 0 V to VDD V Ω typ 10.6 Test Conditions/Comments VS = 0 V to 30 V, IS = −10 mA; see Figure 24 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = −10 mA 12 0.35 15 17 Ω max Ω typ 0.7 2.7 3.2 0.9 1.1 VS = 0 V to 30 V, IS = −10 mA 3.8 4.5 Ω max Ω typ Ω max nA typ VDD = 39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V; see Figure 27 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.05 ±0.25 ±0.05 ±0.75 Drain Off Leakage, ID (Off ) ±0.25 ±0.1 ±0.75 Channel On Leakage, ID (On), IS (On) ±0.4 ±2 ±3.5 ±3.5 ±12 Rev. 0 | Page 6 of 20 nA max nA typ nA max nA typ nA max VS = 1 V/30 V, VD = 30 V/1 V; see Figure 27 VS = VD = 1 V/30 V; see Figure 23 ADG5412/ADG5413 Parameter DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments 2.0 0.8 V min V max μA typ μA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 18 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 18 V; see Figure 30 VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 25 RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 28 RL = 50 Ω, CL = 5 pF; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG5413 Only) 2.5 180 220 130 169 25 230 248 167 174 Charge Injection, QINJ 280 8 ns min pC typ Off Isolation −78 dB typ Channel-to-Channel Crosstalk −70 dB typ Total Harmonic Distortion + Noise 0.03 % typ −3 dB Bandwidth 174 MHz typ Insertion Loss −0.8 dB typ 18 18 58 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 80 100 VDD 1 μA typ μA max V min/V max 130 9/40 GND = 0 V, VSS = 0 V Guaranteed by design; not subject to production test. CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 5. Parameter CONTINUOUS CURRENT, Sx OR Dx VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 89 160 59 94 37 49 mA maximum mA maximum 95 170 63 98 39 50 mA maximum mA maximum 61 110 43 70 29 42 mA maximum mA maximum 80 144 54 87 35 47 mA maximum mA maximum Rev. 0 | Page 7 of 20 ADG5412/ADG5413 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 278 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 112.6°C/W 30.4°C/W 260(+0/−5)°C 1 Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. Rev. 0 | Page 8 of 20 ADG5412/ADG5413 IN4 8 9 IN3 NC = NO CONNECT 11 VDD GND 3 S4 4 TOP VIEW (Not to Scale) 9 S3 D4 5 D3 09202-002 10 12 S2 ADG5412/ ADG5413 VSS 2 TOP VIEW 12 NC (Not to Scale) S4 6 11 S3 GND 5 D4 7 PIN 1 INDICATOR S1 1 10 NC NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. 09202-003 VDD ADG5412/ ADG5413 14 IN2 S2 13 VSS 4 13 D2 14 D3 8 D2 S1 3 15 IN1 IN2 15 IN3 7 16 D1 2 IN4 6 IN1 1 16 D1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. LFCSP Pin Configuration Figure 2. TSSOP Pin Configuration Table 7. Pin Function Descriptions TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin No. LFCSP 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP Mnemonic IN1 D1 S1 VSS GND S4 D4 IN4 IN3 D3 S3 NC VDD S2 D2 IN2 Exposed Pad Description Logic Control Input 1. Drain Terminal 1. This pin can be an input or output. Source Terminal 1. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. Source Terminal 4. This pin can be an input or output. Drain Terminal 4. This pin can be an input or output. Logic Control Input 4. Logic Control Input 3. Drain Terminal 3. This pin can be an input or output. Source Terminal 3. This pin can be an input or output. No Connection. Most Positive Power Supply Potential. Source Terminal 2. This pin can be an input or output. Drain Terminal 2. This pin can be an input or output. Logic Control Input 2. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 8. ADG5412 Truth Table INx 1 0 Switch Condition On Off Table 9. ADG5413 Truth Table INx 0 1 S1, S4 Off On S2, S3 On Off Rev. 0 | Page 9 of 20 ADG5412/ADG5413 TYPICAL PERFORMANCE CHARACTERISTICS 16 12 VDD = +10V VDD = +9V VSS = –10V VSS = –9V TA = 25°C 14 10 ON RESISTANCE (Ω) VDD = +11V VSS = –11V 12 ON RESISTANCE (Ω) TA = 25°C 10 8 VDD10 = +13.5V VSS = –13.5V 6 VDD = +16.5V VSS = –16.5V VDD = +15V VSS = –15V VDD = 36V VSS = 0V VDD = 32.4V VSS = 0V 8 6 VDD = 39.6V VSS = 0V 4 4 2 –10 –5 0 5 10 15 20 VS, VD (V) 0 0 5 10 15 20 25 30 35 40 45 09202-033 –15 09202-034 0 –20 15 09202-040 2 VS, VD (V) Figure 4. RON as a Function of VS, VD (Dual Supply) Figure 7. RON as a Function of VS, VD (Single Supply) 12 18 VDD = +18V VSS = –18V 10 16 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 14 8 VDD = +20V VSS = –20V 6 VDD = +22V VSS = –22V 4 TA = +125°C 12 TA = +85°C 10 TA = +25°C 8 TA = –40°C 6 4 2 2 VDD = +15V VSS = –15V 0 –15 –10 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) 09202-035 TA = 25°C 0 5 10 VS, VD (V) Figure 8. RON as a Function of VS (VD) for Different Temperatures, ±15 V Dual Supply Figure 5. RON as a Function of VS, VD (Dual Supply) 16 25 VDD = +10V VSS = 0V VDD = 10.8V VSS = 0V VDD = +9V VSS = 0V 20 14 12 ON RESISTANCE (Ω) TA = 25°C 15 10 VDD = 11V VSS = 0V VDD = 12V VSS = 0V VDD = 13.2V VSS = 0V TA = +125°C 10 TA = +85°C 8 TA = +25°C 6 TA = –40°C 4 5 0 0 2 4 6 8 10 12 VS, VD (V) 14 VDD = +20V VSS = –20V 0 –20 –15 –10 –5 0 5 10 15 20 VS, VD (V) Figure 9. RON as a Function of VS (VD) for Different Temperatures, ±20 V Dual Supply Figure 6. RON as a Function of VS, VD (Single Supply) Rev. 0 | Page 10 of 20 09202-041 2 09202-032 ON RESISTANCE (Ω) –5 ADG5412/ADG5413 30 0.8 VDD = 12V VSS = 0V LEAKAGE CURRENT (nA) 25 ON RESISTANCE (Ω) VDD = +20V VSS = –20V VBIAS = +15V/–15V 0.6 TA = +125°C 20 TA = +85°C 15 TA = +25°C TA = –40°C 10 5 ID, IS (ON) + + ID, IS (ON) – – 0.4 IS (OFF) + – 0.2 ID (OFF) – + 0 –0.2 IS (OFF) – + –0.4 2 4 6 8 10 12 VS, VD (V) 09202-042 0 0.6 8 TA = +25°C 6 TA = –40°C LEAKAGE CURRENT (nA) 4 2 0.4 ID, IS (ON) – – IS (OFF) + – 0.2 ID (OFF) – + 0 ID (OFF) + – 0 10 5 15 20 30 25 35 40 VS, VD (V) –0.2 0.8 VDD = +15V VSS = –15V VBIAS = +10V/–10V 50 75 ID, IS (ON) – – 0.4 IS (OFF) + – 0.2 0 125 ID, IS (ON) + + ID, IS (ON) – – 0.4 ID (OFF) – + 0.2 0 IS (OFF) + – –0.2 IS (OFF) – + ID (OFF) – + –0.2 100 VDD = 36V VSS = 0V VBIAS = 1V/30V 0.6 ID, IS (ON) + + 0.6 25 Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply LEAKAGE CURRENT (nA) 0.8 IS (OFF) – + 0 TEMPERATURE (°C) Figure 11. RON as a Function of VS (VD) for Different Temperatures, 36 V Single Supply ID (OFF) + – –0.4 IS (OFF) – + ID (OFF) + – –0.4 0 25 50 75 100 125 TEMPERATURE (°C) 09202-037 LEAKAGE CURRENT (nA) ID, IS (ON) + + VDD = 36V VSS = 0V 09202-043 0 125 –0.6 0 25 50 75 100 125 TEMPERATURE (°C) Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply Figure 12. Leakage Currents vs. Temperature, ±15 V Dual Supply Rev. 0 | Page 11 of 20 09202-039 ON RESISTANCE (Ω) TA = +85°C 100 VDD = 12V VSS = 0V VBIAS = 1V/10V 14 10 75 Figure 13. Leakage Currents vs. Temperature, ±20 V Dual Supply 16 TA = +125°C 50 TEMPERATURE (°C) Figure 10. RON as a Function of VS (VD) for Different Temperatures, 12 V Single Supply 12 25 09202-036 0 –0.6 09202-038 ID (OFF) + – 0 ADG5412/ADG5413 –10 –20 –30 –30 –50 –60 NO DECOUPLING CAPACITORS –40 –50 –60 –70 –70 –80 –80 DECOUPLING CAPACITORS –90 –90 –100 1k –100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 10k 0.10 TA = 25°C VDD = +15V VSS = –15V 20 1G LOAD = 1kΩ TA = 25°C 0.09 0.08 –30 0.07 THD + N (%) –20 –40 –50 –60 VDD = 12V, VSS = 0V, VS = 6V p-p 0.06 0.05 0.04 VDD = 36V, VSS = 0V, VS = 18V p-p –70 0.03 –80 0.02 –90 0.01 –100 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 500 5 10 15 0 450 TA = 25°C VDD = +15V VSS = –15V –0.5 400 –1.0 300 INSERTION LOSS (dB) VDD = +20V VSS = –20V 350 VDD = +36V VSS = 0V 250 200 150 VDD = +15V VSS = –15V VDD = +12V VSS = 0V –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 50 –4.5 –10 0 10 20 30 VS (V) 40 09202-030 0 –20 VDD = 20V, VSS = 20V, VS = 20V p-p 0 Figure 20. THD + N vs. Frequency, ±15 V Dual Supply TA = 25°C 100 VDD = 15V, VSS = 15V, VS = 15V p-p FREQUENCY (MHz) Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply CHARGE INJECTION (pC) 10M Figure 19. ACPSRR vs. Frequency, ±15 V Dual Supply 09202-028 CROSSTALK (dB) –10 1M FREQUENCY (Hz) Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply 0 100k 09202-026 –40 TA = 25°C VDD = +15V VSS = –15V 09202-027 ACPSRR (dB) –20 09202-025 OFF ISOLATION (dB) –10 0 TA = 25°C VDD = +15V VSS = –15V 09202-029 0 Figure 18. Charge Injection vs. Source Voltage –5.0 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 21. Bandwidth Rev. 0 | Page 12 of 20 100M ADG5412/ADG5413 350 300 tON (12V) tON (±20V) tON (±15V) 200 tOFF (±15V) tON (36V) 150 100 tOFF (12V) tOFF (36V) tOFF (±20V) 50 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 09202-031 TIME (ns) 250 Figure 22. tON, tOFF Times vs. Temperature Rev. 0 | Page 13 of 20 ADG5412/ADG5413 TEST CIRCUITS IS (OFF) Dx Dx A VS VD VS 09202-015 A 09202-016 Sx ID (OFF) Sx A ID (ON) VD Figure 23. On Leakage Figure 27. Off Leakage VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS RS IDS Sx INx VS V p-p V1 Dx 09202-014 09202-024 GND VS RON = V1/IDS Figure 24. On Resistance VDD Figure 28. THD + Noise VSS VDD 0.1µF 0.1µF VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT VDD NETWORK ANALYZER VSS VDD S1 RL 50Ω VOUT RL 1kΩ Dx Sx RL 50Ω S2 VSS 50Ω INx VS Dx VS VIN GND RL 50Ω GND VOUT VS 09202-021 CHANNEL-TO-CHANNEL CROSSTALK = 20 log INSERTION LOSS = 20 log VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS Sx 50Ω 50Ω INx VS RL 50Ω GND VOUT OFF ISOLATION = 20 log VOUT VS 09202-020 Dx VIN VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 29. Bandwidth Figure 25. Channel-to-Channel Crosstalk Figure 26. Off Isolation Rev. 0 | Page 14 of 20 VOUT 09202-023 Sx Dx VIN ADG5412/ADG5413 VDD VSS VSS D1 S2 D2 CL 35pF RL 300Ω CL 35pF 90% 90% 0V 90% VOUT2 90% 0V ADG5413 GND tD tD Figure 30. Break-Before-Make Time Delay, tD VDD VSS 0.1µF 0.1µF VIN VDD Sx VS ADG5412 50% 50% VSS VOUT Dx CL 35pF RL 300Ω INx 90% VOUT 90% GND tOFF tON 09202-018 IN1, IN2 RL 300Ω VOUT2 VOUT1 50% Figure 31. Switching Times RS VS VDD VSS VDD VSS Sx Dx VOUT VIN ADG5412 ON OFF CL 1nF IN VOUT QINJ = CL × ΔVOUT GND Figure 32. Charge Injection Rev. 0 | Page 15 of 20 ΔVOUT 09202-019 VS2 VOUT1 50% 0V 09202-017 VDD S1 VS1 VIN 0.1µF 0.1µF ADG5412/ADG5413 TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN is the digital input capacitance. ISS ISS represents the negative supply current. tON tON represents the delay between applying the digital control input and the output switching on. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S. ΔRON ΔRON represents the difference between the RON of any two channels. RFLAT (ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. tOFF tOFF represents the delay between applying the digital control input and the output switching off. tD tD represents the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. VINH VINH is the minimum input voltage for Logic 1. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. Rev. 0 | Page 16 of 20 ADG5412/ADG5413 TRENCH ISOLATION In the ADG5412 and ADG5413, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 33. Trench Isolation Rev. 0 | Page 17 of 20 09202-022 In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latchup proof switch. NMOS ADG5412/ADG5413 APPLICATIONS INFORMATION The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5412/ADG5413 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V. The ADG5412/ADG5413 (as well as other select devices within the same family) achieve an 8 kV human body model ESD rating, which provides a robust solution eliminating the need for separate protect circuitry designs in some applications. Rev. 0 | Page 18 of 20 ADG5412/ADG5413 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 2.70 2.60 SQ 2.50 4 9 0.80 0.75 0.70 0.45 0.40 0.35 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. 012909-B TOP VIEW Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG5412BRUZ ADG5412BRUZ-REEL7 ADG5412BCPZ-REEL7 ADG5413BRUZ ADG5413BRUZ-REEL7 ADG5413BCPZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. Rev. 0 | Page 19 of 20 Package Option RU-16 RU-16 CP-16-17 RU-16 RU-16 CP-16-17 ADG5412/ADG5413 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09202-0-7/10(0) Rev. 0 | Page 20 of 20