TDA8922C 2 × 75 W class-D power amplifier Rev. 01 — 7 September 2009 Product data sheet 1. General description The TDA8922C is a high-efficiency Class D audio power amplifier. Typical output power is 2 × 75 W with a speaker load impedance of 6 Ω. The TDA8922C is available in both HSOP24 and DBS23P power packages. The amplifier operates over a wide supply voltage range from ±12.5 V to ±32.5 V and features low quiescent current consumption. 2. Features n Pin compatible with TDA8950/20C for both HSOP24 and DBS23P packages n Symmetrical operating supply voltage range from ±12.5 V to ±32.5 V n Stereo full differential inputs, can be used as stereo Single-Ended (SE) or mono Bridge-Tied Load (BTL) amplifier n High output power in typical applications: u SE 2 × 75 W, RL = 6 Ω (VDD = 30 V; VSS = −30 V) u SE 2 × 60 W, RL = 8 Ω (VDD = 30 V; VSS = −30 V) u BTL 1 × 155 W, RL = 8 Ω (VDD = 25 V; VSS = −25 V) n Low noise n Smooth pop noise-free start-up and switch off n Zero dead time switching n Fixed frequency n Internal or external clock n High efficiency n Low quiescent current n Advanced protection strategy: voltage protection and output current limiting n Thermal FoldBack (TFB) n Fixed gain of 30 dB in SE and 36 dB in BTL applications n Fully short-circuit proof across load n BD modulation in BTL configuration 3. Applications n n n n DVD Mini and micro receiver Home Theater In A Box (HTIAB) system High-power speaker system TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit 30 32.5 V General supply voltage VDD Operating mode [1] 12.5 Operating mode [2] VSS negative supply voltage −12.5 −30 −32.5 V Vth(ovp) overvoltage protection threshold VDD − VSS voltage 65 - 70 V Iq(tot) total quiescent current - 40 70 mA Operating mode; no load; no filter; no RC-snubber network connected Stereo single-ended configuration output power Po Tj = 85 °C; LLC = 22 µH; CLC = 680 nF (see Figure 10); RL = 6 Ω; THD + N = 10 %; VDD = 30 V; VSS = −30 V [3] - 75 - W Tj = 85 °C; LLC = 22 µH; CLC = 680 nF (see Figure 10); RL = 8 Ω; THD + N = 10 %; VDD = 25 V; VSS = −25 V [3] - 155 - W Mono bridge-tied load configuration output power Po [1] VDD is the supply voltage on pins VDDP1, VDDP2 and VDDA. [2] VSS is the supply voltage on pins VSSP1, VSSP2, VSSA and VSSD. [3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3. 5. Ordering information Table 2. Ordering information Type number Package Name Description Version TDA8922CJ DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 TDA8922CTH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height TDA8922C_1 Product data sheet SOT566-3 © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 2 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 6. Block diagram VDDA 3 (20) IN1M IN1P n.c. OSC MODE SGND n.c. 10 (4) VDDP2 STABI PROT 18 (12) 13 (7) 23 (16) IN2M 14 (8) 15 (9) BOOT1 9 (3) PWM MODULATOR INPUT STAGE 8 (2) 11 (5) SWITCH1 CONTROL AND HANDSHAKE mute DRIVER HIGH 16 (10) OUT1 DRIVER LOW STABI VSSP1 7 (1) 6 (23) OSCILLATOR MANAGER MODE TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION TDA8922CTH (TDA8922CJ) VDDP2 22 (15) BOOT2 2 (19) mute IN2P VDDP1 CONTROL SWITCH2 AND HANDSHAKE 5 (22) 4 (21) INPUT STAGE 1 (18) VSSA PWM MODULATOR 12 (6) n.c. 24 (17) VSSD 19 (-) n.c. DRIVER HIGH 21 (14) OUT2 DRIVER LOW 17 (11) VSSP1 20 (13) 010aaa549 VSSP2 Pin numbers in brackets refer to type number TDA8922CJ. Fig 1. Block diagram TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 3 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 7. Pinning information 7.1 Pinning OSC 1 IN1P 2 IN1M 3 n.c. 4 n.c. 5 n.c. 6 PROT 7 VDDP1 8 BOOT1 9 OUT1 10 VSSP1 11 VSSD 24 1 VSSA STABI 12 VDDP2 23 2 SGND VSSP2 13 BOOT2 22 3 VDDA OUT2 21 4 IN2M BOOT2 15 VSSP2 20 5 IN2P VDDP2 16 n.c. 19 6 MODE 7 OSC VSSA 18 8 IN1P SGND 19 9 IN1M VDDA 20 STABI 18 TDA8922CTH VSSP1 17 OUT1 16 TDA8922CJ OUT2 14 VSSD 17 BOOT1 15 10 n.c. VDDP1 14 11 n.c. IN2P 22 PROT 13 12 n.c. MODE 23 IN2M 21 010aaa546 Fig 2. Pin configuration TDA8922CTH 010aaa547 Fig 3. Pin configuration TDA8922CJ TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 4 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 7.2 Pin description Table 3. Symbol VSSA Pin description Pin Description TDA8922CTH TDA8922CJ 1 18 negative analog supply voltage SGND 2 19 signal ground VDDA 3 20 positive analog supply voltage IN2M 4 21 channel 2 negative audio input IN2P 5 22 channel 2 positive audio input MODE 6 23 mode selection input: Standby, Mute or Operating mode OSC 7 1 oscillator frequency adjustment or tracking input IN1P 8 2 channel 1 positive audio input IN1M 9 3 channel 1 negative audio input n.c. 10 4 not connected n.c. 11 5 not connected n.c. 12 6 not connected PROT 13 7 decoupling capacitor for protection (OCP) VDDP1 14 8 channel 1 positive power supply voltage BOOT1 15 9 channel 1 bootstrap capacitor OUT1 16 10 channel 1 PWM output VSSP1 17 11 channel 1 negative power supply voltage STABI 18 12 decoupling of internal stabilizer for logic supply n.c. 19 - not connected VSSP2 20 13 channel 2 negative power supply voltage OUT2 21 14 channel 2 PWM output BOOT2 22 15 channel 2 bootstrap capacitor VDDP2 23 16 channel 2 positive power supply voltage VSSD 24 17 negative digital supply voltage 8. Functional description 8.1 General The TDA8922C is a two-channel audio power amplifier that uses Class D technology. For each channel, the audio input signal is converted into a digital Pulse Width Modulation (PWM) signal using an analog input stage and a PWM modulator; see Figure 1. To drive the output power transistors, the digital PWM signal is fed to a control and handshake block and to high- and low-side driver circuits. This level-shifts the low-power digital PWM signal from a logic level to a high-power PWM signal switching between the main supply lines. A second order low-pass filter converts the PWM signal to an analog audio signal that can be used to drive a loudspeaker. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 5 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier The TDA8922C single-chip Class D amplifier contains high-power switches, drivers, timing and handshaking between the power switches, along with some control logic. To ensure maximum system robustness, an advanced protection strategy has been implemented to provide overvoltage, overtemperature and overcurrent protection. Each of the two audio channels contains a PWM modulator, an analog feedback loop and a differential input stage. The TDA8922C also contains circuits common to both channels such as the oscillator, all reference sources, the mode interface and a digital timing manager. The two independent amplifier channels feature high output power, high efficiency, low distortion and low quiescent currents. They can be connected in the following configurations: • Stereo Single-Ended (SE) • Mono Bridge-Tied Load (BTL) The amplifier system can be switched to one of three operating modes using pin MODE: • Standby mode: featuring very low quiescent current • Mute mode: the amplifier is operational but the audio signal at the output is suppressed by disabling the voltage-to-current (VI) converter input stages • Operating mode: the amplifier is fully operational, de-muted and can deliver an output signal A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure pop noise-free start-up. The bias-current setting of the (VI converter) input stages is related to the voltage on the MODE pin. In Mute mode, the bias-current setting of the VI converters is zero (VI converters are disabled). In Operating mode, the bias current is at a maximum. The time constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated using an RC network connected to pin MODE. An example of a circuit for driving the MODE pin, optimized for optimal pop noise performance, is shown in Figure 4. If the capacitor was omitted, the very short switching time constant could result in audible pop noises being generated at start-up (depending on the DC output offset voltage and loudspeaker used). +5 V 5.6 kΩ 470 Ω MODE TDA8922C 5.6 kΩ 10 µF mute/ operating S1 standby/ operating S2 SGND 010aaa583 Fig 4. Example of mode selection circuit TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 6 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier To ensure the coupling capacitors at the inputs (CIN in Figure 10) are fully charged before the outputs start switching, a delay is inserted during the transition from Mute to Operating mode. An overview of the start-up timing is provided in Figure 5. audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.1 V < VMODE < 2.9 V 0 V (SGND) standby > 350 ms 100 ms time 50 ms audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.2 V mute 2.1 V < VMODE < 2.9 V 0 V (SGND) standby > 350 ms 100 ms 50 ms time 010aaa584 (1) First 1⁄4 pulse down. Upper diagram: When switching from Standby to Mute, there is a delay of approximately 100 ms before the output starts switching. The audio signal will become available once VMODE reaches the Operating mode level (see Table 8), but not earlier than 150 ms after switching to Mute. To start-up pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms for the transition between Mute and Operating modes. Lower diagram: When switching directly from Standby to Operating mode, there is a delay of 100 ms before the outputs start switching. The audio signal becomes available after a second delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin MODE be at least 500 ms for the transition between Standby and Operating modes. Fig 5. Timing on mode selection input pin MODE TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 7 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 8.2 Pulse-width modulation frequency The amplifier output signal is a PWM signal with a typical carrier frequency of between 250 kHz and 450 kHz. A second order LC demodulation filter on the output converts the PWM signal into an analog audio signal. The carrier frequency is determined by an external resistor, ROSC, connected between pins OSC and VSSA. The optimal carrier frequency setting is between 250 kHz and 450 kHz. The carrier frequency is set to 345 kHz by connecting an external 30 kΩ resistor between pins OSC and VSSA. See Table 9 for more details. If two or more Class D amplifiers are used in the same audio application, it is recommended that an external clock circuit be used with all devices (see Section 13.4). This will ensure that they operate at the same switching frequency, thus avoiding beat tones (if the switching frequencies are different, audible interference known as ‘beat tones’ can be generated). 8.3 Protection The following protection circuits are incorporated into the TDA8922C: • Thermal protection: – Thermal FoldBack (TFB) – OverTemperature Protection (OTP) • OverCurrent Protection (OCP) • Window Protection (WP) • Supply voltage protection: – UnderVoltage Protection (UVP) – OverVoltage Protection (OVP) – UnBalance Protection (UBP) How the device reacts to a fault conditions depends on which protection circuit has been activated. 8.3.1 Thermal protection The TDA8922C employes an advanced thermal protection strategy. A TFB function gradually reduces the output power within a defined temperature range. If the temperature continues to rise, OTP is activated to shut down the device completely. 8.3.1.1 Thermal FoldBack (TFB) If the junction temperature (Tj) exceeds the thermal foldback activation threshold, the gain is gradually reduced. This reduces the output signal amplitude and the power dissipation, eventually stabilizing the temperature. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 8 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier TFB is specified at the thermal foldback activation temperature Tact(th_fold) where the closed-loop voltage gain is reduced by 6 dB. The TFB range is: Tact(th_fold) − 5 °C < Tact(th_fold) < Tact(th_prot) The value of Tact(th_fold) for the TDA8922C is approximately 153 °C; see Table 8 for more details. 8.3.1.2 OverTemperature Protection (OTP) If TFB fails to stabilize the temperature and the junction temperature continues to rise, the amplifier will shut down as soon as the temperature reaches the thermal protection activation threshold, Tact(th_prot). The amplifier will resume switching approximately 100 ms after the temperature drops below Tact(th_prot). The thermal behavior is illustrated in Figure 6. Gain (dB) 30 dB 24 dB 0 dB (Tact(th_fold) − 5°C) 1 Tact(th_prot) Tact(th_fold) 2 Tj (°C) 3 001aah656 (1) Duty cycle of PWM output modulated according to the audio input signal. (2) Duty cycle of PWM output reduced due to TFB. (3) Amplifier is switched off due to OTP. Fig 6. Behavior of TFB and OTP 8.3.2 OverCurrent Protection (OCP) In order to guarantee the robustness of the TDA8922C, the maximum output current delivered at the output stages is limited. OCP is built in for each output power switch. OCP is activated when the current in one of the power transistors exceeds the OCP threshold (IORM = 6 A) due, for example, to a short-circuit to a supply line or across the load. The TDA8922C amplifier distinguishes between low-ohmic short-circuit conditions and other overcurrent conditions such as a dynamic impedance drop at the loudspeakers. The impedance threshold (Zth) depends on the supply voltage. How the amplifier reacts to a short circuit depends on the short-circuit impedance: • Short-circuit impedance > Zth: the amplifier limits the maximum output current to IORM but the amplifier does not shut down the PWM outputs. Effectively, this results in a clipped output signal across the load (behavior very similar to voltage clipping). TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 9 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier • Short-circuit impedance < Zth: the amplifier limits the maximum output current to IORM and at the same time discharges the capacitor on pin PROT. When CPROT is fully discharged, the amplifier shuts down completely and an internal timer is started. The value of the protection capacitor (CPROT) connected to pin PROT can be between 10 pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is enabled that will discharge CPROT. When OCP is activated, the active power transistor is turned off and the other power transistor is turned on to reduce the current (CPROT is partially discharged). Normal operation is resumed at the next switching cycle (CPROT is recharged). CPROT is partially discharge each time OCP is activated during a switching cycle. If the fault condition that caused OCP to be activated persists long enough to fully discharge CPROT, the amplifier will switch off completely and a restart sequence will be initiated. After a fixed period of 100 ms, the amplifier will attempt to switch on again, but will fail if the output current still exceeds the OCP threshold. The amplifier will continue trying to switch on every 100 ms. The average power dissipation will be low in this situation because the duty cycle is short. Switching the amplifier on and off in this way will generate unwanted ‘audio holes’. This can be avoided by increasing the value of CPROT (up to 220 pF) to delay amplifier switch-off. CPROT will also prevent the amplifier switching off due to transient frequency-dependent impedance drops at the speakers. The amplifier will switch on, and remain in Operating mode, once the overcurrent condition has been removed. OCP ensures the TDA8922C amplifier is fully protected against short-circuit conditions while avoiding audio holes. Table 4. Type TDA8922C [1] Current limiting behavior during low output impedance conditions at different values of CPROT[1] VDD/VSS VI (mV, p-p) f (Hz) CPROT (pF) (V) PWM output stops Short Short (Zth = 0 Ω) (Zth = 0.5 Ω) Short (Zth = 1 Ω) +29.5/ −29.5 500 20 10 yes yes yes 1000 10 yes yes yes 20 15 yes yes yes 1000 15 yes no no 1000 220 no no no Tested using three samples and an external clock. 8.3.3 Window Protection (WP) Window Protection (WP) checks the conditions at the output terminals of the power stage and is activated: • During the start-up sequence, when the TDA8922C is switching from Standby to Mute. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 10 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier Start-up will be interrupted If a short-circuit is detected between one of the output terminals and pin VDDP1/VDDP2 or VSSP1/VSSP2. The TDA8922C will wait until the short-circuit to the supply lines has been removed before resuming start-up. The short circuit will not generate large currents because the short-circuit check is carried out before the power stages are enabled. • When the amplifier is shut down completely because the OCP circuit has detected a short circuit to one of the supply lines. WP will be activated when the amplifier attempts to restart after 100 ms (see Section 8.3.2). The amplifier will not start-up again until the short circuit to the supply lines has been removed. 8.3.4 Supply voltage protection If the supply voltage drops below the minimum supply voltage threshold, Vth(uvp), the UVP circuit will be activated and the system will shut down. Once the supply voltage rises above Vth(uvp) again, the system will restart after a delay of 100 ms. If the supply voltage exceeds the maximum supply voltage threshold, Vth(ovp), the OVP circuit will be activated and the power stages will be shut down. When the supply voltage drops below Vth(ovp) again, the system will restart after a delay of 100 ms. An additional UnBalance Protection (UBP) circuit compares the positive analog supply voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is triggered if the voltage difference exceeds a factor of two (VDDA > 2 × |VSSA| OR |VSSA| > 2 × VDDA). When the supply voltage difference drops below the unbalance threshold, Vth(ubp), the system restarts after 100 ms. An overview of all protection circuits and their respective effects on the output signal is provided in Table 5. Table 5. Overview of TDA8922C protection circuits Protection name Complete shutdown Restart directly Restart after 100 ms Pin PROT detection TFB[1] N N N N OTP Y N Y N OCP Y[2] N[2] Y[2] Y WP N[3] Y N N UVP Y N Y N OVP Y N Y N UBP Y N Y N [1] Amplifier gain depends on the junction temperature and heatsink size. [2] The amplifier shuts down completely only if the short-circuit impedance is below the impedance threshold (Zth; see Section 8.3.2). In all other cases, current limiting results in a clipped output signal. [3] Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been activated (short-circuit to one of the supply lines). 8.4 Differential audio inputs The audio inputs are fully differential ensuring a high common mode rejection ratio and maximum flexibility in the application. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 11 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier • Stereo operation: to avoid acoustical phase differences, the inputs should be in anti-phase and the speakers should be connected in anti-phase. This configuration: – minimizes power supply peak current – minimizes supply pumping effects, especially at low audio frequencies • Mono BTL operation: the inputs must be connected in anti-parallel. The output of one channel is inverted and the speaker load is connected between the two outputs of the TDA8922C. In practice (because of the OCP threshold) the output power can be boosted to twice the output power that can be achieved with the single-ended configuration. The input configuration for a mono BTL application is illustrated in Figure 7. OUT1 IN1P IN1M Vin SGND IN2P IN2M OUT2 power stage mbl466 Fig 7. Input configuration for mono BTL application 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit ∆V voltage difference VDD − VSS; Standby, Mute modes - 65 V IORM repetitive peak output current maximum output current limiting 6 - A Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C VMODE voltage on pin MODE 0 6 V VOSC voltage on pin OSC 0 SGND + 6 V VI input voltage referenced to SGND pins IN1P, IN1M, IN2P and IN2M −5 +5 V VPROT voltage on pin PROT referenced to voltage on pin VSSD 0 12 V VESD electrostatic discharge voltage referenced to SGND Human Body Model (HBM) −2000 +2000 V Charged Device Model (CDM) −500 +500 V Iq(tot) total quiescent current Operating mode; no load; no filter no RC-snubber network connected - 70 mA VPWM(p-p) peak-to-peak PWM voltage on pins OUT1 and OUT2 - 120 V TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 12 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 10. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W Rth(j-c) thermal resistance from junction to case 1.5 K/W 11. Static characteristics Table 8. Static characteristics VDD = 30 V; VSS = −30 V; fosc = 350 kHz; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions supply voltage Operating mode Min Typ Max Unit [1] 12.5 30 32.5 V [2] Supply VDD VSS negative supply voltage Operating mode −12.5 −30 −32.5 V Vth(ovp) overvoltage protection threshold voltage Standby, Mute modes VDD − VSS 65 - 70 V Vth(uvp) undervoltage protection threshold voltage VDD − VSS 20 - 25 V Vth(ubp) unbalance protection threshold voltage - 33 - % Iq(tot) total quiescent current - 40 70 mA Istb standby current - 480 650 µA [4] 0 - 6 V Standby mode [4][5] 0 - 0.8 V Mute mode [4][5] 2.1 - 2.9 V Operating mode [4][5] 4.2 - 6 V - 110 150 µA - 0 - V - - ±25 mV - - ±150 mV - - ±30 mV - - ±210 mV 9.3 9.8 10.3 V - 154 - °C [3] Operating mode; no load; no filter; no RC-snubber network connected Mode select input; pin MODE VMODE II voltage on pin MODE referenced to SGND input current VI = 5.5 V Audio inputs; pins IN1M, IN1P, IN2P and IN2M VI input voltage DC input [4] Amplifier outputs; pins OUT1 and OUT2 VO(offset) output offset voltage SE; Mute mode SE; Operating mode [6] BTL; Mute mode BTL; Operating mode [6] Stabilizer output; pin STABI VO(STABI) output voltage on pin STABI Mute and Operating modes; with respect to VSSD Temperature protection Tact(th_prot) thermal protection activation temperature TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 13 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier Table 8. Static characteristics …continued VDD = 30 V; VSS = −30 V; fosc = 350 kHz; Tamb = 25 °C; unless otherwise specified. Symbol Tact(th_fold) Parameter Conditions thermal foldback activation temperature closed loop SE voltage gain reduced with 6 dB [7] Min Typ Max Unit - 153 - °C [1] VDD is the supply voltage on pins VDDP1, VDDP2 and VDDA. [2] VSS is the supply voltage on pins VSSP1, VSSP2, VSSA and VSSD. [3] Unbalance protection activated when VDDA > 2 × |VSSA| OR |VSSA| > 2 × VDDA. [4] With respect to SGND (0 V). [5] The transition between Standby and Mute modes has hysteresis, while the slope of the transition between Mute and Operating modes is determined by the time-constant of the RC network on pin MODE; see Figure 8. [6] DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes. The slope caused by any DC output offset is determined by the time-constant of the RC network on pin MODE. [7] At a junction temperature of approximately Tact(th_fold) − 5 °C, gain reduction commences and at a junction temperature of approximately Tact(th_prot), the amplifier switches off. slope is directly related to the time-constant of the RC network on the MODE pin VO (V) VO(offset)(on) Standby Mute On VO(offset)(mute) 0 0.8 2.1 2.9 4.2 5.5 VMODE (V) 010aaa585 Fig 8. Behavior of mode selection pin MODE 12. Dynamic characteristics 12.1 Switching characteristics Table 9. Dynamic characteristics VDD = 30 V; VSS = −30 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ROSC = 30.0 kΩ 290 345 365 kHz 250 - 450 kHz Internal oscillator fosc(typ) typical oscillator frequency fosc oscillator frequency External oscillator input or frequency tracking; pin OSC VOSC voltage on pin OSC Vtrip trip voltage ftrack tracking frequency HIGH-level SGND + 4.5 SGND + 5 [1] TDA8922C_1 Product data sheet SGND + 6 V - SGND + 2.5 - V 500 - kHz 900 © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 14 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier Table 9. Dynamic characteristics …continued VDD = 30 V; VSS = −30 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Zi input impedance Ci input capacitance input rise time tr(i) Conditions from SGCN to SGND + 5 V [2] Min Typ Max Unit 1 - - MΩ - - 15 pF - - 100 ns [1] When using an external oscillator, the frequency ftrack (500 kHz minimum, 900 kHz maximum) will result in a PWM frequency fosc (250 kHz minimum, 450 kHz maximum) due to the internal clock divider; see Section 8.2. [2] When tr(i) > 100 ns, the output noise floor will increase. 12.2 Stereo SE configuration characteristics Table 10. Dynamic characteristics VDD = 30 V; VSS = −30 V; RL = 6 Ω; fi = 1 kHz; fosc = 350 kHz; Rs(L) < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified. Symbol Po Parameter Conditions output power L = 22 µH; CLC = 680 nF; Tj = 85 °C THD = 0.5 %; RL = 6 Ω THD = 10 %; RL = 6 Ω THD total harmonic distortion Gv(cl) closed-loop voltage gain SVRR supply voltage rejection ratio Min Typ Max Unit - 58 - W [2] - 75 - W Po = 1 W; fi = 1 kHz [3] - 0.02 - % Po = 1 W; fi = 6 kHz [3] - 0.05 - % 29 30 31 dB between pins VDDPn and SGND Operating mode; fi = 100 Hz [4] - 72 - dB Operating mode; fi = 1 kHz [4] - 55 - dB Mute mode; fi = 100 Hz [4] - 80 - dB Standby mode; fi = 100 Hz [4] - 116 - dB Operating mode; fi = 100 Hz [4] - 72 - dB Operating mode; fi = 1 kHz [4] - 60 - dB Mute mode; fi = 100 Hz [4] - 72 - dB Standby mode; fi = 100 Hz [4] - 116 - dB 45 63 - kΩ between pins VSSPn and SGND Zi input impedance between one of the input pins and SGND Vn(o) output noise voltage Operating mode; Rs = 0 Ω; inputs shorted [5] - 160 - µV Mute mode [6] - 85 - µV [7] - 70 - dB - - 1 dB [8] - 75 - dB αcs channel separation |∆Gv| voltage gain difference αmute mute attenuation fi = 1 kHz; Vi = 2 V (RMS) CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB ηpo output power efficiency SE, RL = 6 Ω - 88 - % SE, RL = 8 Ω - 90 - % BTL, RL = 16 Ω - 90 - % high-side drain-source on-state resistance [9] - 380 - mΩ low-side drain-source on-state resistance [9] - 320 - mΩ RDSon(hs) RDSon(ls) TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 15 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier [1] Rs(L) is the series resistance of the low-pass LC filter inductor used in the application. [2] Output power is measured indirectly; based on RDSon measurement; see Section 13.3. [3] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter; max. limit is guaranteed but may not be 100 % tested. [4] Vripple = Vripple(max) = 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND. [5] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter. [6] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter. [7] Po = 1 W; fi = 1 kHz. [8] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz. [9] Leads and bond wires included. 12.3 Mono BTL application characteristics Table 11. Dynamic characteristics VDD = 25 V; VSS = −25 V; RL = 8 Ω; fi = 1 kHz; fosc = 350 kHz; Rs(L) < 0.1 Ω [1]; Tamb = 25 °C; unless otherwise specified. Symbol Po THD Parameter Conditions output power Tj = 85 °C; LLC = 22 µH; CLC = 680 nF (see Figure 10) total harmonic distortion Gv(cl) closed-loop voltage gain SVRR supply voltage rejection ratio Min Typ Max Unit THD = 0.5 %; RL = 8 Ω - 115 - W THD = 10 %; RL = 8 Ω - 155 - W Po = 1 W; fi = 1 kHz [3] - 0.02 - % Po = 1 W; fi = 6 kHz [3] - 0.05 - % - 36 - dB [2] between pin VDDPn and SGND Operating mode; fi = 100 Hz [4] - 72 - dB Operating mode; fi = 1 kHz [4] - 64 - dB Mute mode; fi = 100 Hz [4] - 86 - dB Standby mode; fi = 100 Hz [4] - 100 - dB Operating mode; fi = 100 Hz [4] - 72 - dB Operating mode; fi = 1 kHz [4] - 72 - dB Mute mode; fi = 100 Hz [4] - 86 - dB Standby mode; fi = 100 Hz [4] - 100 - dB 45 63 - kΩ between pin VSSPn and SGND Zi input impedance measured between one of the input pins and SGND Vn(o) output noise voltage Operating mode; Rs = 0 Ω [5] - 190 - µV Mute mode [6] - 45 - µV [7] - 75 - dB - 75 - dB αmute mute attenuation fi = 1 kHz; Vi = 2 V (RMS) CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) [1] Rs(L) is the series resistance of the low-pass LC filter inductor used in the application. [2] Output power is measured indirectly; based on RDSon measurement; see Section 13.3. [3] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter; max. limit is guaranteed but may not be 100 % tested. [4] Vripple = Vripple(max) = 2 V (p-p). [5] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter; low noise due to BD modulation. [6] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter. [7] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 16 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 13. Application information 13.1 Mono BTL application When using the power amplifier in a mono BTL application, the inputs of the two channels must be connected in anti-parallel and the phase of one of the inputs must be inverted; (see Figure 7). In principle, the loudspeaker can be connected between the outputs of the two single-ended demodulation filters. 13.2 Pin MODE To ensure a pop noise-free start-up, an RC time-constant must be applied to pin MODE. The bias-current setting of the VI converter input is directly related to the voltage on pin MODE. In turn the bias-current setting of the VI converters is directly related to the DC output offset voltage. A slow dV/dt on pin MODE results in a slow dV/dt for the DC output offset voltage, ensuring a pop noise-free transition between Mute and Operating modes. A time-constant of 500 ms is sufficient to guarantee pop noise-free start-up; see Figure 4, Figure 5 and Figure 8 for more information. 13.3 Estimating the output power 13.3.1 Single-Ended (SE) Maximum output power: P o ( 0.5% ) 2 RL -------------------------------------------------------- × 0.5 ( V DD – V SS ) × ( 1 – t w ( min ) × 0.5 f osc ) R L + R DSon ( hs ) + R s ( L ) = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------2R L (1) Maximum output current is internally limited to 6 A: 0.5 ( V DD – V SS ) × ( 1 – t w ( min ) × 0.5 f osc ) I o ( peak ) = -----------------------------------------------------------------------------------------------------R L + R DSon ( hs ) + R s ( L ) (2) Where: • • • • • • Po(0.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) Rs(L): series impedance of the filter coil tw(min): minimum pulse width (typical 100 ns, temperature dependent) fosc: oscillator frequency Remark: Note that Io(peak) should be less than 6 A (Section 8.3.2). Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and the voltage drop across the coil. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 17 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 13.3.2 Bridge-Tied Load (BTL) Maximum output power: P o ( 0.5% ) 2 RL ------------------------------------------------------------------- × ( V DD – V SS ) × ( 1 – t w ( min ) × 0.5 f osc ) R L + R DSon ( hs ) + R DSon ( ls ) = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2R L (3) Maximum output current internally limited to 6 A: ( V DD – V SS ) × ( 1 – t w ( min ) × 0.5 f osc ) I o ( peak ) = ----------------------------------------------------------------------------------------------R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R s ( L ) (4) Where: • • • • • • • • Po(0.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RDSon(ls): low-side RDSon of power stage output DMOS (temperature dependent) Rs(L): series impedance of the filter coil VP: single-sided supply voltage or 0.5 × (VDD + |VSS|) tw(min): minimum pulse width (typical 100 ns, temperature dependent) fosc: oscillator frequency Remark: Note that Io(peak) should be less than 6 A; see Section 8.3.2. Io(peak) is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and the voltage drop across the coil. 13.4 External clock To ensure duty cycle-independent operation, the external clock frequency is divided by two internally. The external clock frequency is therefore twice the internal clock frequency (typically 2 × 350 kHz = 700 kHz). If several Class D amplifiers are used in a single application, it is recommended that all the devices run at the same switching frequency. This can be achieved by connecting the OSC pins together and feeding them from an external oscillator. When using an external oscillator, it is necessary to force pin OSC to a DC level above SGND. This disables the internal oscillator and causes the PWM to switch at half the external clock frequency. The internal oscillator requires an external resistor ROSC, connected between pin OSC and pin VSSA. ROSC must be removed when using an external oscillator. The noise generated by the internal oscillator is supply voltage dependent. An external low-noise oscillator is recommended for low-noise applications running at high supply voltages. 13.5 Heatsink requirements An external heatsink must be connected to the TDA8922C. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 18 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier Equation 5 defines the relationship between maximum power dissipation before activation of TFB and total thermal resistance from junction to ambient. (5) T j – T amb Rth ( j – a ) = ----------------------P Power dissipation (P) is determined by the efficiency of the TDA8922C. Efficiency measured as a function of output power is given in Figure 20. Power dissipation can be derived as a function of output power as shown in Figure 19. mbl469 30 P (W) (1) 20 (2) 10 (3) (4) (5) 0 0 20 40 60 80 100 Tamb (°C) (1) Rth(j-a) = 5 K/W. (2) Rth(j-a) = 10 K/W. (3) Rth(j-a) = 15 K/W. (4) Rth(j-a) = 20 K/W. (5) Rth(j-a) = 35 K/W. Fig 9. Derating curves for power dissipation as a function of maximum ambient temperature TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 19 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier In the following example, a heatsink calculation is made for an 8 Ω BTL application with a ±30 V supply: The audio signal has a crest factor of 10 (the ratio between peak power and average power (20 dB)); this means that the average output power is 1⁄10 of the peak power. Thus, the peak RMS output power level is the 0.5 % THD level, i.e. 110 W. The average power is then 1⁄10 × 110 W = 11 W. The dissipated power at an output power of 11 W is approximately 5 W. When the maximum expected ambient temperature is 50 °C, the total Rth(j-a) becomes ( 150 – 50 ) ------------------------- = 20 K/W 5 Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a) Rth(j-c) (thermal resistance from junction to case) = 1.5 K/W Rth(c-h) (thermal resistance from case to heatsink) = 0.5 K/W to 1 K/W (dependent on mounting) So the thermal resistance between heatsink and ambient temperature is: Rth(h-a) (thermal resistance from heatsink to ambient) = 20 − (1.5 + 1) = 17.5 K/W The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in Figure 9. A maximum junction temperature Tj = 150 °C is taken into account. The maximum allowable power dissipation for a given heatsink size can be derived, or the required heatsink size can be determined, at a required power dissipation level; see Figure 9. 13.6 Pumping effects In a typical stereo single-ended configuration, the TDA8922C is supplied by a symmetrical supply voltage (e.g. VDD = 30 V and VSS = −30 V). When the amplifier is used in an SE configuration, a ‘pumping effect’ can occur. During one switching interval, energy is taken from one supply (e.g. VDD), while a part of that energy is returned to the other supply line (e.g. VSS) and vice versa. When the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source increases and the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on: • • • • • Speaker impedance Supply voltage Audio signal frequency Value of supply line decoupling capacitors Source and sink currents of other channels Pumping effects should be minimized to prevent the malfunctioning of the audio amplifier and/or the voltage supply source. Amplifier malfunction due to the pumping effect can trigger UVP, OVP or UBP. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 20 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier The most effective way to avoid pumping effects is to connect the TDA8922C in a mono full-bridge configuration. In the case of stereo single-ended applications, it is advised to connect the inputs in anti-phase (see Section 8.4 on page 11). The power supply can also be adapted; for example, by increasing the values of the supply line decoupling capacitors. 13.7 Application schematic Notes on the application schematic: • • • • Connect a solid ground plane around the switching amplifier to avoid emissions Place 100 nF capacitors as close as possible to the TDA8922C power supply pins Connect the heatsink to the ground plane or to VSSPn using a 100 nF capacitor Use a thermally conductive, electrically non-conductive, Sil-Pad between the TDA8922C heat spreader and the external heatsink • The heat spreader of the TDA8922C is internally connected to VSSD • Use differential inputs for the most effective system level audio performance with unbalanced signal sources. In case of hum due to floating inputs, connect the shielding or source ground to the amplifier ground. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 21 of 40 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TDA8922C_1 RVDDA 5.6 kΩ VDDA 10 Ω 470 Ω mode control VDDP VDDP GND CVSSP 470 µF 470 kΩ VSSP VSSP mute/ operating RVSSA VSSA 10 Ω 10 kΩ 10 kΩ mode control VDDP 4 OSC 6 5 CVP CVSSP 100 nF 100 nF 100 nF MODE Rev. 01 — 7 September 2009 − CIN 1 23 VDDP RSN 8 10 Ω CSN 220 pF CSN 220 pF 11 VSSP 10 3 9 470 nF OUT1 BOOT1 LLC CBO CLC 15 nF SGND − CIN 19 TDA8922CJ 15 IN2P LLC OUT2 VDDP 21 22 of 40 © NXP B.V. 2009. All rights reserved. CVSSA 220 nF 220 nF VSSA 17 CSTAB 470 nF VSSP VSSP2 RSN 10 Ω CVDDP CVP CVSSP 100 nF 100 nF 100 nF CPROT(1) VSSA (1) The value of CPROT can be in the range 10 pF to 220 pF (see Section 8.3.2) Fig 10. Typical application diagram 13 VDDP2 16 VSSD PROT VSSA STABI 7 VDDP VSSP CSN 220 pF CLC RZO 22 Ω − CZO + 100 nF CSN 220 pF VSSP 010aaa548 TDA8922C VDDA 12 18 CVDDA VDDA − CZO 100 nF CBO 470 nF 20 + 15 nF 14 IN2M RZO 22 Ω 2 × 75 W class-D power amplifier + CIN BOOT2 22 470 nF IN2 330 nF 470 nF T2 HFE > 80 2 IN1M 33 µH 22 µH VSSP CVDDP 470 nF IN1 6 Ω to 8 Ω 4 Ω to 8 Ω SGND n.c. n.c. n.c. IN1P 470 kΩ standby/ operating T1 HFE > 80 ROSC 30 kΩ + 10 µF 5.6 kΩ VSSA CIN SINGLE-ENDED OUTPUT FILTER VALUES LOAD LLC CLC +5 V CVP 22 µF VSSP1 CVDDP 470 µF VDDP1 Product data sheet +5 V TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 13.8 Curves measured in reference design (demonstration board) 010aaa565 10 THD+N (%) 1 (1) 10−1 (2) 10−2 (3) 10−3 10−2 10−1 1 102 10 103 Po (W) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), 2 × 6 Ω SE configuration. (1) fi = 6 kHz. (2) fi = 1 kHz. (3) fi = 100 Hz. Fig 11. THD + N as a function of output power, SE configuration with 2 × 6 Ω load 010aaa566 10 THD+N (%) 1 (1) 10−1 (2) 10−2 (3) 10−3 10−2 10−1 1 10 102 103 Po (W) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), 2 × 8 Ω SE configuration. (1) fi = 6 kHz. (2) fi = 1 kHz. (3) fi = 100 Hz. Fig 12. THD + N as a function of output power, SE configuration with 2 × 8 Ω load TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 23 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa567 10 THD+N (%) 1 10−1 (1) (2) 10−2 (3) 10−3 10−2 10−1 1 102 10 103 Po (W) VDD = 25 V, VSS = −25 V, fosc = 350 kHz (external oscillator), 1 × 8 Ω BTL configuration. (1) fi = 6 kHz. (2) fi = 1 kHz. (3) fi = 100 Hz. Fig 13. THD + N as a function of output power, BTL configuration with 1 × 8 Ω load 010aaa568 10 THD+N (%) 1 10−1 (1) 10−2 (2) 10−3 10 102 103 104 105 fi (Hz) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), 2 × 6 Ω SE configuration. (1) Po = 1 W. (2) Po = 10 W. Fig 14. THD + N as a function of frequency, SE configuration with 2 × 6 Ω load TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 24 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa569 10 THD+N (%) 1 10−1 (1) 10−2 (2) 10−3 10 102 103 104 105 fi (Hz) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), 2 × 8 Ω SE configuration. (1) Po = 1 W. (2) Po = 10 W. Fig 15. THD + N as a function of frequency, SE configuration with 2 × 8 Ω load 010aaa570 10 THD+N (%) 1 10−1 (1) 10−2 (2) 10−3 10 102 103 104 105 fi (Hz) VDD = 25 V, VSS = −25 V, fosc = 350 kHz (external oscillator), 1 × 8 Ω BTL configuration. (1) Po = 1 W. (2) Po = 10 W. Fig 16. THD + N as a function of frequency, BTL configuration with 1 × 8 Ω load TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 25 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa571 0 αcs (dB) −20 −40 −60 (1) −80 (2) −100 10 102 103 104 105 fi (Hz) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), 2 × 6 Ω SE configuration. 1 W and 10 W respectively. Fig 17. Channel separation as a function of frequency, SE configuration with 2 × 6 Ω load 010aaa572 0 αcs (dB) −20 −40 −60 (1) −80 (2) −100 10 102 103 104 105 fi (Hz) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), 2 × 8 Ω SE configuration. 1 W and 10 W respectively. Fig 18. Channel separation as a function of frequency, SE configuration with 2 × 8 Ω load TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 26 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa573 30 PD (W 20 (1) (2) (3) 10 0 10−2 10−1 101 1 102 103 Po (W) fi = 1 kHz; fosc = 350 kHz (external oscillator). (1) 2 × 6 Ω SE configuration; VDD = 32 V; VSS = −32 V. (2) 2 × 8 Ω SE configuration; VDD = 32 V; VSS = −32 V. (3) 1 × 8 Ω BTL configuration; VDD = 25 V; VSS = −25 V. Fig 19. Power dissipation as a function of output power per channel, SE configuration 010aaa574 100 η (%) (1) (2) (3) 80 60 40 20 0 0 20 40 60 80 100 120 140 160 Po (W) fi = 1 kHz, fosc = 350 kHz (external oscillator). (1) 2 × 8 Ω SE configuration; VDD = 32 V; VSS = −32 V. (2) 2 × 6 Ω SE configuration; VDD = 32 V; VSS = −32 V. (3) 1 × 8 Ω BTL configuration; VDD = 25 V; VSS = −25 V. Fig 20. Efficiency as a function of output power per channel, SE configuration TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 27 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa575 100 Po (W) (1) 80 (2) 60 (3) (4) 40 20 0 12.5 −12.5 17.5 −17.5 22.5 −22.5 32.5 VDD (V) −32.5 VSS (V) 27.5 −27.5 Infinite heat sink used. fi = 1 kHz, fosc = 350 kHz (external oscillator). (1) THD + N = 10 %, 6 Ω. (2) THD + N = 10 %, 8 Ω (3) THD + N = 0.5 %, 6 Ω (4) THD + N = 0.5 %, 8 Ω. Fig 21. Output power as a function of supply voltage, SE configuration 010aaa576 200 Po (W) 160 (1) 120 (2) 80 40 0 12.5 −12.5 15 −15 17.5 −17.5 20 −20 22.5 −22.5 27.5 VDD (V) −27.5 VSS (V) 25 −25 Infinite heat sink used. fi = 1 kHz, fosc = 350 kHz (external oscillator). (1) THD + N = 10 %, 8 Ω. (2) THD + N = 0.5 %, 8 Ω. Fig 22. Output power as a function of supply voltage, BTL configuration TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 28 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa577 40 (1) Gv(cl) (dB) (2) 30 (3) 20 10 102 10 103 104 105 fi (Hz) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), Vi = 100 mV, Ci = 330 pF. (1) 1 × 8 Ω BTL configuration; LLC = 15 µH, CLC = 680 nF, VDD = 25 V, VSS = −25 V. (2) 2 × 8 Ω SE configuration; LLC = 33 µH, CLC = 330 nF, VDD = 30 V, VSS = −30 V. (3) 2 × 6 Ω SE configuration; LLC = 33 µH, CLC = 330 nF, VDD = 30 V; VSS = −30 V. Fig 23. Closed-loop voltage gain as a function of frequency 010aaa578 −20 SVRR (dB) (1) −60 (2) −100 (3) −140 102 10 103 104 105 fi (Hz) Ripple on VDD, short on input pins. VDD = 30 V, VSS = −30 V, Vripple = 2 V (p-p), 2 × 8 Ω SE configuration. (1) Operating mode. (2) Mute mode. (3) Standby mode. Fig 24. SVRR as a function of ripple frequency, ripple on VDD TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 29 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa579 −20 SVRR (dB) (1) −60 (2) (3) −100 −140 102 10 103 104 105 fi (Hz) Ripple on VSS, short on input pins. VDD = 30 V, VSS = −30 V, Vripple = 2 V (p-p), 2 × 8 Ω SE configuration. (1) Mute mode. (2) Operating mode. (3) Standby mode. Fig 25. SVRR as a function of ripple frequency, ripple on VSS 010aaa586 0 SVRR (dB) −40 (1) −80 (2) (3) −120 102 10 103 104 105 fi (Hz) Ripple on VDD, short on input pins. VDD = 25 V, VSS = −25 V, Vripple = 2 V (p-p), 1 × 8 Ω BTL configuration. (1) Operating mode. (2) Mute mode. (3) Standby mode. Fig 26. SVRR as a function of ripple frequency, ripple on VDD TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 30 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa587 0 SVRR (dB) −40 (1) (2) −80 (3) −120 102 10 103 104 105 fi (Hz) Ripple on VSS, short on input pins. VDD = 25 V, VSS = −25 V, Vripple = 2 V (p-p), 1 × 8 Ω BTL configuration. (1) Operating mode. (2) Mute mode. (3) Standby mode. Fig 27. SVRR as a function of ripple frequency, ripple on VSS 010aaa580 102 Vo (V) 1 10−2 10−4 (1) (2) 10−6 0 2 4 6 VMODE (V) VDD = 30 V, VSS = −30 V, Vi = 100 mV. (1) Mode voltage down. (2) Mode voltage up. Fig 28. Output voltage as a function of mode voltage TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 31 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 010aaa581 −50 αmute (dB) −60 −70 (1) −80 (2) −90 10 102 103 104 105 fi (Hz) VDD = 30 V, VSS = −30 V, fosc = 350 kHz (external oscillator), Vi = 2 V (RMS). (1) 2 × 6 Ω SE configuration. (2) 2 × 8 Ω SE configuration. Fig 29. Mute attenuation as a function of frequency TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 32 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 14. Package outline DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 non-concave Dh x D Eh view B: mounting base side A2 d A5 A4 β E2 B j E E1 L2 L3 L1 L 1 e1 Z e 0 5 v M e2 m w M bp c Q 23 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A 2 mm A4 A5 bp c D (1) d D h E (1) e e1 e2 12.2 4.6 1.15 1.65 0.75 0.55 30.4 28.0 12 2.54 1.27 5.08 11.8 4.3 0.85 1.35 0.60 0.35 29.9 27.5 Eh E1 E2 j L 6 10.15 6.2 1.85 3.6 9.85 5.8 1.65 2.8 L1 L2 L3 m Q v w x β Z (1) 14 10.7 2.4 1.43 2.1 4.3 0.6 0.25 0.03 45° 13 9.9 1.6 0.78 1.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 98-02-20 02-04-24 SOT411-1 Fig 30. Package outline SOT411-1 (DBS23P) TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 33 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3 E D A x X c E2 y HE v M A D1 D2 12 1 pin 1 index Q A A2 E1 (A3) A4 θ Lp detail X 24 13 Z w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) D1 D2 E(2) E1 E2 e HE Lp Q +0.08 0.53 0.32 16.0 13.0 −0.04 0.40 0.23 15.8 12.6 1.1 0.9 11.1 10.9 6.2 5.8 2.9 2.5 1 14.5 13.9 1.1 0.8 1.7 1.5 bp c D(2) v w x y 0.25 0.25 0.03 0.07 Z θ 2.7 2.2 8° 0° Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-02-18 03-07-23 SOT566-3 Fig 31. Package outline SOT566-3 (HSOP24) TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 34 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 35 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 13. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 36 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Soldering of through-hole mount packages 16.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 16.2 Soldering by dipping or by solder wave Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.3 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 °C and 400 °C, contact may be up to 5 seconds. TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 37 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 16.4 Package related soldering information Table 14. Suitability of through-hole mount IC packages for dipping and wave soldering Package Soldering method Dipping Wave CPGA, HCPGA - suitable DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1] PMFP[2] - not suitable [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable. 17. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8922C_1 20090907 Product data sheet - - TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 38 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA8922C_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 7 September 2009 39 of 40 TDA8922C NXP Semiconductors 2 × 75 W class-D power amplifier 20. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.1.1 8.3.1.2 8.3.2 8.3.3 8.3.4 8.4 9 10 11 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.3.1 13.3.2 13.4 13.5 13.6 13.7 13.8 14 15 15.1 15.2 15.3 15.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pulse-width modulation frequency . . . . . . . . . . 8 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal protection . . . . . . . . . . . . . . . . . . . . . . 8 Thermal FoldBack (TFB) . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . . . . . . . . . 9 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9 Window Protection (WP). . . . . . . . . . . . . . . . . 10 Supply voltage protection . . . . . . . . . . . . . . . . 11 Differential audio inputs . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics. . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . 14 Stereo SE configuration characteristics . . . . . 15 Mono BTL application characteristics . . . . . . . 16 Application information. . . . . . . . . . . . . . . . . . 17 Mono BTL application . . . . . . . . . . . . . . . . . . . 17 Pin MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Estimating the output power . . . . . . . . . . . . . . 17 Single-Ended (SE) . . . . . . . . . . . . . . . . . . . . . 17 Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . 18 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 18 Heatsink requirements . . . . . . . . . . . . . . . . . . 18 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 20 Application schematic . . . . . . . . . . . . . . . . . . . 21 Curves measured in reference design (demonstration board) . . . . . . . . . . . . . . . . . . 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 Soldering of SMD packages . . . . . . . . . . . . . . 35 Introduction to soldering . . . . . . . . . . . . . . . . . 35 Wave and reflow soldering . . . . . . . . . . . . . . . 35 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 35 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 36 16 16.1 16.2 16.3 16.4 17 18 18.1 18.2 18.3 18.4 19 20 Soldering of through-hole mount packages . Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . Soldering by dipping or by solder wave . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 37 38 38 39 39 39 39 39 39 40 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 September 2009 Document identifier: TDA8922C_1