TDA8933B Class D audio amplifier Rev. 01 — 23 October 2008 Preliminary data sheet 1. General description The TDA8933B is a high-efficiency class D amplifier with low power dissipation. The continuous time output power is 2 × 10 W in a stereo half-bridge application (RL = 8 Ω) or 1 × 20 W in a mono full-bridge application (RL =16 Ω). Due to the low power dissipation the device can be used without any external heat sink when playing music. Due to the implementation of Thermal Foldback (TF) the device remains operating with considerable music output power without the need for an external heat sink, even for high supply voltages and/or lower load impedances. The device has two full differential inputs driving two independent outputs. It can be used in a mono full-bridge configuration (Bridge-Tied Load (BTL)) or as stereo half-bridge configuration (Single-Ended (SE)). 2. Features Operating voltage from 10 V to 36 V asymmetrical or ±5 V to ±18 V symmetrical Mono bridge-tied load (full-bridge) or stereo single-ended (half-bridge) application Application without heat sink using thermally enhanced small outline package High efficiency and low-power dissipation Thermal foldback to avoid audio holes Current limiting to avoid audio holes Full short circuit proof across load and to supply lines (using advanced current protection) n Internal or external oscillator (master-slave setting) that can be switched n No pop noise n Full differential inputs n n n n n n n 3. Applications n n n n n n Flat-panel television sets Flat-panel monitor sets Multimedia systems Wireless speakers Mini/micro systems Home sound sets TDA8933B NXP Semiconductors Class D audio amplifier 4. Quick reference data Table 1. Quick reference data General; Vp = 25 V, fosc = 320 kHz, Tamb = 25 °C unless specified otherwise Symbol Parameter Conditions Min Typ Max Unit 10 25 36 V VP supply voltage asymmetrical supply IP supply current Sleep mode - 0.6 1.0 mA Iq(tot) total quiescent current Operating mode; no load; no snubbers or filter connected - 40 50 mA 7.5 8.5 - W 9.3 10.3 - W 15.4 17.1 - W 18.9 20.6 - W Stereo SE channel; Rs < 0.1 Ω[1] Po(RMS) RMS output power continuous time output power per channel[2] RL = 4 Ω; VP = 17 V THD+N = 10 %, fi = 1 kHz RL = 8 Ω; VP = 25 V THD+N = 10 %, fi = 1 kHz Mono BTL channel; Rs < 0.1 Ω[1] Po(RMS) RMS output power continuous time output power[2] RL = 8 Ω; VP = 17 V THD+N = 10 %, fi = 1 kHz RL = 16 Ω; VP = 25 V THD+N = 10 %, fi = 1 kHz [1] Rs is the total series resistance of an inductor and an ESR single-ended capacitor in the application. [2] Output power is measured indirectly, based on RDSon measurement. 5. Ordering information Table 2. Ordering information Type number Package Name TDA8933BTW Description Version HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad TDA8933B_1 Preliminary data sheet SOT549-1 © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 2 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 6. Block diagram OSCREF OSCIO 10 VDDA 31 8 28 IN1P 2 OSCILLATOR 29 DRIVER HIGH PWM MODULATOR VSSD IN1N INREF IN2P 26 DRIVER LOW 3 21 MANAGER 12 20 15 DRIVER HIGH PWM MODULATOR IN2N 27 CTRL 22 CTRL 23 DRIVER LOW 14 PROTECTIONS: OVP, OCP, OTP, UVP, TF, WP VDDP1 OUT1 VSSP1 BOOT2 VDDP2 OUT2 VSSP2 VDDA STABILIZER 11 V DIAG BOOT1 4 25 STAB1 VSSP1 VDDA STABILIZER 11 V CGND POWERUP 7 6 REGULATOR 5 V 18 DREF VSSD 5 VDDA 11 30 TEST STAB2 VSSP2 MODE ENGAGE 24 TDA8933BTW 13 VSSA 19 HVPREF HVP1 HVP2 HALF SUPPLY VOLTAGE 9 1, 16, 17, 32 010aaa455 VSSA Fig 1. VSSD(HW) Block diagram TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 3 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 7. Pinning information 7.1 Pinning VSSD(HW) 1 IN1P 2 32 VSSD(HW) 31 OSCIO IN1N 3 30 HVP1 DIAG 4 ENGAGE 5 29 VDDP1 28 BOOT1 POWERUP 6 27 OUT1 CGND 7 VDDA 8 26 VSSP1 25 STAB1 VSSA 9 TDA8933BTW 24 STAB2 23 VSSP2 22 OUT2 OSCREF 10 HVPREF 11 INREF 12 21 BOOT2 TEST 13 IN2N 14 20 VDDP2 19 HVP2 IN2P 15 18 DREF 17 VSSD(HW) VSSD(HW) 16 010aaa456 Fig 2. Pin configuration diagram (HTSSOP32 package) 7.2 Pin description Table 3. Pinning description Symbol Pin Description VSSD(HW) 1 negative digital supply voltage and handle wafer connection IN1P 2 positive audio input for channel 1 IN1N 3 negative audio input for channel 1 DIAG 4 diagnostic output; open-drain ENGAGE 5 engage input to switch between Mute mode and Operating mode POWERUP 6 power-up input to switch between Sleep mode and Mute mode CGND 7 control ground; reference for POWERUP, ENGAGE and DIAG VDDA 8 positive analog supply voltage VSSA 9 negative analog supply voltage OSCREF 10 input internal oscillator setting (only master setting) HVPREF 11 decoupling of internal half supply voltage reference INREF 12 decoupling for input reference voltage TEST 13 test signal input; for testing purpose only IN2N 14 negative audio input for channel 2 IN2P 15 positive audio input for channel 2 VSSD(HW) 16 negative digital supply voltage and handle wafer connection VSSD(HW) 17 negative digital supply voltage and handle wafer connection DREF 18 decoupling of internal (reference) 5 V regulator for logic supply TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 4 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 3. Pinning description …continued Symbol Pin Description HVP2 19 half supply output voltage 2 for charging single-ended capacitor for channel 2 VDDP2 20 positive power supply voltage for channel 2 BOOT2 21 bootstrap high-side driver channel 2 OUT2 22 Pulse Width Modulated (PWM) output channel 2 VSSP2 23 negative power supply voltage for channel 2 STAB2 24 decoupling of internal 11 V regulator for channel 2 drivers STAB1 25 decoupling of internal 11 V regulator for channel 1 drivers VSSP1 26 negative power supply voltage for channel 1 OUT1 27 PWM output channel 1 BOOT1 28 bootstrap high-side driver for channel 1 VDDP1 29 positive power supply voltage for channel 1 HVP1 30 half supply output voltage 1 for charging single-ended capacitor for channel 1 OSCIO 31 oscillator input in slave configuration or oscillator output in master configuration VSSD(HW) 32 negative digital supply voltage and handle wafer connection Exposed die pad[1] - [1] The exposed die pad has to be connected to VSSD(HW). 8. Functional description 8.1 General The TDA8933B is a mono full-bridge or stereo half-bridge audio power amplifier using class D technology. The audio input signal is converted into a PWM signal via an analog input stage and a PWM modulator. To enable the output power Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side. A 2nd-order low-pass filter in the application converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8933B contains two independent half bridges with full differential input stages. The loudspeakers can be connected in the following configurations: • Mono full-bridge: Bridge-Tied Load (BTL) • Stereo half-bridge: Single-Ended (SE) The TDA8933B contains circuits common to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. The following protections are built-in: thermal foldback and overtemperature, current and voltage protections. TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 5 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 8.2 Mode selection and interfacing The TDA8933B can be switched to one of four operating modes using pins POWERUP and ENGAGE: • Sleep mode: with low supply current. • Mute mode: the amplifiers are switching to idle (50 % duty cycle), but the audio signal at the output is suppressed by disabling the Vl-converter input stages. The capacitors on pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical supply only) • Operating mode: the amplifiers are fully operational with an output signal • Fault mode Both pins POWERUP and ENGAGE refer to pin CGND. Table 4 shows the different modes as a function of the voltages on the POWERUP and ENGAGE pins. Table 4. Mode selection for the TDA8933B Mode Pin POWERUP[1] ENGAGE[1] DIAG Sleep < 0.8 V < 0.8 V undefined Mute 2 V to 6 V < 0.8 V >2V Operating 2 V to 6 V 2.4 V to 6 V >2V Fault 2 V to 6 V undefined < 0.8 V [1] When there are symmetrical supply conditions, the voltage applied to pins POWERUP and ENGAGE must never exceed the supply voltage (VDDA, VDDP1 or VDDP2). If the transition between Mute mode and Operating mode is controlled via a time constant, the start-up will be pop-free since the DC output offset voltage is applied gradually to the output. The bias current setting of the V/I-converters is related to the voltage on pin ENGAGE. • Mute mode: the bias current setting of the V/I-converters is zero (V/I-converters disabled). • Operating mode: the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between Mute mode and Operating mode can be generated by applying a capacitor on pin ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF. TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 6 of 42 TDA8933B NXP Semiconductors Class D audio amplifier VP POWERUP DREF OSCIO HVPREF HVP1, HVP2 ENGAGE 2.0 V (typical) 1.2 V (typical) OUT1, OUT2 ≤ 0.8 V AUDIO AUDIO AUDIO PWM PWM PWM DIAG operating mute operating fault operating sleep 010aaa457 Fig 3. Start-up sequence 8.3 Pulse Width Modulation (PWM) frequency The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz. Using a 2nd-order low-pass filter in the application results in an analog audio signal across the loudspeaker. The PWM switching frequency can be set by an external resistor Rosc connected between pin OSCREF and VSSD(HW). The carrier frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ, the carrier frequency is set to a typical value of 320 kHz (see Figure 4). If two or more TDA8933B devices are used in the same audio application, it is recommended to synchronize the switching frequency of all devices. See Section 14.6 for more information. The value of the resistor also sets the frequency of the carrier and can be calculated with Equation 1: 9 12.45x10 f osc = ------------------------R osc (1) Where: fosc = oscillator frequency (Hz) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 7 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Rosc = oscillator resistor (Ω) (on pin OSCREF) 010aaa531 550 fosc (kHz) 450 350 250 25 30 35 40 45 Rosc (kΩ) Fig 4. Oscillation frequency as a function of Rosc Table 5 summarizes how to configure the TDA8933B in master or slave configuration. For device synchronization see Section 14.6. Table 5. Master or slave configuration Configuration Pin OSCREF OSCIO Master Rosc > 25 kΩ to VSSD(HW) output Slave Rosc = 0 Ω; shorted to VSSD(HW) input 8.4 Protections The following protections are implemented in the TDA8933B: • • • • • Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protections – UnderVoltage Protection (UVP) – OverVoltage Protection (OVP) – UnBalance Protection (UBP) • Electro Static Discharge (ESD) The behavior of the device under the different fault conditions differs according to the protection activated and is described in the following sections. 8.4.1 Thermal Foldback (FT) If the junction temperature of the TDA8933B exceeds the threshold level (Tj > 140 °C), the gain of the amplifier is decreased gradually to a level where the combination of dissipation (P) and the thermal resistance from junction to ambient (Rth(j-a)) results in a junction temperature of around the threshold level. TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 8 of 42 TDA8933B NXP Semiconductors Class D audio amplifier This means that the device will not switch off completely, but remains operational at lower output power levels. With music output signals, this feature enables high peak output powers while still operating without any external heat sink other than the copper area on the Printed-Circuit Board (PCB). If the junction temperature still increases due to external causes the OTP shuts down the amplifier completely. 8.4.2 OverTemperature Protection (OTP) If the junction temperature Tj > 155 °C the power stage will shut down immediately. 8.4.3 OverCurrent Protection (OCP) The OCP can distinguish between an impedance drop of the loudspeaker and a low-ohmic short circuit. If an impedance drop causes the output current to exceed 2 A, e.g. due to dynamic behavior of the loudspeaker, the amplifier will start limiting the current above 2 A. Therefore the current limiting feature will avoid audio interruption (audio holes) due to a loudspeaker impedance drop. If a fault condition causes the output current to exceed 2 A, like a short circuit between the loudspeaker terminals or from the loudspeaker terminal to the supply lines or ground, the amplifier is switched off and a timer of 100 ms is started. The DIAG is set low for the first 50 ms of the timer. The timer will keep the power stage disabled for at least 100 ms. Every 100 ms the amplifier will try to restart as long as the short circuit between the loudspeaker terminals remains. The average power dissipation in the TDA8933B will be low because the short circuit current will flow only during a very short time every 100 ms. If a short circuit occurs between a loudspeaker terminal and the supply lines or ground, the activated WP will keep the power stage disabled (no restart every 100 ms). Restart will take place after removing this short. 8.4.4 Window Protection (WP) The window protection protects the amplifier against the following fault conditions: • During the start-up sequence, when pin POWERUP is switched from Sleep mode to Mute mode. In the event of a short circuit at one of the output terminals to VDDP1, VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8933B waits for open circuit outputs. Because the check is done before enabling the power stages no large currents will flow in the event of a short circuit. • When the amplifier is shut down completely due to activation of the OCP or because of a short circuit to one of the supply lines, then during restart (i.e. after 100 ms) the window protection will be activated. As a result the amplifier will not start up until the short circuit to the supply lines has been removed. 8.4.5 Supply voltage protection If the supply voltage drops below 10 V the UnderVoltage Protection (UVP) circuit is activated and the system will shut down directly. This switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level the power stage is restarted after 100 ms. TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 9 of 42 TDA8933B NXP Semiconductors Class D audio amplifier If the supply voltage exceeds 36 V the OVP circuit is activated and the power stages will shut down. It is enabled again as soon as the supply voltage drops below the threshold level. The power stage is restarted after 100 ms. Supply voltages > 40 V may damage the TDA8933B. Two conditions should be distinguished here: • If the supply voltage is pumped to higher values by the TDA8933B application itself (see also Section 14.8), the OVP is triggered and the TDA8933B is shut down. The supply voltage will decrease and the TDA8933B is thus protected against any overstress. • If a supply voltage > 40 V is caused by other or by external causes the TDA8933B will shut down, but the device can still be damaged since the supply voltage in this case will remain > 40 V. The OVP protection is not a supply clamp. An additional UnBalance Protection (UBP) circuit compares the positive analog supply voltage VDDA with the negative analog supply voltage VSSA and is triggered if the difference between them exceeds a certain level. This level depends on the sum of both supply voltages. The UBP threshold levels can be defined as follows: • LOW-level threshold: VP(th)(ubp)l < 8/5 × VHVPREF • HIGH-level threshold: VP(th)(ubp)h > 8/3 × VHVPREF In a symmetrical supply the UBP is released when the unbalance of the supply voltage is within 6 % of its starting value. Table 6 shows an overview of all protections and their effect on the output signal. Table 6. Protection Overview of protections for the TDA8933B Restart When fault is removed OTP no yes OCP yes no WP yes no UVP no yes OVP no yes UBP no yes TDA8933B_1 Preliminary data sheet Every 100 ms © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 10 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 8.5 Diagnostic input and output Except for TF, whenever one of the protections is triggered pin DIAG is activated to LOW level (see Table 6). An internal current source will pull up the open-drain DIAG output to approximately 2.5 V. This current source can deliver approximately 50 µA. The DIAG pin refers to pin CGND. The diagnostic output signal during different short circuit conditions is illustrated in Figure 5. Using pin DIAG as input, a voltage < 0.8 V will put the device into Fault mode. Vo Vo 2.4 V 2.4 V amplifier restart 0V ≈ 50 ms ≈ 50 ms no restart 0V short to supply line shorted load 001aad759 Fig 5. Diagnostic output for different short circuit conditions 8.6 Differential inputs For a high common-mode rejection ratio and for maximum flexibility in the application the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the two channels can be inverted so that the amplifier can then operate as a mono BTL amplifier. The input configuration for a mono BTL application is illustrated in Figure 6. In the SE configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies and minimizes supply pumping (see also Section 14.8). IN1P OUT1 IN1N audio input IN2P OUT2 IN2N 001aad760 Fig 6. Input configuration for a mono BTL application TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 11 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 8.7 Output voltage buffers When pin POWERUP is set HIGH the half-supply output voltage buffers are switched on in asymmetrical configuration. The start-up will then be pop-free because the device starts switching when the capacitor on pin HVPREF and the SE capacitors are completely charged. Output voltage buffer pins: • Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its value. The half-supply voltage output is disabled when the TDA8933B is used in a symmetrical supply application. • Pin HVPREF: This output voltage reference buffer charges the capacitor on pin HVPREF. • Pin INREF: This output voltage reference buffer charges the input reference capacitor on pin INREF, which applies the bias voltage for the inputs. 9. Internal circuitry Table 7. Internal circuitry Pin Symbol 1 VSSD(HW) Equivalent circuit 1, 16, 17, 32 16 VDDA 17 32 VSSA 001aad784 2 IN1P 3 IN1N 12 INREF 14 IN2N 15 IN2P VDDA 2 kΩ ± 20 % 2, 15 V/I 48 kΩ ± 20 % 12 HVPREF 48 kΩ ± 20 % 2 kΩ ± 20 % 3, 14 V/I VSSA TDA8933B_1 Preliminary data sheet 001aad785 © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 12 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 7. Internal circuitry Pin Symbol 4 DIAG Equivalent circuit VDDA 2.5 V 50 µA 500 Ω ± 20 % 4 100 kΩ ± 20 % CGND VSSA 001aaf607 5 ENGAGE VDDA 2.8 V Iref = 50 µA 2 kΩ ± 20 % 5 100 kΩ ± 20 % VSSA CGND 001aaf608 6 POWERUP VDDA 6 VSSA 7 CGND 001aad788 CGND VDDA 7 VSSA 001aad789 TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 13 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 7. Internal circuitry Pin Symbol 8 VDDA Equivalent circuit 8 VSSA VSSD 001aad790 9 VSSA VDDA 9 VSSD 001aad791 10 OSCREF VDDA Iref 10 VSSA 11 001aad792 HVPREF VDDA 11 VSSA 13 001aaf604 TEST VDDA 13 VSSA 001aad795 TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 14 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 7. Internal circuitry Pin Symbol 18 DREF Equivalent circuit VDD 18 VSSD 001aag025 19 HVP2 30 HVP1 VDDA 19, 30 VSSA 20 VDDP2 23 VSSP2 26 VSSP1 29 VDDP1 001aag026 20, 29 23, 26 001aad798 21 BOOT2 28 BOOT1 21, 28 OUT1, OUT2 001aad799 22 OUT2 27 OUT1 VDDP1, VDDP2 22, 27 VSSP1, VSSP2 TDA8933B_1 Preliminary data sheet 001aag027 © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 15 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 7. Internal circuitry Pin Symbol 24 STAB2 25 STAB1 Equivalent circuit VDDA 24, 25 VSSP1, VSSP2 31 001aag028 OSCIO DREF 31 VSSD 001aag029 10. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VP supply voltage asymmetrical supply[1] −0.3 +40.1 V Vx voltage on pin x IN1P, IN1N, IN2P, IN2N [2] −5 +5 V OSCREF, OSCIO, TEST [3] VSSD(HW) − 0.3 5 V POWERUP, ENGAGE, DIAG [4] VCGND − 0.3 6 V all other pins [5] VSS − 0.3 VDD + 0.3 V [6] 2 - A IORM repetitive peak output current Tj junction temperature - 150 °C Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C P power dissipation Vesd electrostatic discharge voltage maximum output current limiting - 5 W human body model [7] −2000 +2000 V machine model [8] −200 +200 V [1] VP = VDDP1 − VSSP1 = VDDP2 − VSSP2 [2] Measured with respect to pin INREF; Vx < VDD + 0.3 V. [3] Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V. [4] Measured with respect to pin CGND; Vx < VDD + 0.3 V. [5] VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2. [6] Current limiting concept. [7] Human Body Model (HBM); Rs = 1500 Ω; C = 100 pF. For pins 2, 3, 11, 14 and 15 Vesd = 1800V. TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 16 of 42 TDA8933B NXP Semiconductors Class D audio amplifier [8] Machine Model (MM); Rs = 0 Ω; C = 200 pF; L = 0.75 µH. 11. Thermal characteristics Table 9. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient free air natural convection Ψj-lead thermal characterization parameter from junction to lead Ψj-top thermal characterization parameter from junction to top of package Rth(j-c) thermal resistance from junction to case Min Typ Max Unit JEDEC test board [1] - 47 50 K/W Two-layer application board [2] - 48 - K/W Three-layer application board [3] - 30 - K/W - - 30 K/W - - 2 K/W - 4.0 - K/W [4] free-air natural convection [1] Measured on a JEDEC high K-factor test board (standard EIA/JESO 51-7) in free air with natural convection. [2] Measured on a two-layer application board (55 mm × 40 mm), 35 µm copper, FR4 base material in free air with natural convection. [3] Measured on a three-layer application board (70 mm × 50 mm), 35 µm copper, FR4 base material in free air with natural convection. [4] Strongly dependent on where the measurement is taken on the package. 12. Static characteristics Table 10. Characteristics VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit supply voltage asymmetrical supply 10 25 36 V symmetrical supply ±5 ±12.5 ±18 V Supply VP IP supply current Iq(tot) total quiescent current Operating mode; no load, no snubbers or filter connected Sleep mode - 0.6 1.0 mA - 40 50 mA Tj = 25 °C - 380 - mΩ Tj = 125 °C - 545 - mΩ 0 - 6.0 V VI = 3 V - 1 20 µA Series resistance output switches RDSon drain-source on-state resistance Power-up input: pin POWERUP[1] VI input voltage II input current VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - 6.0 V TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 17 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 10. Characteristics …continued VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise. Symbol Parameter Engage input: pin Conditions Min Typ Max Unit 2.4 2.8 3.1 V ENGAGE[1] VO output voltage VI input voltage IO output current VIL VIH 0 - 6.0 V - 50 60 µA LOW-level input voltage 0 - 0.8 V HIGH-level input voltage 2.4 - 6.0 V protection activated; see Table 6 - - 0.8 V Operating mode 2 2.5 3.3 V Reference to VSSA - 2.1 - V VI = 3 V Diagnostic output: pin DIAG[1] VO output voltage Bias voltage for inputs: pin INREF VO(bias) bias output voltage Half-supply voltage Pins HVP1 and HVP2 VO output voltage half-supply voltage to charge SE capacitor 0.5VP − 0.2 V 0.5VP 0.5VP + 0.2 V V IO output current VHVP1 = VHVP2 = VO − 1 V - 50 - output voltage half-supply reference voltage in Mute mode 0.5VP − 0.2 V 0.5VP 0.5VP + 0.2 V V 4.5 4.8 5.1 V Mute mode - - 15 mV Operating mode - - 100 mV Mute mode - - 20 mV Operating mode - - 150 mV 10 11 12 V mA Pin HVPREF VO Reference voltage for internal logic: pin DREF VO output voltage reference to VSSA Amplifier outputs: pins OUT1 and OUT2 VO(offset) output offset voltage SE; with respect to HVPREF BTL Stabilizer output: pins STAB1, STAB2 VO output voltage Mute mode and Operating mode; with respect to pins VSSP1 and VSSP2 Voltage protections VP(uvp) undervoltage protection supply voltage 8.0 9.5 9.9 V VP(ovp) overvoltage protection supply voltage 36.1 38.5 40 V TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 18 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 10. Characteristics …continued VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit VP(th)(ubp)l low unbalance protection threshold supply voltage VP = 22 V; VHVPREF = 11 V - - 18 V VP(th)(ubp)h high unbalance protection threshold supply voltage VP = 22 V; VHVPREF = 11 V 29 - - V current limiting 2.0 2.5 - A Current protections IO(ocp) overcurrent protection output current Temperature protection Tact(th_prot) thermal protection activation temperature 155 - 160 °C Tact(th_fold) thermal foldback activation temperature 140 - 150 °C Oscillator reference: pin OSCIO[2] VIH HIGH-level input voltage 4.0 - 5.0 V VIL LOW-level input voltage 0 - 0.8 V VOH HIGH-level output voltage 4.0 - 5.0 V VOL LOW-level output voltage 0 - 0.8 V Nslave(max) maximum number of slaves 12 - - - driven by one master [1] Measured with respect to pin CGND. [2] Measured with respect to pin VSSD(HW). 13. Dynamic characteristics Table 11. Switching characteristics VP = 25 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Rosc = 39 kΩ - 320 - kHz range 300 - 500 kHz Internal oscillator fosc oscillator frequency Timing PWM output: pins OUT1 and OUT2 tr rise time IO = 0 A - 10 - ns tf fall time IO = 0 A - 10 - ns tw(min) minimum pulse width IO = 0 A - 80 - ns TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 19 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 12. SE characteristics VP = 25 V, RL = 2 × 8 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [1] and Tamb = 25 °C; unless otherwise specified. Symbol Po(RMS) Parameter RMS output power Conditions continuous time output power per Min Typ Max Unit channel[2] RL = 4 Ω; VP = 17 V THD+N = 0.5 %, fi = 1 kHz 5.9 6.8 - W THD+N = 0.5 %, fi = 100 Hz - 6.8 - W THD+N = 10 %, fi = 1 kHz 7.5 8.5 - W THD+N = 10 %, fi = 100 Hz - 8.5 - W THD+N = 0.5 %, fi = 1 kHz 7.3 8.2 - W THD+N = 0.5 %, fi = 100 Hz - 8.2 - W THD+N = 10 %, fi = 1 kHz 9.3 10.3 - W - 10.3 - W fi = 1 kHz - 0.014 0.1 % fi = 6 kHz - 0.05 0.1 % 29 30 31 dB - 0.5 1 dB 70 80 - dB fi = 100 Hz - 60 - dB fi = 1 kHz 40 50 - dB RL = 8 Ω; VP = 25 V THD+N = 10 %, fi = 100 Hz THD+N total harmonic distortion-plus-noise Gv(cl) closed-loop voltage gain |∆GV| voltage gain difference Po = 1 W [3] Vi =100 mV; no load αcs channel separation Po = 1 W; fi = 1 kHz SVRR supply voltage ripple rejection Operating mode [4] |Zi| input impedance differential 70 100 - kΩ Vn(o) output noise voltage Operating mode; Ri = 0 Ω [5] - 100 150 µV Mute mode [5] - 70 100 µV VO(mute) mute output voltage Mute mode; Vi = 1 V (RMS) - 100 - µV CMRR common mode rejection ratio Vi(cm) = 1 V (RMS) - 75 - dB ηpo output power efficiency VP = 17 V; RL = 4 Ω; Po = 8 W/channel 86 89 - % VP = 25 V; RL = 8 Ω; Po = 10 W/channel 89 92 - % [1] RS is the total series resistance of an inductor and a ESR single ended capacitor in the application. [2] Output power is measured indirectly; based on RDSon measurement. [3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. [4] Vripple = 2 V (p-p); Ri = 0 Ω. [5] B = 20 Hz to 20 kHz, AES17 brick wall. TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 20 of 42 TDA8933B NXP Semiconductors Class D audio amplifier Table 13. BTL characteristics VP = 25 V, RL = 16 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [1] and Tamb = 25 °C; unless otherwise specified. Symbol Po(RMS) Parameter RMS output power Conditions Min Typ Max Unit THD+N = 0.5 %, fi = 1 kHz 11.9 13.7 - W THD+N = 0.5 %, fi = 100 Hz - 13.7 - W THD+N = 10 %, fi = 1 kHz 15.4 17.1 - W THD+N = 10 %, fi = 100 Hz - 17.1 - W THD+N = 0.5 %, fi = 1 kHz 14.9 16.5 - W THD+N = 0.5 %, fi = 100 Hz - 16.5 - W THD+N = 10 %, fi = 1 kHz 18.9 20.6 - W - 20.6 - W fi = 1 kHz - 0.01 0.1 % fi = 6 kHz - 0.04 0.1 % 35 36 37 dB 35 50 - kΩ continuous time output power[2] RL = 8 Ω; VP = 17 V RL = 16 Ω; VP = 25 V THD+N = 10 %, fi = 100 Hz THD+N total harmonic distortion-plus-noise Po = 1 W Gv(cl) closed-loop voltage gain |Zi| input impedance differential Vn(o) output noise voltage Ri = 0 Ω [3] Operating mode [4] - 100 150 µV Mute mode [4] - 70 100 µV VO(mute) mute output voltage Mute mode; Vi = 1 V (RMS) - 100 - µV CMRR common mode rejection ratio Vi(cm) = 1 V (RMS) - 75 - dB ηpo output power efficiency Po = 17 W; VP = 17 V; RL = 8 Ω 89 91 - % 92 94 - % Po = 21 W; VP = 25 V; RL = 16 Ω [5] [1] RS is the total series resistance of an inductor and a ESR single ended capacitor in the application. [2] Output power is measured indirectly; based on RDSon measurement. [3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. [4] B = 22 Hz to 20 kHz, AES17 brick wall. [5] 2 ⋅ Po η po = ---------------------2 ⋅ Po + P 14. Application information 14.1 Output power estimation The output power Po at THD+N = 0.5 %, just before clipping, for the SE and the BTL configurations can be estimated using Equation 2 and Equation 3. TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 21 of 42 TDA8933B NXP Semiconductors Class D audio amplifier SE configuration: P o ( 0.5% ) 2 RL --------------------------------------------------------- × (1 – t × f ) × V w ( min ) osc P R L + R DSon + R s + R ESR = -----------------------------------------------------------------------------------------------------------------------------------------8 × RL (2) BTL configuration: P o ( 0.5% ) 2 RL ----------------------------------------------------- × (1 – t × f osc ) × V P w ( min ) R L + 2 × ( R DSon + R s ) = -------------------------------------------------------------------------------------------------------------------------------------2 × RL (3) Where: • • • • • • • VP = supply voltage VDDP1 − VSSP1 (V) or VDDP2 − VSSP2 (V) RL = load resistance (Ω) RDSon = drain-source on-state resistance (Ω) Rs = series resistance output inductor (Ω) RESR = Equivalent Series Resistance SE capacitance (Ω) tw(min) = minimum pulse width(s); 80 ns typical fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 kΩ The output power Po at THD+N = 10 % can be estimated by: P o ( 10% ) = 1.25 × P o ( 0.5% ) (4) Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at different load impedances. The output power is calculated with: RDSon = 0.38 Ω (at Tj = 25 °C), Rs = 0.05 Ω, RESR = 0.05 Ω and IO(ocp) = 2 A (minimum). TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 22 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 010aaa499 20 010aaa500 20 (3) Po (10 %) (W/channel) Po (0.5 %) (W/channel) (3) 16 16 (2) 12 (2) 12 (1) (1) 8 8 4 4 0 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) a. THD+N = 0.5 % 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) b. THD+N = 10 % (1) RL = 4 Ω (2) RL = 6 Ω (3) RL = 8 Ω When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details. Fig 7. SE output power as a function of supply voltage 010aaa501 40 Po (0.5 %) (W) 010aaa502 40 (3) Po (10 %) (W) (3) 30 30 20 20 (2) (2) (1) (1) 10 10 0 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) a. THD+N = 0.5 % 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) b. THD+N = 10 % (1) RL = 6 Ω (2) RL = 8 Ω (3) RL = 16 Ω When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details. Fig 8. BTL output power as a function of supply voltage TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 23 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 14.2 Output current limitation The peak output current IO(max) is internally limited to a minimum value of 2 A. During normal operation the output current should not exceed this threshold level, otherwise the signal will be distorted. The peak output current in SE or BTL configurations can be calculated using Equation 5 and Equation 6. SE configuration: 0.5 × V P I O ( max ) ≤ ---------------------------------------------------------- ≤ 2 A R L + R DSon + R s + R ESR (5) BTL configuration: VP I O ( max ) ≤ ------------------------------------------------------ ≤ 2 A R L + 2 × ( R DSon + R s ) (6) Where: • • • • • VP = supply voltage VDDP1 − VSSP1 (V) or VDDP2 − VSSP2 (V) RL = load resistance (Ω) RDSon = drain-source on-state resistance (Ω) Rs = series resistance output inductor (Ω) RESR = Equivalent Series Resistance SE capacitance (Ω) Example: An 8 Ω speaker in the BTL configuration can be used up to a supply voltage of 18 V without running into current limiting. Current limiting (clipping) will avoid audio holes but produces a similar distortion to voltage clipping. 14.3 Speaker configuration and impedance For a flat frequency response (second-order Butterworth filter with an output frequency of 40 kHz) it is necessary to change the low-pass filter components LLC and CLC according to the speaker configuration and impedance. Table 14 shows the values required in practice. Table 14. Filter component values Configuration RL (Ω) LLC (µH) CLC (nF) SE 4 22 680 6 33 470 8 47 330 8 22 680 16 47 330 BTL TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 24 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 14.4 Single-ended capacitor The SE capacitor forms a high-pass filter with the speaker impedance. This means that the frequency response will roll off with 20 dB per decade below f−3dB and a cut-off frequency of 3 dB. The 3 dB cut-off frequency is equal to: 1 f –3dB = ----------------------------------2π × R L × C SE (7) Where: • f−3dB = 3 dB cut-off frequency (Hz) • RL = load resistance (W) • CSE = single-ended capacitance (F); see Figure 32 Table 15 shows an overview of the required SE capacitor values in the case of a 60 Hz, 40 Hz or 20 Hz 3 dB cut-off frequency. Table 15. SE capacitor values Impedance (Ω) CSE (µF) f−3dB = 60 Hz f−3dB = 40 Hz f−3dB = 20 Hz 4 680 1000 2200 6 470 680 1500 8 330 470 1000 14.5 Gain reduction The gain of the TDA8933B is internally fixed at 30 dB for SE and 36 dB for BTL. The gain can be reduced by a resistive voltage divider at the input (see Figure 9). R1 audio in 470 nF R3 R2 100 kΩ 470 nF 010aaa137 Fig 9. Input configuration for reducing gain When applying a resistive divider, the total voltage gain Gv(tot) can be calculated using Equation 8 and Equation 9: R EQ G v ( tot ) = G v ( cl ) + 20 log -----------------------------------------R EQ + ( R1 + R2 ) (8) Where: • Gv(tot) = total voltage gain (dB) • Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB) • REQ = equivalent resistance, R3 and Zi (Ω) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 25 of 42 TDA8933B NXP Semiconductors Class D audio amplifier • R1 = series resistors (Ω) • R2 = series resistors (Ω) R3 × Z R EQ = ------------------i R3 + Z i (9) Where: • REQ = equivalent resistance (Ω) • R3 = parallel resistor (Ω) • Zi = internal input impedance (Ω) Example: Substituting R1 = R2 = 4.7 kΩ, Zi = 100 kΩ and R3 = 22 kΩ in Equation 8 and Equation 9 results in a gain of Gv(tot) = 26.3 dB. 14.6 Device synchronization If two or more TDA8933B devices are used in one application it is recommended that all the devices are synchronized at the same switching frequency to avoid beat tones. This can be done by connecting all OSCIO pins together and configuring one of the devices as master while the others are configured as slaves (see Figure 10). A device is configured as master when a resistor Rosc is connected between pin OSCREF and pin VSSD(HW), thus setting the carrier frequency. Pin OSCIO of the master is then configured as an oscillator output for synchronization. The OSCREF pins of the slave devices should be shorted to pin VSSD(HW), configuring pin OSCIO as an input. master slave IC1 IC2 TDA8933B TDA8933B OSCREF VSSD(HW) OSCIO Cosc 100 nF OSCIO VSSD(HW) OSCREF Rosc 39 kΩ 010aaa138 Fig 10. Master/slave concept in a two-chip application TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 26 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 14.7 Thermal behavior (PCB considerations) The TDA8933B is available in a thermally enhanced HTSSOP32 (SOT549-1) package for reflow soldering. The HTSSOP32 package has an exposed die pad that reduces significantly the overall Rth(j-a). Therefore it is required to solder the exposed die pad (at VSSD level) to a copper plane for cooling. A low thermal-resistance can be achieved when using a multilayer PCB with sufficient space for two or three thermal planes. Increasing the area of the thermal plane, the number of planes or the copper thickness can reduce further the thermal resistance Rth(j-a) of both packages. Find below the typical thermal resistance (free air and natural convection) of two practical PCB implementations: • Rth(j-a) = 48 K/W for a small two-layer application board (55 mm × 40 mm, µm copper, FR4 base material). • Rth(j-a) = 30 K/W for a three-layer application board (70 mm × 50 mm, 35 µm copper, FR4 base material). Equation 10 shows the relation between the maximum allowable power dissipation P and the thermal resistance from junction to ambient. T j ( max ) – T amb R th ( j – a ) = ----------------------------------P (10) Where: • • • • Rth(j-a) = thermal resistance from junction to ambient (K/W) Tj(max) = maximum junction temperature (°C) Tamb = ambient temperature (°C) P = power dissipation, which is determined by the efficiency of the TDA8933B The power dissipation is shown in Figure 19 (SE) and Figure 27 (BTL). Thermal foldback will limit the maximum junction temperature to 140 °C. 14.8 Pumping effects When the amplifier is used in an SE configuration a so-called ‘pumping effect’ can occur. During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of that energy is delivered back to the other supply line (e.g. VSSP1) and vice versa. When the power supply cannot sink energy the voltage across output capacitors that power supply will increase. The voltage increase caused by the pumping effect depends on: • • • • • Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 27 of 42 TDA8933B NXP Semiconductors Class D audio amplifier The pumping effect should not cause a malfunction of either the audio amplifier or the power supply, which can also be caused by triggering of the undervoltage or overvoltage protection of the amplifier. Pumping effects in an SE configuration can be minimized by connecting audio inputs in anti-phase and changing the polarity of one speaker as shown in Figure 11. IN1P audio in1 OUT1 IN1N IN2N audio in2 OUT2 IN2P 010aaa140 Fig 11. SE application for reducing pumping effect 14.9 SE curves measured in the reference design 010aaa503 102 THD+N (%) THD+N (%) 10 10 1 1 (3) 10−1 10−1 (1) 010aaa504 102 (1) (3) (2) 10−2 10−3 10−2 10−2 (2) 10−1 1 a. VP = 25 V; RL = 2 × 8 Ω SE 10 102 Po (W/channel) 10−3 10−2 10−1 1 10 102 Po (W/channel) b. VP = 17 V; RL = 2 × 4 Ω SE (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz Fig 12. Total harmonic distortion-plus-noise as a function of output power TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 28 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 010aaa505 102 THD+N (%) THD+N (%) 10 10 1 1 10−1 010aaa506 102 10−1 (1) (1) (2) 10−2 10−2 (2) 10−3 10 102 103 104 fi (Hz) 105 a. VP = 25 V; RL = 2 × 8 Ω SE 10−3 10 102 103 104 fi (Hz) 105 b. VP = 17 V; RL = 2 × 4 Ω SE (1) Po = 7 W (2) Po = 1 W Fig 13. Total harmonic distortion-plus-noise as a function of frequency 010aaa507 40 010aaa508 0 SVRR (dB) Gv(cl) (dB) −20 30 (2) −40 (1) (2) 20 −60 (1) 10 10 102 103 104 fi (Hz) 105 Ri = 0 Ω; Vi = 100 mV (RMS); Cse = 1000 µF (1) RL = 2 × 4 Ω SE at VP = 17 V (2) RL = 2 × 8 Ω SE at VP = 25 V Fig 14. Gain as a function of frequency −80 10 103 104 fi (Hz) 105 Vripple = 500 mV (RMS) referenced to ground; Shorted input; CHVPREF = 47 µF (1) VP = 17 V; RL = 2 × 4 Ω SE (2) VP = 25 V; RL = 2 × 8 Ω SE Fig 15. Supply voltage ripple rejection as a function of frequency TDA8933B_1 Preliminary data sheet 102 © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 29 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 010aaa509 100 S/N (dB) 010aaa510 0 αcs (dB) (2) −20 80 (1) 60 −40 40 −60 20 −80 0 10−2 10−1 1 10 Po (W) 102 (1) (2) −100 10 Ri = 0 Ω; 20 kHz brick wall filter AES17 102 103 104 (1) RL = 2 × 4 Ω SE at VP = 17 V (1) RL = 2 × 4 Ω SE at VP = 17 V (2) RL = 2 × 8 Ω SE at VP = 25 V Fig 16. Signal-to-noise ratio as a function of output power 010aaa511 ηpo (%) Fig 17. Channel separation as a function of frequency 010aaa512 3.0 P (W) (1) 80 105 Po = 1 W (2) RL = 2 × 8 Ω SE at VP = 25 V 100 fi (Hz) (2) 2.0 60 (1) (2) 40 1.0 20 0 0 3 6 9 12 15 Po (W/channel) 2 × Po 2 × Po + P 0.0 10−2 10−1 1 10 102 Po (W/channel) fi = 1 kHz; Power dissipation in junction only fi = 1 kHz; η po = ------------------------- (1) RL = 2 × 4 Ω SE at 17 V (2) RL = 2 × 8 Ω SE at 25 V (1) RL = 2 × 4 Ω SE at 17 V (2) RL = 2 × 8 Ω SE at 25 V Fig 18. Output power efficiency as a function of output power Fig 19. Power dissipation as a function of output power per channel (two channels driven) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 30 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 010aaa513 30 010aaa514 4.0 P (W) Po (W/channel) (1) (2) 3.0 20 (1) (2) 2.0 (3) 10 (4) 1.0 0 0.0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) fi = 1 kHz; Short time Po fi = 1 kHz; Po at THD+N = 10 %; Power dissipation in junction only (1) RL = 2 × 8 Ω SE at THD = 10 % (1) RL = 2 × 4 Ω SE (2) RL = 2 × 8 Ω SE at THD = 0.5 % (2) RL = 2 × 8 Ω SE (3) RL = 2 × 4 Ω SE at THD = 10 % (4) RL = 2 × 4 Ω SE at THD = 0.5 % Fig 20. Maximum output power per channel as a function of supply voltage Fig 21. Power dissipation as a function of supply voltage 010aaa515 4 010aaa516 4 Vo (V) Vo (V) Operating 3 Operating 3 2 2 1 1 Sleep Mute 0 0 0 0.5 1 1.5 2 2.5 3 VPOWERUP (V) VENGAGE > 2 V; fi = 1 kHz; Vi = 100 mV (RMS) Fig 22. Output voltage as a function of voltage on pin POWERUP 0 1.0 1.5 2.0 2.5 3.0 VENGAGE (V) VPOWERUP = 2 V; fi = 1 kHz; Vi = 100 mV (RMS) Fig 23. Output voltage as a function of voltage on pin ENGAGE TDA8933B_1 Preliminary data sheet 0.5 © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 31 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 14.10 BTL curves measured in the reference design 010aaa517 102 THD+N (%) 10 10 1 1 10−1 010aaa518 102 THD+N (%) 10−1 (1) (1) (2) 10−2 10−2 (2) (3) (3) 10−3 10−2 10−1 1 10 Po (W) 102 a. VP = 17 V; RL = 8 Ω BTL 10−3 10−2 10−1 1 10 Po (W) 102 b. VP = 25 V; RL = 16 Ω BTL (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 1 kHz Fig 24. Total harmonic distortion-plus-noise as a function of output power 010aaa519 102 THD+N (%) 10 10 1 1 10−1 10−1 (1) (1) 10−2 010aaa520 102 THD+N (%) 10−2 (2) 10−3 10 102 (2) 103 a. VP = 17 V; RL = 8 Ω BTL 104 fi (Hz) 105 10−3 10 102 103 104 fi (Hz) 105 b. VP = 25 V; RL = 16 Ω BTL (1) Po = 12 W (1) Po = 10 W (2) Po = 1 W (2) Po = 1 W Fig 25. Total harmonic distortion-plus-noise as a function of frequency TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 32 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 010aaa521 100 010aaa522 45 (2) ηpo (%) (1) Gv(cl) (dB) 80 (1) 35 60 (2) 40 25 20 15 0 0 5 10 15 20 Po (W) 25 10 fi = 1 kHz 102 103 104 fi (Hz) 105 Vi = 100 mV (RMS) (1) 8 Ω BTL at 17 V (1) RL = 8 Ω BTL at VP = 17 V (2) 16 Ω BTL at 25 V (2) RL = 16 Ω BTL at VP = 25 V Fig 26. Output power efficiency as a function of output power Fig 27. Gain as a function of frequency 010aaa523 3 010aaa524 5 P (W) P (W) 4 2 3 (1) (1) (2) 2 (2) 1 1 0 10−2 10−1 1 10 102 Po (W) fi = 1 kHz; Power dissipation in junction only (1) 8 Ω BTL at 17 V 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) fi = 1 kHz; Po at THD+N = 10 %; Power dissipation in junction only (1) RL = 8 Ω BTL (2) 16 Ω BTL at 25 V (2) RL = 16 Ω BTL Fig 28. Power dissipation as a function of output power Fig 29. Power dissipation as a function of supply voltage TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 33 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 010aaa525 50 Po (W) (1) 010aaa526 0 SVRR (dB) −20 40 (2) −40 30 (3) −60 20 (4) (1) −80 10 (2) −100 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VP (V) fi = 1 kHz 10 102 103 104 fi (Hz) 105 Vripple = 500 mV (RMS) with relation to ground; Shorted inputs; CHVP = 100 nF (1) 16 Ω BTL at THD+N = 10 % (1) VP = 17 V; RL = 8 Ω BTL (2) 16 Ω BTL at THD+N = 0.5 % (2) VP = 25 V; RL = 16 Ω BTL (3) 8 Ω BTL at THD+N = 10 % (4) 8 Ω BTL at THD+N = 0.5 % Fig 30. Output power as a function of supply voltage Fig 31. Supply voltage ripple rejection as a function of frequency TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 34 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 14.11 Typical application schematics (simplified) VP Rvdda VP VPA 10 Ω Cvdda 100 nF Cvddp 220 µF (35 V) GND VSSD(HW) Cin IN1P 470 nF Cin IN1N 470 nF DIAG ENGAGE MUTE control Cen 470 nF POWERUP CGND SLEEP control Cosc VDDA VPA VSSA 100 nF Rosc OSCREF 39 kΩ HVPREF Chvpref 47 µF (25 V) INREF Cinref 100 nF Cin 470 nF TEST IN2N Cin 470 nF IN2P VSSD(HW) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 10 U1 TDA8932B 24 23 11 22 12 21 13 20 14 19 15 18 16 17 VSSD(HW) OSCIO HVP1 VP VDDP1 BOOT1 OUT1 Cvddp 100 nF Cbo 15 nF Llc VSSP1 STAB1 Rsn 10 Ω STAB2 Csn 470 pF VSSP2 Cstab 100 nF VDDP2 HVP2 Cse Optional Llc OUT2 BOOT2 Clc Cbo 15 nF Optional VP Cvddp 100 nF Rsn 10 Ω Csn 470 pF Clc Cse DREF VSSD(HW) Cdref 100 nF 010aaa527 Fig 32. Typical simplified application diagram for 2 × SE (asymmetrical supply) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 35 of 42 TDA8933B NXP Semiconductors Class D audio amplifier VP Rvdda VP 10 Ω VPA Cvdda 100 nF Cvddp 220 µF (35 V) GND VSSD(HW) Cin Cin IN1P 1 µF IN1N 1 µF DIAG MUTE control ENGAGE Cen 470 nF POWERUP CGND SLEEP control Cosc 100 nF Rosc VDDA VPA VSSA OSCREF 39 kΩ HVPREF INREF Chvp 100 nF Cinref 100 nF TEST IN2N IN2P VSSD(HW) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 9 10 Rhvp 470 Ω OSCIO VP VDDP1 BOOT1 OUT1 Cvddp 100 nF Cbo 15 nF VSSP1 Rsn 10 Ω 12 21 20 14 19 15 18 16 17 Cstab 100 nF VSSP2 Optional VDDP2 HVP2 Clc Llc OUT2 BOOT2 Clc Csn 470 pF 24 22 Chvp 100 nF Llc 25 U1 TDA8932B STAB2 23 Rhvp 470 Ω HVP1 STAB1 11 13 VSSD(HW) Cbo 15 nF Rsn 10 Ω Optional VP Cvddp 100 nF Csn 470 pF Cdref 100 nF Chvp 100 nF DREF VSSD(HW) 010aaa528 Fig 33. Typical simplified application diagram for 1 × BTL (asymmetrical supply) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 36 of 42 TDA8933B NXP Semiconductors Class D audio amplifier VDD Rvdda VDD VDDA 10 Ω Cvdda 100 nF Cvddp 220 µF (25 V) Cvssa 100 nF Cvssp 220 µF (25 V) GND Rvssa VSS VSSA 10 Ω VSS VSSD(HW) VSSA 1 Cin IN1P Cin 470 nF IN1N 470 nF DIAG ENGAGE MUTE control Cen 470 nF POWERUP CGND SLEEP control Cosc VSSA VDDA VSSA 100 nF Rosc VDDA VSSA OSCREF 39 kΩ HVPREF INREF Cinref 100 nF TEST Cin 470 nF VSSA IN2N Cin IN2P 470 nF VSSD(HW) VSSA 32 2 31 3 30 4 29 5 28 6 27 7 26 8 9 11 22 12 21 15 16 HVP1 VDD VDDP1 BOOT1 OUT1 20 19 18 17 Cvddp 100 nF Cbo 15 nF Llc VSSP1 Optional VSS STAB1 Cvssp 100 nF 24 23 14 VSSA OSCIO 25 U1 TDA8932B STAB2 10 13 VSSD(HW) VSSP2 Cstab 100 nF Csn 470 pF Cbo 15 nF VDDP2 Cvssp Llc Optional VDD Cvddp 100 nF HVP2 Clc VSS 100 nF OUT2 BOOT2 Rsn 10 Ω Rsn 10 Ω Csn 470 pF Clc DREF VSSD(HW) Cdref 100 nF VSSA 010aaa529 Fig 34. Typical simplified application diagram for 2 × SE (symmetrical supply) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 37 of 42 TDA8933B NXP Semiconductors Class D audio amplifier VDD Rvdda VDD 10 Ω VDDA Cvdda 100 nF Cvddp 220 µF (25 V) Cvssa 100 nF Cvssp 220 µF (25 V) GND Rvssa VSS VSSA 10 Ω VSS VSSA Cin Cin VSSD(HW) IN1P 1 µF IN1N 1 µF DIAG MUTE control SLEEP control ENGAGE Cen 470 nF POWERUP CGND Cosc VDDA 100 nF Rosc VSSA VDDA VSSA OSCREF VSSA 39 kΩ HVPREF INREF Cinref 100 nF TEST VSSA IN2N IN2P VSSA VSSD(HW) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 9 10 VSSD(HW) VSSA OSCIO HVP1 VDD VDDP1 BOOT1 OUT1 VSSP1 Optional VSS STAB1 Cvssp 100 nF 25 U1 TDA8932B STAB2 24 23 11 22 12 21 13 20 14 19 15 18 16 17 Cvddp 100 nF Llc Cbo 15 nF VSSP2 Cstab 100 nF Cvssp 100 nF Cbo 15 nF VDDP2 VDD HVP2 Clc Csn 470 pF VSS OUT2 BOOT2 Rsn 10 Ω Cvddp 100 nF Clc Llc Rsn 10 Ω Optional Csn 470 pF DREF VSSD(HW) Cdref 100 nF VSSA 010aaa530 Fig 35. Typical simplified application diagram for 1 × BTL (symmetrical supply) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 38 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 15. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-1 E D A X c y HE exposed die pad side v M A Dh Z 32 17 A2 Eh (A3) A A1 pin 1 index θ Lp L detail X 16 1 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D(1) Dh E(2) Eh e HE L Lp v w y Z θ mm 1.1 0.15 0.05 0.95 0.85 0.25 0.30 0.19 0.20 0.09 11.1 10.9 5.1 4.9 6.2 6.0 3.6 3.4 0.65 8.3 7.9 1 0.75 0.50 0.2 0.1 0.1 0.78 0.48 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-11-02 MO-153 Fig 36. Package outline SOT549-1 (HTSSOP32) TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 39 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 16. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8933B_1 20081023 Preliminary data sheet - - TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 40 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA8933B_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 23 October 2008 41 of 42 TDA8933B NXP Semiconductors Class D audio amplifier 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 15 16 17 17.1 17.2 17.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mode selection and interfacing . . . . . . . . . . . . . 6 Pulse Width Modulation (PWM) frequency . . . . 7 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Foldback (FT) . . . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . . . . . . . . . 9 OverCurrent Protection (OCP) . . . . . . . . . . . . . 9 Window Protection (WP). . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . . 9 Diagnostic input and output . . . . . . . . . . . . . . 11 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 11 Output voltage buffers. . . . . . . . . . . . . . . . . . . 12 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal characteristics. . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Application information. . . . . . . . . . . . . . . . . . 21 Output power estimation. . . . . . . . . . . . . . . . . 21 Output current limitation . . . . . . . . . . . . . . . . . 24 Speaker configuration and impedance . . . . . . 24 Single-ended capacitor . . . . . . . . . . . . . . . . . . 25 Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 25 Device synchronization . . . . . . . . . . . . . . . . . . 26 Thermal behavior (PCB considerations). . . . . 27 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 27 SE curves measured in the reference design. 28 BTL curves measured in the reference design 32 Typical application schematics (simplified) . . . 35 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 40 Legal information. . . . . . . . . . . . . . . . . . . . . . . 41 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17.4 18 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Contact information . . . . . . . . . . . . . . . . . . . . 41 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 23 October 2008 Document identifier: TDA8933B_1