RoboClock® CY7B9950:2.5 / 3.3 V, 200 MHz High Speed Multi-Phase PLL Clock Buffer


CY7B9950 RoboClock®
2.5/3.3 V, 200 MHz High-Speed
Multi-Phase PLL Clock Buffer
2.5/3.3 V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer
Features
Functional Description
The CY7B9950 RoboClock® is a low voltage, low power,
eight-output, 200 MHz clock driver. It features output phase
programmability which is necessary to optimize the clock tree
design of high performance computer and communication
systems.
■
2.5 V or 3.3 V operation
■
Split output bank power supplies
■
Output frequency range: 6 MHz to 200 MHz
■
50 ps typical matched-pair output-output skew
■
50 ps typical cycle-cycle jitter
■
49.5 / 50.5% typical output duty cycle
■
Selectable output drive strength
■
Selectable positive or negative edge synchronization
■
Eight LVTTL outputs driving 50terminated lines
■
LVCMOS / LVTTL overvoltage tolerant reference input
■
Phase adjustments in 625 / 1250 ps steps up to +7.5 ns
■
2×, 4× multiply and (1/2)×, (1/4)× divide ratios
■
Spread spectrum compatible
■
Industrial temperature range: –40C to +85 C
The device also features split output bank power supplies, which
enable the user to run two banks (1Qn and 2Qn) at a power
supply level different from that of the other two banks (3Qn and
4Qn). Additionally, the three-level PE/HD pin controls the
synchronization of the output signals to either the rising or falling
edge of the reference clock and selects the drive strength of the
output buffers. The high drive option (PE/HD = MID) increases
the output current from ± 12 mA to ± 24 mA(3.3 V).
■
32-pin TQFP package
For a complete list of related documentation, click here.
Logic Block Diagram
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature enables the user to
skew the outputs to lead or lag the reference clock. Any one of
the outputs can be connected to the feedback input to achieve
different reference frequency multiplications, divide ratios, and
zero input-output delay.
TEST PE/HD FS
3
3
REF
VDDQ1
3
PLL
FB
3
1F1:0
3
3
2F1:0
3
3
3F1:0
3
1Q0
Phase
Select
1Q1
2Q0
Phase
Select
2Q1
3Q0
Phase
Select
and /K
3Q1
VDDQ3
3
4F1:0
3
4Q0
Phase
Select
and /M
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation
Document Number: 38-07338 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 3, 2016
CY7B9950 RoboClock®
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
Device Configuration ....................................................... 5
Governing Agencies ......................................................... 5
Absolute Maximum Conditions ....................................... 6
Operating Conditions ....................................................... 6
DC Electrical Specifications at 2.5 V .............................. 7
DC Electrical Specifications at 3.3 V .............................. 8
Thermal Resistance .......................................................... 9
AC Test Loads and Waveforms ....................................... 9
AC Input Specifications ................................................. 10
Switching Characteristics .............................................. 11
AC Timing Definitions .................................................... 12
Document Number: 38-07338 Rev. *J
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC®Solutions ....................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY7B9950 RoboClock®
Pinouts
3F1
Document Number: 38-07338 Rev. *J
REF
VSS
TEST
2F1
2F0
27
26
25
VDD
30
28
FS
31
29
3F0
32
Figure 1. 32-pin TQFP pinout (Top View)
1
2
3
24
1F1
4F0
4F1
23
22
1F0
PE/HD
VDDQ4
4
5
21
20
VDDQ1
1Q0
4Q1
4Q0
VSS
6
7
19
18
1Q1
8
17
9
10
11
12
13
14
15
16
VSS
3Q1
3Q0
VDDQ3
FB
VDD
2Q1
2Q0
CY7B9950
sOE#
VSS
VSS
Page 3 of 17
CY7B9950 RoboClock®
Pin Definitions
Pin
Name
I/O [1]
Type
29
REF
I
LVTTL /
LVCMOS
Description
Reference clock input.
13
FB
I
LVTTL
27
TEST
I
Three-level
When MID or HIGH, disables PLL[2]. REF goes to outputs of Bank 1 and
Bank 2. REF also goes to outputs of Bank 3 and Bank 4 through output dividers
K and M. Set LOW for normal operation.
Feedback input.
22
sOE#
I, PD
Two-level
Synchronous output enable. When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a Low state (for PE = H or M) – 2Q0, and 2Q1 may be used as the
feedback signal to maintain phase lock. When test is held at MID level and
sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# Low for normal operation.
4
PE/HD
I, PU
Three-level
Selects Positive or negative edge control and High or low output drive strength.
When Low/High the outputs are synchronized with the negative/positive edge
of the reference clock, respectively. When at MID level, the output drive
strength is increased and the outputs synchronize with the positive edge of the
reference clock (see Table 6 on page 5).
24, 23, 26,
25, 1, 32, 3,
2
nF[1:0]
I
Three-level
Select frequency and phase of the outputs (see Table 1, Table 2, Table 3 on
page 5, Table 4 on page 5, and Table 5 on page 5).
31
FS
I
Three-level
Selects VCO operating frequency range (see Table 4 on page 5)
19, 20, 15,
16, 10, 11,
6, 7
nQ[1:0]
O
LVTTL
Four banks of two outputs (see Table 1, Table 2, and Table 3 on page 5)
21
VDDQ1[3]
PWR
Power
Power supply for Bank 1 and Bank 2 output buffers (see Table 7 on page 5 for
supply level constraints).
12
VDDQ3[3]
PWR
Power
Power supply for Bank 3 output buffers (see Table 7 on page 5 for supply level
constraints).
5
VDDQ4[3]
PWR
Power
Power supply for Bank 4 output buffers (see Table 7 on page 5 for supply level
constraints).
14, 30
VDD[3]
PWR
Power
Power supply for internal circuitry (see Table 7 on page 5 for supply level
constraints).
8, 9, 17, 18,
28
VSS
PWR
Power
Ground
Notes
1. PD indicates an internal pull-down and PU indicates an internal pull-up. 3 indicates a three-level input buffer.
2. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
3. A bypass capacitor (0.1F) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic are cancelled by the lead inductance of the traces.
Document Number: 38-07338 Rev. *J
Page 4 of 17
CY7B9950 RoboClock®
Device Configuration
Table 5. Output Skew Settings(continued)
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1 and Table 2, respectively.
Table 1. Output Divider Settings — Bank 3
3F[1:0]
K — Bank3 output divider
LL
2
HH
4
Other [4]
1
Table 2. Output Divider Settings — Bank 4
4F[1:0]
M — Bank4 output divider
LL
2
Other
[4]
1
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that
corresponds to each FS level is given in Table 3 on page 5.
Table 3. Frequency Range Select
FS
Skew
nF[1:0] (1Q[0:1],2Q[0:1])
Skew (3Q[0:1]) Skew (4Q[0:1])
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
Zero skew
Zero skew
Zero skew
MH
+1tU
+2tU
+2tU
HL
+2tU
+4tU
+4tU
HM
+3tU
+6tU
+6tU
HH
+4tU
Divide by 4
Inverted[6]
In addition to determining whether the outputs synchronize to the
rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as indicated
in Table 6.
The CY7B9950 RoboClock® features split power supply buses
for Banks 1 and 2, Bank 3 and Bank 4, which enables the user
to obtain both 3.3 V and 2.5 V output signals from one device.
The core power supply (VDD) must be set at a level that is equal
to or higher than any one of the output power supplies.
Table 6. PE/HD Settings
PE/HD
Synchronization
Output drive strength[7]
L
Negative
Low drive
PLL frequency range
M
Positive
High drive
H
Positive
Low drive
L
24 to 50 MHz
M
48 to 100 MHz
H
96 to 200 MHz
Table 7. Power Supply Constraints
The selectable output skew is in discrete increments of time units
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
the tU value is: tU = 1 / (fNOM × MF), where MF is a multiplication
factor, which is determined by the FS setting as indicated in
Table 4.
VDDQ1[8]
VDD
3.3 V 3.3 V or 2.5 V
2.5 V
VDDQ3[8]
VDDQ4[8]
3.3 V or 2.5 V
3.3 V or 2.5 V
2.5 V
2.5 V
2.5 V
Governing Agencies
Table 4. MF Calculation
FS
MF
fNOM at which tU is 1.0 ns (MHz)
L
32
31.25
M
16
62.5
H
8
125
The following agencies provide specifications that apply to the
CY7B9950 RoboClock®. The agency name and relevant
specification is listed below.
Table 8. Governing Agencies and Specifications
Table 5. Output Skew Settings
Agency name
Specification
JEDEC
JESD 51 (theta JA), JESD 65 (skew, jitter)
IEEE
Skew
nF[1:0] (1Q[0:1],2Q[0:1])
Skew (3Q[0:1]) Skew (4Q[0:1])
LL[5]
–4tU
Divide by 2
Divide by 2
LM
–3tU
–6tU
–6tU
UL-194_V0
MIL
1596.3 (jitter specs)
94 (moisture grading)
883E method 1012.1 (therma theta JC)
Notes
4. These states are used to program the phase of the respective banks (see Table 5 on page 5).
5. LL disables outputs if TEST = MID and sOE# = HIGH.
6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID and sOE# disables them LOW when PE/HD = LOW.
7. Please refer to “DC Parameters” section for IOH/IOL specifications.
8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3 V, VDDQ1 = 3.3 V, VDDQ3 = 2.5 V and
VDDQ4 = 2.5 V.
Document Number: 38-07338 Rev. *J
Page 5 of 17
CY7B9950 RoboClock®
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–
4.6
V
VDD
Supply voltage
VIN(MIN)
Input voltage
Relative to VSS
VSS – 0.3
–
V
VIN(MAX)
Input voltage
Relative to VDD
–
VDD + 0.3
V
TS
Temperature, storage
Non-functional
–65
150
°C
TJ
Temperature, junction
Functional
–
155
°C
ØJC
Dissipation, junction to case
Mil-Spec 883E Method 1012.1
–
42
°C/W
ØJA
Dissipation, junction to ambient
JEDEC (JESD 51)
–
105
°C/W
ESDHBM
ESD protection (human body
model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability rating
At 1/8 in.
MSL
Moisture sensitivity level
FIT
Failure in time
V–0
3
Manufacturing testing
10
ppm
Operating Conditions
Parameter
VDD
TA
Description
Operating voltage
Temperature, operating ambient
Document Number: 38-07338 Rev. *J
Condition
Min
Max
Unit
2.5 V ± 5%
2.375
2.625
V
3.3 V ± 10%
2.97
3.63
V
–40
85
°C
Page 6 of 17
CY7B9950 RoboClock®
DC Electrical Specifications at 2.5 V
Parameter
Description
VIL
Input low voltage
VIH
Input high voltage
VIHH[9]
Input high voltage
VIMM[9]
Input MID voltage
VILL
[9]
Input low voltage
Condition
REF, FB and sOE# Inputs
3-level inputs 
(TEST, FS, nF[1:0], PE/HD) (These pins are
normally wired to VDD, GND, or unconnected.)
Min
Max
Unit
–
0.7
V
1.7
–
V
VDD – 0.4
–
V
VDD/2 – 0.2 VDD/2 + 0.2
V
–
0.4
V
IIL
Input leakage current
VIN = VDD/GND, 
VDD = max. (REF and FB inputs)
–5
5
A
I3
3-level input DC current
HIGH, VIN = VDD
–
200
A
MID, VIN = VDD/2
LOW, VIN = VSS
3-level inputs
(TEST, FS, nF[1:0],
PE/HD)
–50
50
A
–200
–
A
–25
–
A
IPU
Input pull-up current
VIN = VSS, VDD = max.
IPD
Input pull-down current
VIN = VDD, VDD = max., (sOE#)
–
100
A
VOL
Output low voltage
VOH
Output high voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
IOL = 20 mA (PE/HD = MID), (nQ[0:1])
–
0.4
V
IOH = –12 mA (PE/HD = L/H), (nQ[0:1])
2.0
–
V
IOH = –20 mA (PE/HD = MID), (nQ[0:1])
2.0
–
V
–
2
mA
IDDQ
Quiescent supply current
VDD = max., TEST = MID, REF = LOW, 
sOE# = LOW, outputs not loaded
IDD
Dynamic supply current
At 100 MHz
CIN
Input pin capacitance
150
mA
4
pF
Note
9. These inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
Document Number: 38-07338 Rev. *J
Page 7 of 17
CY7B9950 RoboClock®
DC Electrical Specifications at 3.3 V
Parameter
Description
VIL
Input LOW voltage
VIH
Input HIGH voltage
VIHH[10]
Input HIGH voltage
VIMM[10]
Input MID voltage
VILL
[10]
Input LOW voltage
Condition
REF, FB and sOE# Inputs
3-level inputs 
(TEST, FS, nF[1:0], PE/HD) (These pins are
normally wired to VDD, GND or unconected.)
Min
Max
Unit
–
0.8
V
2.0
–
V
VDD – 0.6
–
V
VDD/2 – 0.3 VDD/2 + 0.3
–
V
0.6
V
IIL
Input leakage current
VIN = VDD/GND, VDD = max. (REF and FB inputs)
–5
5
A
I3
3-level input DC current
HIGH, VIN = VDD
3-level inputs 
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV, PE/HD)
–
200
A
–50
50
A
–200
–
A
MID, VIN = VDD/2
LOW, VIN = VSS
IPU
Input pull-up current
VIN = VSS, VDD = max.
–100
–
A
IPD
Input pull-down current
VIN = VDD, VDD = max., (sOE#)
–
100
A
VOL
Output LOW voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
0.4
V
IOL = 24 mA (PE/HD = MID), (nQ[0:1])
–
0.4
V
VOH
Output HIGH voltage
IOH = –12 mA (PE/HD = L/H), (nQ[0:1])
2.4
–
V
IOH = –24 mA (PE/HD = MID), (nQ[0:1])
2.4
–
V
–
2
mA
IDDQ
Quiescent supply current
VDD = max., TEST = MID, REF = LOW, 
sOE# = LOW, outputs not loaded
IDD
Dynamic supply current
At 100 MHz
CIN
Input pin capacitance
230
mA
4
pF
Note
10. These inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
Document Number: 38-07338 Rev. *J
Page 8 of 17
CY7B9950 RoboClock®
Thermal Resistance
Parameter [11]
Description
θJA
Thermal resistance 
(junction to ambient)
θJC
Thermal resistance 
(junction to case)
Test Conditions
32-pin TQFP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
65
°C/W
12
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads
VDDQ
Output
150
20 pF
Output
150
For Lock Output
20 pF
For All Other Outputs
Figure 3. Output Waveforms
tORISE
tORISE
tOFALL
tPWH
2.0V
tOFALL
tPWH
1.7V
VTH =1.25V
VTH =1.5V
tPWL
0.8V
tPWL
0.7V
2.5V LVTTL OUTPUT WAVEFORM
3.3V LVTTL OUTPUT WAVEFORM
Figure 4. Test Waveforms
 1 ns
1 ns
1 ns
3.0V
 1 ns
2.5V
1.7V
2.0V
VTH =1.5V
0.8V
0V
3.3V LVTTL INPUT TEST WAVEFORM
VTH =1.25V
0.7V
0V
2.5V LVTTL INPUT TEST WAVEFORM
Note
11. These parameters are guaranteed by design and are not tested.
Document Number: 38-07338 Rev. *J
Page 9 of 17
CY7B9950 RoboClock®
AC Input Specifications
Parameter
Description
Condition
Min
Max
Unit
TR,TF
Input rise/fall time
0.8 V–2.0 V
–
10
ns/V
TPWC
Input clock pulse
HIGH or LOW
2
–
ns
TDCIN
Input duty cycle
%
FREF
Reference input frequency
Document Number: 38-07338 Rev. *J
10
90
FS = LOW
6
50
FS = MID
12
100
FS = HIGH
24
200
MHz
Page 10 of 17
CY7B9950 RoboClock®
Switching Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
6
–
200
MHz
200
–
400
MHz
FOR
Output frequency range
VCOLR
VCO lock range
VCOLBW
VCO loop bandwidth
0.25
–
3.5
MHz
tSKEWPR
Matched-pair skew[10]
Skew between the earliest and the
latest output transitions within the
same bank.
–
50
100
ps
tSKEW0
Output-output skew[10]
Skew between the earliest and the
latest output transitions among all
outputs at 0tU.
–
100
200
ps
tSKEW1
Skew between the earliest and the
latest output transitions among all
outputs for which the same phase
delay has been selected.
–
100
200
ps
tSKEW2
Skew between the nominal output
rising edge to the inverted output
falling edge.
–
–
500
ps
Skew between non-inverted outputs
running at different frequencies.
–
–
500
ps
tSKEW4
Skew between nominal to inverted
outputs running at different
frequencies.
–
–
500
ps
tSKEW5
Skew between nominal outputs at
different power supply levels.
–
–
650
ps
Skew between the outputs of any
two devices under identical settings
and conditions (VDDQ,VDD,temp, air
flow, frequency, etc.).
–
–
750
ps
–250
–
+250
ps
Fout < 100 MHz, measured at VDD/2
48
49.5/50.5
52
%
Fout > 100 MHz, measured at VDD/2
45
48/52
55
tSKEW3
Output-output skew[10]
tPART
Part-part skew
tPD0
Ref-FB propagation delay[11]
tODCV
Output duty cycle
tPWH
Output high time deviation from
50%
Measured at 2.0V for VDD = 3.3 V
and at 1.7 V for VDD = 2.5V.
–
–
1.5
ns
tPWL
Output low time deviation from
50%
Measured at 0.8 V for VDD = 3.3 V
and at 0.7 V for VDD = 2.5 V.
–
–
2.0
ns
tR/tF
Output rise/fall time
Measured at 
0.8 V–2.0 V for VDD = 3.3 V and 
0.7 V–1.7 V for VDD = 2.5 V.
0.15
–
1.5
ns
tLOCK
PLL lock time [12,13]
–
–
0.5
ms
tCCJ
Cycle-cycle jitter
Divide by one output frequency, 
FS = L, FB = divide by 1, 2, 4.
–
50
100
ps
Divide by one output frequency, 
FS = M/H, FB = divide by 1, 2, 4.
–
70
150
ps
Notes
10. Test load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
11. tPD is measured at 1.5 V for VDD = 3.3 V and at 1.25 V for VDD = 2.5 V with REF rise/fall times of 0.5 ns between 0.8 V–2.0 V.
12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
13. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Document Number: 38-07338 Rev. *J
Page 11 of 17
CY7B9950 RoboClock®
AC Timing Definitions
Figure 5. Timing Definitions
tREF
tPWL
tPWH
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR
tSKEW0,1
tSKEWPR
tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
REF DIVIDED BY 2
tSKEW1,3,4
tSKEW1,3,4
REF DIVIDED BY 4
Document Number: 38-07338 Rev. *J
Page 12 of 17
CY7B9950 RoboClock®
Ordering Information
Part Number
Package Type
Product Flow
Pb-free
CY7B9950 RoboClock®AXC
32-pin TQFP
Commercial, 0 to 70 C
CY7B9950
RoboClock®AXCT
32-pin TQFP – Tape and Reel
Commercial, 0 to 70 C
CY7B9950
RoboClock®AXI
32-pin TQFP
Industrial, –40 C to 85 C
32-pin TQFP – Tape and Reel
Industrial, –40C to 85 C
CY7B9950 RoboClock®AXIT
Ordering Code Definitions
CY 7B 9950 A
X X X
X = blank or T 
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I 
C = Commercial; I = Industrial
X = Pb-free; blank = leaded
Package Type: A = 32-pin TQFP
Part Identifier
Family
Company ID: CY = Cypress
Document Number: 38-07338 Rev. *J
Page 13 of 17
CY7B9950 RoboClock®
Package Diagram
Figure 6. 32-pin TQFP (7 × 7 × 1.0 mm) A3210 Package Outline, 51-85063
51-85063 *E
Document Number: 38-07338 Rev. *J
Page 14 of 17
CY7B9950 RoboClock®
Acronyms
Table 9. Acronyms Used in this Document
Acronym
Description
CLKOUT
Clock Output
CMOS
Complementary Metal Oxide Semiconductor
DPM
Die Pick Map
EPROM
Erasable Programmable Read Only Memory
NTSC
National Television System Committee
OE
Output Enable
PAL
Phase Alternate Line
PD
Power Down
PLL
Phase Locked Loop
PPM
Parts Per Million
TTL
Transistor-Transistor Logic
Document Conventions
Units of Measure
Table 10. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
°C
degree Celsius
µW
microwatt
dB
decibel
mA
milliampere
fC
femtoCoulomb
mm
millimeter
fF
femtofarad
ms
millisecond
Hz
hertz
mV
millivolt
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolt
k
kilohm

ohm
MHz
megahertz
pA
picoampere
M
megaohm
pF
picofarad
µA
microampere
pp
peak-to-peak
µF
microfarad
ppm
parts per million
µH
microhenry
ps
picosecond
µs
microsecond
sps
samples per second
µV
microvolt

sigma: one standard deviation
µVrms
microvolts root-mean-square
Document Number: 38-07338 Rev. *J
Page 15 of 17
CY7B9950 RoboClock®
Document History Page
Document Title: CY7B9950 RoboClock®, 2.5/3.3 V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer
Document Number: 38-07338
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
121663
11/25/02
RGL
New Data Sheet
*A
122548
12/12/02
RGL
Removed the PD#/DIV and DS[1:0] pins in VIHH,VIMM and VILL for both 2.5V
and 3.3V DC Electrical Specs tables
*B
124646
03/05/03
RGL
Corrected the description of Pin 27(TEST) in the Pin Description table
Corrected the description of Pin 12 (VDDQ) in the Pin Description table
Corrected the Min and Max values of VDD from 2.25/2.75 to 2.375/2.625 Volts
in the Absolute Maximum Conditions table
*C
433662
See ECN
RGL
Added Jitter typical values.
Updated Ordering Information:
Added Lead-free devices.
*D
1562063
See ECN
PYG /
AESA
Updated Ordering Information:
Added a MPN CY7B9940V-5AXC.
Added Status column to Ordering Information table.
*E
2894960
03/17/10
KVM
Updated Device Configuration:
Updated Table 5:
Fixed typo in output skew settings.
Updated Absolute Maximum Conditions:
Updated VDD value.
Added Operating Conditions.
Updated Ordering Information.
Updated Package Diagram.
Updated Sales, Solutions, and Legal Information:
Updated links.
*F
3058099
10/14/10
BASH
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
*G
4176123
10/28/2013
CINM
Updated Package Diagram:
spec 51-85063 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*H
4571728
11/17/2014
CINM
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*I
4764256
05/13/2015
XHT
Updated Absolute Maximum Conditions:
Changed value of MSL parameter from 1 to 3.
Updated Package Diagram:
spec 51-85063 – Changed revision from *D to *E.
*J
5257087
05/03/2016
PSR
Added Thermal Resistance.
Updated to new template.
Document Number: 38-07338 Rev. *J
Description of Change
Page 16 of 17
CY7B9950 RoboClock®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
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Document Number: 38-07338 Rev. *J
RoboClock is a registered trademark of Cypress Semiconductor Corporation.
Revised May 3, 2016
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