CY25562
Spread Spectrum Clock Generator
Spread Spectrum Clock Generator
Features
■
50 to 200 MHz operating frequency range
■
Wide range of spread selections: 9
■
Accepts clock and crystal inputs
■
Low power dissipation
❐ 70 mW Typ (Fin = 65 MHz)
■
Frequency spread disable function
■
Center spread modulation
■
Low cycle-to-cycle jitter
■
8-pin SOIC package
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading system performance.
CY25562 is a simple and versatile device. The frequency and
spread percentage range is selected by programming S0 and S1
digital inputs. These inputs use three logic states including high
(H), low (L), and middle (M) logic levels to select one of the nine
available spread percentage ranges. Refer to Figure 2 on page
4 for programming details.
CY25562 is intended for applications with a reference frequency
in the range of 50 to 200 MHz.
A wide range of digitally selectable spread percentages is made
possible by using the tri-level (high, low, and middle) logic at the
S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Functional Description
Spread spectrum clock control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
CY25562 is a spread spectrum clock generator (SSCG) IC used
to reduce electromagnetic interference (EMI) found in today’s
high speed digital electronic systems.
CY25562 is available in an eight-pin SOIC package with a 0 to
70 °C operating temperature range.
CY25562 uses a Cypress proprietary phase locked loop (PLL)
and spread spectrum clock (SSC) technology to synthesize and
frequency modulate the input frequency of the reference clock.
By doing this, the measured EMI at the fundamental and
harmonic frequencies of clock (SSCLK) is reduced.
Refer to CY25561 for applications with lower drive requirements
and CY25560 with lower drive and frequency requirements.
For a complete list of related documentation, click here.
Logic Block Diagram
300K
Xin/
CLK
1
Xout
8
VDD
VSS
REFERENCE
DIVIDER
MODULATION
CONTROL
2
VDD
DIVIDER
&
MUX
4 SSCLK
20 K
20 K
20 K
VSS
•
vco
VDD
20 K
5
SSCC
Loop
Filter
CP
FEEDBACK
DIVIDER
INPUT
DECODER
LOGIC
3
Cypress Semiconductor Corporation
Document Number: 38-07392 Rev. *H
PD
VSS
6
S1
7
S0
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 20, 2016
CY25562
Contents
Pinout ................................................................................ 3
Pin Description ................................................................. 3
Functional Overview ........................................................ 4
Frequency and Spread Percentage Selection ............. 4
Tri-level Logic .............................................................. 4
SSCG Theory of Operation ......................................... 4
CY25562 Application Schematic ..................................... 6
Absolute Maximum Ratings ............................................ 7
Electrical Characteristics ................................................. 7
Thermal Resistance .......................................................... 7
Electrical Timing Characteristics .................................... 8
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Document Number: 38-07392 Rev. *H
Package Drawing and Dimensions ............................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC®Solutions ....................................................... 13
Cypress Developer Community ................................. 13
Technical Support ..................................................... 13
Page 2 of 13
CY25562
Pinout
Figure 1. 8-pin SOIC pinout
XIN/CLK 1
8 XOUT
VDD 2
7 S0
CY25562
VSS 3
SSCLK 4
6 S1
5 SSCC
Pin Description
Pin #
Pin Name
Type
1
Xin/CLK
I
Pin Description
Clock or crystal connection input. Refer to Figure 2 on page 4 for input frequency range
selection.
2
VDD
P
Positive power supply
3
GND
P
Power supply ground
4
SSCLK
O
SSCG modulated clock output
5
SSCC
I
Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input
is high and disabled when input is low. This pin is pulled high internally.
6
S1
I
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth
selection and tri-level logic programming. See Figure 3 on page 4. Pin 6 has internal resistor
divider network to VDD and VSS. Refer to Logic Block Diagram on page 1.
7
S0
I
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth
selection and tri-level logic programming. See Figure 3 on page 4. Pin 7 has internal resistor
divider network to VDD and VSS. Refer to Logic Block Diagram on page 1.
8
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock
drives Xin/CLK.
Document Number: 38-07392 Rev. *H
Page 3 of 13
CY25562
Functional Overview
Frequency and Spread Percentage Selection
Figure 2. Frequency and Spread Percentage Selection (Center Spread)
5 0 – 1 0 0 M H z (L o w R a n g e )
In p u t
F re q u e n c y
(M H z )
50 - 60
60 - 70
70 - 80
80 - 100
S1=M
S0=M
(% )
4 .3
4 .0
3 .8
3 .5
S1=M
S0=0
(% )
3 .9
3 .6
3 .4
3 .1
S1=1
S0=0
(% )
3 .3
3 .1
2 .9
2 .7
S1=0
S0=0
(% )
2 .9
2 .6
2 .5
2 .2
S1=0
S0=M
(% )
2 .7
2 .5
2 .4
2 .1
S e le c t th e
F req u e n c y a n d
C e n te r S p re a d %
d e s ire d a n d th e n
set S1, S0 as
in d ic a te d .
1 0 0 – 2 0 0 M H z (H ig h R a n g e )
In p u t
F re q u e n c y
(M H z )
100 – 120
1 2 0 -1 3 0
130 - 140
140 - 150
150 - 160
160 - 170
170 - 180
180 - 190
190 - 200
S1=1
S0=M
(% )
3 .0
2 .7
2 .6
2 .6
2 .5
2 .4
2 .4
2 .3
2 .3
S1=0
S0=1
(% )
2 .4
2 .1
2 .0
2 .0
1 .8
1 .8
1 .8
1 .7
1 .6
S1=1
S0=1
(% )
1 .6
1 .4
1 .3
1 .3
1 .2
1 .2
1 .2
1 .1
1 .1
S1=M
S0=1
(% )
1 .3
1 .1
1 .1
1 .1
1 .0
1 .0
1 .0
0 .9
0 .9
S e le c t th e
F req u e n c y a n d
C e n te r S p re a d %
d e s ire d a n d th e n
set S1, S0 as
in d ic a te d .
Tri-level Logic
With binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using
two control lines. Tri-level logic in CY25562 is implemented by defining a third logic state in addition to the standard logic “1” and “0.”
Pins six and seven of CY25562 recognize a logic state by the voltage applied to the respective pin. These states are defined as “0”
(low), “M” (middle), and “1” (one). Each of these states have a defined voltage range that is interpreted by CY25562 as “0”, “M,” or “1”
logic state. Refer to Electrical Characteristics on page 7 for voltage ranges for each logic state. CY25562 has two equal value resistors
connected internally to pin 6 and pin 7, which produce the default “M” state. Pins 6 or 7 can be tied directly to ground or VDD to
program a logic “0” or “1” state, respectively. See the following examples:
Figure 3. Tri-level Logic Example
VDD
CY25562
CY25562
S0 = "M" (N/C)
7
S1 = "0" (GND)
6
SSCC = "1"
5
S0
S0 = "1"
7
S1
S0 = "1"
7
S1 = "1"
6
SSCC = "1"
5
S1
S1 = "0" (GND)
6
SSCC = "1"
5
VDD
S0
S1
VDD
SSCG Theory of Operation
CY25562 is a PLL-type clock generator using a proprietary
Cypress design to modulate the reference clock. By precisely
controlling the bandwidth of the output clock, CY25562 becomes
a low-EMI clock generator. The theory and detailed operation of
CY25562 is discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50 percent. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the odd
harmonics, that is; third, fifth, seventh, etc. The amount of energy
Document Number: 38-07392 Rev. *H
S0
VDD
CY25562
contained in the fundamental and odd harmonics can be reduced
by increasing the bandwidth of the fundamental clock frequency.
Conventional digital clocks have a very high Q factor; all the
energy at that frequency is concentrated in a very narrow
bandwidth, and consequently, higher energy peaks. Regulatory
agencies test electronic equipment by the amount of peak
energy radiated from the equipment. By reducing the peak
energy at the fundamental and harmonic frequencies, the
equipment under test satisfies agency requirements for EMI.
Conventional methods of reducing EMI use shielding, filtering,
multi-layer PCBs, etc. CY25562 reduces the peak energy in the
clock by increasing the clock bandwidth, thus lowering the Q.
Page 4 of 13
CY25562
SSCG
SSCG uses a patented technology of modulating the clock over
a very narrow bandwidth and controlled rate of change, both
peak and cycle-to-cycle. CY25562 takes a narrow band digital
reference clock in the range of 50 to 200 MHz and produces a
clock that sweeps between a controlled start (F1) and stop (F2)
frequency at a precise rate of change. To understand what
happens to a clock when SSCG is applied, consider a 200 MHz
clock with a 50 percent duty cycle, as shown in this figure.
important factor in the amount of EMI reduction realized from an
SSCG clock.
The modulation domain analyzer is used to visualize the sweep
waveform and sweep period. Figure 4 shows the modulation
profile of a 200 MHz SSCG clock. Notice that the actual sweep
waveform is not a simple sine or sawtooth waveform. Figure 4
also shows a scan of the same SSCG clock using a spectrum
analyzer. The spectrum analyzer scan shows a 10 dB reduction
in the peak RF energy when using CY25562 SSCG clock.
Modulation Rate
50 %
50 %
Tc = 5.0 ns
Clock frequency = fc = 200 MHz
Clock period = Tc = 1/200 MHz
If this clock is applied to the Xin/CLK pin of CY25562, the output
clock at pin 4 (SSCLK) sweeps back and forth between two
frequencies. These two frequencies, F1 and F2, calculate total
amount of spread or bandwidth applied to the reference clock at
pin 1. As the clock is making the transition, sweep, from F1 to
F2, the amount of time and sweep waveform become a very
Spread spectrum clock generators use frequency modulation
(FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (Fmax) and minimum
frequency of the clock (Fmin) determine this band of frequencies.
The time required to transition from Fmin to Fmax and back to
Fmin is the period of the modulation rate, Tmod. Modulation
rates of SSCG clocks are generally referred to in terms of
frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the modulation rate. In some SSCG clock generators, the selected range determines the internal divider count.
In other SSCG clocks, the internal divider count is fixed over the
operating range of the part. CY25562 has a fixed divider count
of 2332.
Figure 4. SSCG Clock, Part Number, Fin = 200 MHz
Device
CY25562
Cdiv
2332
(All Ranges)
Example:
Device =
CY25562
Fin
=
200 MHz
Range =
S1 = 1, S0 = 1
Then;
Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.
Modulation Profile
Document Number: 38-07392 Rev. *H
Spectrum Analyzer
Page 5 of 13
CY25562
CY25562 Application Schematic
Figure 5. Application Schematic
VDD
C3
0.1 uF
2
1
200 MHz Reference Clock
8
XIN/CLK
VDD
SSCLK
4
XOUT
CY25562
VDD
5
S1
SSCC
VSS
S0
6
VDD
7
3
The schematic in Figure 5 demonstrates how CY25562 is configured in a typical application. This application is using a 200 MHz
reference clock connected to pin 1. Because an external reference clock is used, pin 8 (Xout) is left unconnected.
This configuration depicts the profile and spectrum scans shown in Figure 4 on page 5. Note that S0 = S1 = 1, for a spread of
approximately 1.1 percent.
Document Number: 38-07392 Rev. *H
Page 6 of 13
CY25562
Absolute Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings [1, 2] may shorten the useful life of
the device. User guidelines are not tested.
Junction temperature ............................... –40 °C to +140 °C
Operating temperature .................................... 0 °C to 70 °C
Storage temperature ................................ –65 °C to +150 °C
Supply voltage (VDD) ...................................–0.5 V to +6.0 V
Static discharge voltage (ESD) .......................... 2,000 V Min
Electrical Characteristics
VDD = 3.3 V, TA = 25 °C, and CL (Pin 4) = 15 pF unless otherwise noted
Parameter
Description
VDD
Power supply range
Conditions
±10%
Min
Typ
Max
Unit
2.97
3.3
3.63
V
VDD
VDD
V
VINH
Input high voltage
S0 and S1 only
0.85 × VDD
VINM
Input middle voltage
S0 and S1 only
0.40 × VDD 0.50 × VDD 0.60 × VDD
VINL
Input low voltage
S0 and S1 only
0.0
0.0
0.15 × VDD
V
VOH1
Output high voltage
IOH = 6 mA
2.4
–
–
V
VOH2
Output high voltage
IOH = 20 mA
2.0
–
–
V
VOL1
Output low voltage
IOH = 6 mA
–
–
0.4
V
VOL2
Output low voltage
IOH = 20 mA
–
–
1.2
V
Cin1
Input capacitance
Xin/CLK (pin 1)
3
4
5
pF
Cin2
Input capacitance
Xout (pin 8)
6
8
10
pF
Cin2
Input capacitance
S0, S1, SSCC (pins 7, 6, 5)
3
4
5
pF
V
IDD1
Power supply current
Fin = 65 MHz, CL = 15 pF
–
23
30
mA
IDD2
Power supply current
Fin = 200 MHz, CL =15 pF
–
53
66
mA
IDD3
Power supply current
Fin = 200 MHz, no load
–
48
60
mA
Thermal Resistance
Parameter [3]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
8-pin SOIC
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
131
°C/W
41
°C/W
Notes
1. Operation at any absolute maximum rating is not implied.
2. Single power supply: The voltage on any input or I/O pin cannot exceed the power pine during power-up.
3. These parameters are guaranteed by design and are not tested.
Document Number: 38-07392 Rev. *H
Page 7 of 13
CY25562
Electrical Timing Characteristics
VDD = 3.3 V, TA = 25 °C, and CL = 15 pF unless otherwise noted. Rise/Fall at 0.4 to 2.4 V, Duty at 1.5 V
Min
Typ
Max
Unit
ICLKFR
Parameter
Input clock frequency range
Description
Pk–Pk = 3.3 V
50
–
200
MHz
tRISE
Clock rise time (pin 4)
SSCLK, CL = 15 pF, 200 MHz
0.8
0.9
1.0
ns
tFALL
Clock fall time (pin 4)
SSCLK, CL = 15 pF, 200 MHz
0.8
0.9
1.0
ns
tRISE
Clock rise time (pin 4)
SSCLK, CL = 33 pF, 200 MHz
1.1
1.45
1.8
ns
tFALL
Clock fall time (pin 4)
SSCLK, CL = 33 pF, 200 MHz
1.1
1.5
1.9
ns
DTYin
Input clock duty cycle
XIN/CLK (pin 1)
30
50
70
%
DTYout
Output clock duty cycle
SSCLK1 (pin 4)
45
50
55
%
FM1
Frequency modulation
Fin = 70 MHz
29.5
30.0
30.5
kHz
FM2
Frequency modulation
Fin = 200 MHz
85.0
85.4
86
kHz
CCJ1
Cycle-to-Cycle jitter
Fin = 50 MHz, mod ON
–
150
175
ps
CCJ2
Cycle-to-Cycle jitter
Fin = 120 MHz, mod ON
–
175
200
ps
CCJ3
Cycle-to-Cycle jitter
Fin = 200 MHz, mod ON
–
250
300
ps
Document Number: 38-07392 Rev. *H
Conditions
Page 8 of 13
CY25562
Ordering Information
Part Number
Package Type
Product Flow
CY25562SXC
8-pin SOIC, Pb-free
Commercial, 0 C to 70 C
CY25562SXCT
8-pin SOIC – tape and reel, Pb-free
Commercial, 0 C to 70 C
Ordering Code Definitions
CY 25562 S
X
C
T
T = Tape and Reel; Blank = Tube
Temperature Range: C = Commercial
Pb-free
Package: S = 8-pin SOIC
Base part number
Company ID: CY = Cypress
Document Number: 38-07392 Rev. *H
Page 9 of 13
CY25562
Package Drawing and Dimensions
Figure 6. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-07392 Rev. *H
Page 10 of 13
CY25562
Acronyms
Acronym
Document Conventions
Description
Units of Measure
EMI
Electromagnetic Interference
PCB
Printed Circuit Board
%
percent
PLL
Phase-Locked Loop
°C
degree Celsius
SOIC
Small-Outline Integrated Circuit
dB
decibel
SSC
Spread Spectrum Clock
mA
milliampere
SSCG
Spread Spectrum Clock Generator
MHz
megahertz
mm
millimeter
ms
millisecond
mW
milliwatt
ns
nanosecond
pF
picofarad
ps
picosecond
V
volt
ohm
W
watt
Document Number: 38-07392 Rev. *H
Symbol
Unit of Measure
Page 11 of 13
CY25562
Document History Page
Document Title: CY25562, Spread Spectrum Clock Generator
Document Number: 38-07392
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
115526
07/08/02
OXC
New data sheet.
*A
119444
10/17/02
RGL
Updated Absolute Maximum Ratings:
Corrected the values to match the device.
*B
122703
12/28/02
RBI
Updated Absolute Maximum Ratings:
Added power up requirements to maximum ratings information.
*C
2567245
09/16/08
*D
3187957
03/04/2011
CXQ
*E
3537234
02/28/2012
PURU
*F
4586478
12/03/2014
AJU
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Drawing and Dimensions:
Updated package diagram 51-85066 to current revision.
*G
4709860
04/01/2015
TAVA
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*H
5278942
05/20/2016
PSR
Added Thermal Resistance.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *G to *H.
Updated to new template.
Document Number: 38-07392 Rev. *H
Description of Change
PYG / KVM Replaced CY25562SC w/ CY25562SXC, CY255652SCT w/ CY25562SXCT.
/ AESA Package changed from S8 to SZ8.
Updated to new template.
Updated Package Drawing and Dimensions.
Removed Benefits.
Removed Applications.
Added Ordering Code Definitions under Ordering Information.
Added Acronyms and Units of Measure.
Page 12 of 13
CY25562
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 38-07392 Rev. *H
Revised May 20, 2016
Page 13 of 13