CY26121
PacketClock™ Spread Spectrum
Clock Generator
PacketClock™ Spread Spectrum Clock Generator
Features
Benefits
■
Integrated phase-locked loop (PLL)
■
High-performance PLL tailored for spread spectrum application
■
Low jitter, high-accuracy outputs
■
Meets critical timing requirements in complex system designs
■
3.3 V operation
■
Enables application compatibility
■
25 MHz input frequency
■
Works with commonly available crystal or driven reference
■
33.33 MHz or 25 MHz selectable output frequency (-21)
■
Downspread spread spectrum with 30 kHz nominal modulation
frequency
Functional Description
For a complete list of related resources, click here.
Frequency Table
for CLKA-D
Part Number
CY26121-21
CLKSEL = 0
33.33 MHz
CLKSEL = 1
Spread%
25.00
–2.8%
Parallel Crystal Load
15 pF
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 38-07350 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 20, 2016
CY26121
Pin Configuration
Figure 1. 16-pin TSSOP pinout
XOUT
XIN
1
16
VDD
2
15
NC
AVDD
CLKSEL
3
14
REF
4
13
VSS
AVSS
5
12
VSSL
6
11
CLKD
VDDL
CLKA
7
10
SSON
CLKB
8
9
CLKC
Pin Definitions
Pin Name
Pin Number
Description
XIN
1
Reference input Or crystal input
VDD
2
3.3 V voltage supply
AVDD
3
3.3 V analog voltage
CLKSEL
4 (-21)
0 = 33.33 MHz out, 1 = 25 MHz Out. Weak pull-up.
AVSS
5
Analog ground
VSSL
6
CLK ground
CLK(A:D)
SSON
7, 8, 9, 12
Clock outputs at VDDL level
10
Spread spectrum enable pin 0 = SS off; 1 = SS on. Weak pull-up.
VDDL
11
3.3 V clock voltage supply
VSS
13
Ground
REF
14
Reference output at VDD level
15
No connect
16
Crystal output
NC
XOUT
[1]
Notes
1. Float XOUT if XIN is externally driven.
Document Number: 38-07350 Rev. *E
Page 2 of 9
CY26121
Maximum Ratings
Storage temperature
(Non-condensing) .................................... –55 C to +125 C
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Junction temperature .............................. –40 C to +125 C
Supply voltage (VDD, AVDD, VDDL) ................. –0.5 to +7.0 V
Data retention at Tj = 125 C ................................> 10 years
Package power dissipation ...................................... 350 mW
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2000 V
Recommended Operating Conditions
Parameter
Description
Min
Typ
Max
Unit
VDD, AVDD
Supply voltage
3.135
3.30
3.465
V
VDDL
Supply voltage for CLK (A-D)
3.135
3.30
3.465
V
TA
Ambient temperature (industrial temp grade)
–40
–
85
°C
CLOAD
Max. output load capacitance
–
–
15
pF
Fref
Reference frequency
–
25
–
MHz
Min
Typ
Max
Unit
Crystal Specification
Parameter [2]
Description
CRload
Crystal load capacitance (-21)
–
15
–
pF
ESR
Equivalent series resistance
–
–
50
Condition
Min
Typ
Max
Unit
–
mA
DC Electrical Specifications
Parameter
Description
IOH
Output high current
VOH = VDD – 0.5 V, VDD/VDDL= 3.3 V
12
24
IOL
Output low current
VOL = 0.5 V, VDD/VDDL = 3.3 V
12
24
–
mA
IIH
Input high current
VIH = VDD
–
5
10
A
IIL
Input low current
VIL = 0 V
–
–
50
A
VIH
Input high voltage
CMOS levels
0.7 × VDD
–
–
V
VIL
Input low voltage
CMOS levels
–
–
0.3 × VDD
V
CIN[3]
Input capacitance
Input pins excluding XIN
–
–
7
pF
RUP[3]
Pull-up resistor on input pins
VDD = 3.14 to 3.47 V, measured at
VIN = 0 V
80
100
150
k
IDD
Supply current
AVDD/VDD/VDDL Current.
–
42
60
mA
Thermal Resistance
Parameter [3]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
16-pin TSSOP Unit
90
°C/W
14
°C/W
Notes
2. A fundamental parallel resonant crystal must be used.
3. Guaranteed by Characterization, not 100% tested.
3. These parameters are guaranteed by design and are not tested.
Document Number: 38-07350 Rev. *E
Page 3 of 9
CY26121
AC Electrical Specifications
Parameter [4]
Description
Condition
Min
Typ
Max
Unit
DC
Output duty cycle
Duty Cycle is defined in Figure 2,
50% of VDD
45
50
55
%
ER
Rising edge rate
Output clock edge rate,
measured from 20% to 80% of VDD,
CLOAD = 15 pF. See Figure 3.
0.8
1.4
–
V/ns
EF
Falling edge rate
Output clock edge rate,
measured from 80% to 20% of VDD,
CLOAD = 15 pF. See Figure 3.
0.8
1.4
–
V/ns
tj
RMS clock cycle-to-cycle Jitter
RMS cycle-to-cycle jitter with
spread on. Measured at VDD/2.
–
15
40
ps
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition
t1
t2
VDD
50% of VDD
Clock
Output
0V
Figure 3. ER = (0.6 × VDD) /t3, EF = (0.6 × VDD) /t4
t3
t4
V
DD
80% of V DD
Clock
Output
20% of V DD
0V
Notes
4. Guaranteed by Characterization, not 100% tested.
Document Number: 38-07350 Rev. *E
Page 4 of 9
CY26121
Ordering Information
Ordering Code
Package Type
Operating Range
CY26121KZXI-21
16-pin TSSOP
Industrial, –40 °C to 85 °C
CY26121KZXI-21T
16-pin TSSOP – Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 26121 K
Z X
I -21 T
T = Tape and Reel, Blank = Tube
Fixed
Temperature range
I = Industrial
X = Pb-free
16 Pin TSSOP
Indicates Foundry Manufacturing
Base part Number
Company ID: CY = CYPRESS
Document Number: 38-07350 Rev. *E
Page 5 of 9
CY26121
Package Drawing and Dimensions
Figure 4. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 38-07350 Rev. *E
Page 6 of 9
CY26121
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Acronym
Description
Units of Measure
Table 2. Units of Measure
ESR
Equivalent Series Resistance
PLL
Phase-Locked Loop
°C
TSSOP
Thin-Shrunk Small Outline Package
k
kilohm
MHz
megahertz
Document Number: 38-07350 Rev. *E
Symbol
Unit of Measure
degree Celsius
µA
microampere
mA
milliampere
mW
milliwatt
ns
nanosecond
ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
Page 7 of 9
CY26121
Document History Page
Document Title: CY26121, PacketClock™ Spread Spectrum Clock Generator
Document Number: 38-07350
Rev.
ECN No.
Issue Date
Orig. of
Change
**
121669
02/11/03
CKN
*A
2440886
See ECN
KVM /
AESA
Updated Ordering Information:
Added part numbers CY26121ZXC-21, CY26121ZXC-21T, CY26121ZXI-21,
and CY26121ZXI-21T.
Added part numbers CY26121KZC-21, CY26121KZC-21T, CY26121KZI-21,
and CY26121KZI-21T.
Added part numbers CY26121KZXC-21, CY26121KZXC-21T,
CY26121KZXI-21, and CY26121KZXI-21T.
Removed part numbers CY26121ZI-11, CY26121ZI-11T, CY26121ZI-31 and
CY26121ZI-31T.
Added Note “Not recommended for new designs.” and referred in some MPNs.
Updated to new template.
*B
2899683
03/26/10
KVM
Removed reference to -2, -3, -11, -31 parts in all instances across the
document.
Updated Ordering Information:
Removed inactive parts.
Removed Note “Not recommended for new designs.” and its references.
Updated Package Drawing and Dimensions.
*C
3383431
09/26/2011
PURU
Updated Logic Block Diagram.
Added Ordering Code Definitions under Ordering Information.
Updated Package Drawing and Dimensions.
Added Acronyms and Units of Measure.
*D
4556342
10/30/2014
TAVA
Updated Package Drawing and Dimensions:
spec 51-85091 – Changed revision from *C to *E.
Updated to new template.
Completing Sunset Review.
*E
5279177
05/20/2016
PSR
Added Thermal Resistance.
Updated to new template.
Document Number: 38-07350 Rev. *E
Description of Change
New data sheet.
Page 8 of 9
CY26121
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2003-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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Document Number: 38-07350 Rev. *E
Revised May 20, 2016
Page 9 of 9