160 dB Range 100 pA to 10 mA Low Cost Logarithmic Converter ADL5303 Data Sheet FEATURES SIMPLIFIED BLOCK DIAGRAM APPLICATIONS VPS2 PWDN VPS1 10 16 12 ADL5303 PDB 5 2 IPD 3 4 VPDB BIAS VREF ~10kΩ VREF 6 0.5V VSUM VLOG INPT TEMPERATURE COMPENSATION VSUM 8 BFIN 5kΩ BFNG 15 7 14 11 GND ACOM GND VOUT 9 13 10661-001 Optimized for fiber optic photodiode interfacing 8 full decades of range Law conformance: 0.1 dB from 1 nA to 1 mA Single-supply operation: 3.0 V to 5.5 V Complete and temperature stable Accurate laser trimmed scaling Logarithmic slope of 10 mV/dB (at the VLOG pin) Basic logarithmic intercept at 100 pA Easy adjustment of slope and intercept Output bandwidth of 10 MHz, 15 V/μs slew rate Miniature 16-lead package (LFCSP) Low power: ~4.5 mA quiescent current (enabled) Figure 1. High accuracy optical power measurement Wide range baseband log compression Versatile detector for APC loops GENERAL DESCRIPTION The ADL5303 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiber optic systems and offers a large dynamic range in a versatile and easily used form. Wide measurement range and accuracy are achieved using proprietary design and precise laser trimming. The ADL5303 requires only a single positive supply, VPS, of 5 V. When using low supply voltages, the log slope can be altered to fit the available span. Low quiescent current and chip disable facilitate use in battery-operated applications. The input current, IPD, flows in the collector of an optimally scaled NPN transistor, connected in a feedback path around a low offset JFET amplifier. The current summing input node operates at a constant voltage, independent of current, with a default value of 0.5 V; this may be adjusted over a wide range. An adaptive biasing scheme is provided for reducing photodiode dark current at very low light input levels. The VPDB pin applies approximately 0.1 V reverse bias across the photodiode for IPD = 100 pA, rising linearly to 2.0 V of reverse bias at IPD = 10 mA to improve response time at higher power levels. The Rev. 0 input pin INPT is flanked by the VSUM guard pins that track the voltage at the summing node. Connecting the exposed pad of the device to the VSUM pins provides a continuous guard to minimize leakage into the INPT pin. The default value of the logarithmic slope at the VLOG output is set by an internal 5 kΩ resistor. Logarithmic slope can be lowered with an external shunt resistor or increased using the buffer and a pair of external feedback resistors. The addition of a capacitor at the VLOG pin provides a simple low-pass filter. The intermediate voltage, VLOG, is buffered in an output stage that can swing to within about 100 mV of ground and the positive supply, VPS, and provides a peak current drive capacity of ±20 mA. An on-board 2 V reference is provided to facilitate the repositioning of the intercept. The incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. At IPD =1 nA, the bandwidth of the ADL5303 is approximately 2 kHz increasing in proportion to IPD up to a maximum value of 10 MHz. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5303 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Bandwidth and Noise Considerations ..................................... 10 Applications ....................................................................................... 1 Chip Enable ................................................................................. 11 Simplified Block Diagram ............................................................... 1 Using the ADL5303 ........................................................................ 12 General Description ......................................................................... 1 Slope and Intercept Adjustments ............................................. 12 Revision History ............................................................................... 2 Low Supply Slope and Intercept Adjustment ......................... 15 Specifications..................................................................................... 3 Changing the Voltage at the Summing Node ............................ 15 Absolute Maximum Ratings ............................................................ 4 Using the Adaptive Bias ............................................................. 16 ESD Caution .................................................................................. 4 Applications Information .............................................................. 17 Pin Configuration and Function Descriptions ............................. 5 Rescaling ...................................................................................... 17 Typical Performance Characteristics ............................................. 6 Inverting the Slope ..................................................................... 17 Theory of Operation ...................................................................... 10 Evaluation Board ........................................................................ 18 Basic Concepts ............................................................................ 10 Shields and Guards..................................................................... 18 Optical Measurements ............................................................... 10 Outline Dimensions ....................................................................... 21 Decibel Scaling............................................................................ 10 Ordering Guide .......................................................................... 21 REVISION HISTORY 1/13—Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet ADL5303 SPECIFICATIONS VPS = 5 V, GND, ACOM = 0 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT INTERFACE Specified Current Range Input Node Voltage Temperature Drift Input Guard Offset Voltage PHOTODIODE BIAS 2 Minimum Value Transresistance LOGARITHMIC OUTPUT Slope Intercept Law Conformance Error Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage WRT Ground Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Output Resistance Wideband Noise 3 Small Signal Bandwidth3 Slew Rate POWER-DOWN INPUT Logic Level, High State Logic Level, Low State POWER SUPPLY Supply Voltage Quiescent Current In Disabled State Test Conditions/Comments Pin 3, INPT; Pin 2 and Pin 4, VSUM Flows toward Pin 3 Internally preset; may be altered −40°C < TA < +85°C VOFS = VIN – VSUM Established between VPDB and INPT IPD = 100 pA Pin 8, VLOG Laser trimmed at 25°C 0°C < TA < 70°C Laser trimmed at 25°C 0°C < TA < 70°C 10 nA < IPD < 1 mA, peak error 1 nA < IPD < 1 mA, peak error Laser trimmed at 25°C Pin 6, VREF Laser trimmed at 25°C −40°C < TA < +85°C Min 1 Typ Max1 100 0.46 0.5 0.04 −20 +20 70 100 200 195 193 60 35 200 4.95 1.98 1.92 10 0.54 100 0.05 0.1 1.6 0.1 5 2 Unit pA mA V mV/°C mV mV mV/mA 205 207 140 175 0.25 0.7 5.05 mV/dec mV/dec pA pA dB dB V V kΩ 2.02 2.08 V V Ω +20 mV μA MΩ V Ω μV/√Hz MHz V/μs 2 Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT −20 Flowing out of Pin 9 or Pin 13 0.4 35 VPS − 0.1 0.5 1 10 15 RL = 1 kΩ to ground IPD > 1 μA (see the Typical Performance Characteristics section) IPD > 1 μA (see the Typical Performance Characteristics section) 0.2 V to 4.8 V output swing Pin 16, PWDN −40°C < TA < +85°C, 2.7 V < VPS < 5.5 V −40°C < TA < +85°C, 2.7 V < VPS < 5.5 V Pin 10 and Pin 12, VPS2 and VPS1; Pin 14 and 15, GND 2 1 3.0 Minimum and maximum specified limits on parameters are guaranteed but not tested and are six sigma values. This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground. 3 Output noise and incremental bandwidth are functions of input current; see the Typical Performance Characteristics section. 1 2 Rev. 0 | Page 3 of 24 5 4.5 60 5.5 5.6 V V V mA μA ADL5303 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Parameter VPS Input Current to INPT Thermal Data, 2-Layer JEDEC Board, No Air Flow (Exposed Pad Soldered to PCB) θJA θJC Maximum Power Dissipation (Exposed Pad Soldered to PCB) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 6V 20 mA 61.6°C/W 1.2°C/W 0.6 W ESD CAUTION 125°C −40°C to +85°C −65°C to +150°C 300°C Rev. 0 | Page 4 of 24 Data Sheet ADL5303 VLOG 8 9 BFIN NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE VSUM PINS TO PROVIDE LOW LEAKAGE GUARD. 10661-002 14 GND 10 VPS2 ACOM 7 11 VOUT TOP VIEW (Not to Scale) VPDB 5 VSUM 4 12 VPS1 ADL5303 VREF 6 INPT 3 13 BFNG 16 PWDN PIN 1 INDICATOR NC 1 VSUM 2 15 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic NC 2, 4 3 5 VSUM INPT VPDB 6 7 8 9 10 11 12 13 14, 15 16 17 VREF ACOM VLOG BFIN VPS2 VOUT VPS1 BFNG GND PWDN EPAD Description Pins labeled NC can be allowed to float, but it is better to connect these pins to ground. Avoid routing high speed signals through these pins because noise coupling may result. Guard Pins. VSUM is used to shield the INPT current line. Photodiode Current Input. Connect this pin to the photodiode anode (the photo current flows toward INPT). Photodiode Biaser Output. Connect this pin to the photodiode cathode when using adaptive bias control; otherwise, leave this pin floating. Voltage Reference Output of 2 V. Analog Reference Ground. Output of the Logarithmic Front-End Processor. ROUT = 5 kΩ to ground. Buffer Amplifier Noninverting Input (High Impedance). Positive Supply, VPS (3.0 V to 5.5 V). Buffer Output; Low Impedance. Positive Supply, VPS (3.0 V to 5.5 V). Buffer Amplifier Inverting Input. Power Supply Ground Connection. Power-Down Control Input. Device is active when PWDN is taken low. Exposed Pad. Connect the exposed pad to the VSUM pins to provide low leakage guard. Rev. 0 | Page 5 of 24 ADL5303 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.510 1.6 –40°C +25°C +85°C 1.4 TA = –40°C, +25°C, +85°C 0.508 1.2 VSUM (V) VLOG (V) 1.0 0.8 0.6 0.506 0.504 –40°C +25°C 0.4 +85°C 0.502 1n 10n 100n 1µ 10µ 100µ 1m 10m IPD (A) 0.500 100p 10661-003 0 100p 1n 10n 1µ 10µ 1m 100µ 10m IPD (A) Figure 3. VLOG vs. IPD Figure 6. VSUM vs. IPD 2.0 2.8 +85°C +25°C –40°C 2.6 1.5 2.4 1.0 2.2 2.0 0.5 +25°C VPDB (V) ERROR (dB) 10mV/dB SCALE 100n 10661-006 0.2 0 –0.5 1.8 1.6 1.4 +85°C 1.2 –1.0 –40°C 1.0 –1.5 1µ 10µ 100µ 1m 10m IPD (A) 0.6 0 1 2 5 6 7 8 10 9 Figure 7. VPDB vs. IPD 2.4 4.5V 5.0V 5.5V 2.2 1.25 TA = –40°C, +25°C, +85°C VP = 3.0V 1.00 0.75 2.0 0.5 VOUT (V) 1.8 0 –40°C 0.50 0.25 1.6 1.4 +25°C 0 +85°C –0.5 –1.0 100p 1n 10n 100n 1µ IPD (A) 10µ 100µ 1m 10m Figure 5. Absolute Deviation from Nominal Specified Value of VLOG for Several Supply Voltages @ 25°C 1.2 –0.25 1.0 –0.50 0.8 –0.75 0.6 100p 10661-005 ERROR(dB) 10mV/dB SCALE 4 IPD (mA) Figure 4. Logarithmic Conformance (Linearity) for VLOG 1.0 3 1n 10n 100n 1µ 10µ 100µ 1m ERROR ((dB) (10mV/dB)) 100n –1.00 10m IPD (A) Figure 8. Logarithmic Conformance (Linearity) for a 3 V Single Supply Rev. 0 | Page 6 of 24 10661-008 10n 10661-004 1n 10661-007 0.8 –2.0 100p Data Sheet ADL5303 10 10nA 100nA 10 1µA 10µA 10mA 1nA A –10 WIDEBAND NOISE (mV rms) 1mA –20 –30 –40 –50 8 7 6 5 4 3 2 –60 1 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 0 1n 10661-009 –70 100 10n 100n 1µ 10µ 100µ 1m 10m INPUT CURRENT (A) 10661-012 NORMALIZED RESPONSE (dB) 9 100µA 0 Figure 12. Total Wideband Noise Voltage at VLOG vs. IPD Figure 9. Small Signal AC Response, IPD to VLOG (5% Sine Modulation of IPD at Frequency) 3 100 GAIN = 1×, 2×, 2.5×, 5× 100kHz 1 100Hz 1kHz 1MHz 0.1 0.01 1n 10n 100n 1µ 10µ 100µ 1m 10m IPD (A) 0 AV = 5 AV = 2.5 –6 AV = 2 –9 10k 100k 1M 10M 100M Figure 13. Small Signal Response of Buffer 10 100 fC =1kHz 1nA NORMALIZED RESPONSE (dB) –10 10 10nA 1µA 100nA 10µA >100µA 0.1 0 –20 –30 –40 –50 0.01 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 11. Spot Noise Spectral Density at VLOG vs. Frequency –70 10 100 1k FREQUENCY (Hz) 10k 100k 10661-014 –60 10661-011 (µV rms/√Hz) 1k FREQUENCY (Hz) Figure 10. Spot Noise Spectral Density at VLOG vs. IPD 1 AV = 1 –3 –12 100 10661-010 (µV rms/√Hz) 10 10661-013 NORMALIZED RESPONSE (dB) 10kHz Figure 14. Small Signal Response of Buffer Operating as Two-Pole Filter Rev. 0 | Page 7 of 24 ADL5303 Data Sheet 20 2.0 TA = 25°C 15 1.5 MEAN + 3σ 10 ERROR (dB) ((10mV/dB)) 1.0 VREF DRIFT (mV) 5 MEAN + 3σ 0.5 0 MEAN – 3σ –0.5 0 –5 –10 –15 –1.0 MEAN – 3σ –20 –1.5 10n 100n 1µ 10µ 1m 100µ –30 –40 –30 –20 –10 10661-015 1n 10m INPUT (A) 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 15. Logarithmic Conformance Error Distribution (3 σ to Either Side of Mean) 10661-018 –25 –2.0 100p Figure 18. VREF Drift vs. Temperature (3 σ to Either Side of Mean) 5 3 TA = 0°C, 70°C ERROR ((dB) (10mV/dB)) 3 2 MEAN + 3σ @ 70°C 1 MEAN ± 3σ @ 0°C 0 –1 MEAN – 3σ @ 70°C –2 –3 –4 1n 10n 100n 1µ 10µ 100µ 1m 10m INPUT (A) MEAN + 3σ 1 0 –1 –2 –3 MEAN – 3σ –4 –5 –40 –30 –20 –10 10661-016 –5 100p 2 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 16. Logarithmic Conformance Error Distribution (3 σ to Either Side of Mean) 10661-019 SLOPE CHANGE FROM 25°C (mV/dec) 4 Figure 19. Slope Drift vs. Temperature (3 σ to Either Side of Mean) 40 5 TA = –40°C, +85°C INTERCEPT CHANGE FROM 25°C (pA) MEAN + 3σ @ –40°C ERROR ((dB) (10mV/dB)) 3 2 1 MEAN ± 3σ @ +85°C 0 –1 –2 –3 MEAN – 3σ @ –40°C –4 1n 10n 100n 1µ INPUT (A) 10µ 100µ 1m 10m MEAN + 3σ 20 10 0 –10 –20 –30 MEAN – 3σ –40 –50 –40 –30 –20 –10 10661-017 –5 100p 30 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 90 10661-020 4 Figure 20. Intercept Drift vs. Temperature (3 σ to Either Side of Mean) Figure 17. Logarithmic Conformance Error Distribution (3 σ to Either Side of Mean) Rev. 0 | Page 8 of 24 Data Sheet ADL5303 8 160 140 6 120 MEAN + 3σ 100 2 HITS 80 0 60 –2 –6 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 0 60 180 160 160 140 140 120 120 100 100 HITS 180 80 80 60 60 40 40 20 20 0 196 198 200 202 LOGARITHMIC SLOPE (mV/dec) Figure 22. Distribution of Logarithmic Slope 204 140 Figure 23. Distribution of Logarithmic Intercept 0 –20 10661-022 HITS Figure 21. Output Buffer Offset vs. Temperature (3 σ to Either Side of Mean) 80 100 120 LOGARITHMIC INTERCEPT (pA) 10661-023 20 10661-021 –4 40 MEAN – 3σ –10 0 10 INPUT GUARD OFFSET (mV) 20 10661-024 Vos DRIFT (mV) 4 Figure 24. Distribution of Input Guard Offset Voltage VOFS (VINPT – VSUM) Rev. 0 | Page 9 of 24 ADL5303 Data Sheet THEORY OF OPERATION Therefore, Equation 1 can be written as BASIC CONCEPTS VLOG = VY log10(POPT/PZ) The ADL5303 uses an advanced circuit implementation that exploits the logarithmic relationship between the base-toemitter voltage, VBE, and collector current, IC, in a bipolar transistor. Using these principles, the relationship between the input current, IPD, applied to the INPT pin, and the voltage appearing at the intermediate output VLOG pin is: VLOG = VY log10(IPD/IZ) (1) where: VY is the voltage slope (in the case of base-10 logarithms, it is also referred to as volts per decade). IZ is the fixed current in the logarithmic equation called the intercept. In the following example, the scaling is chosen so that VY is trimmed to 200 mV/decade (10 mV/dB). The intercept is positioned at 100 pA; the output voltage, VLOG, crosses zero when IPD is of this value. However, the actual VLOG must always be slightly above ground. Using Equation 2, calculate the output for any value of IPD. Thus, for an input current of 25 nA, VLOG = 0.2 V log10(25 nA/100 pA) = 0.4796 V (2) In practice, both the slope and intercept can be altered, to either higher or lower values, without any significant loss of calibration accuracy, by using one or two external resistors, often in conjunction with the trimmed 2 V voltage reference at the VREF pin. (5) For the ADL5303 operating in its default configuration, an IZ of 100 pA corresponds to a PZ of 110 pW, for a diode having a responsivity of 0.9 A/W. Thus, an optical power of 3 mW generates VLOG = 0.2 V log10(3 mW/110 pW) = 1487 V (6) Note that when using the ADL5303 in optical applications the VLOG output is referred to in terms of the equivalent optical power, the logarithmic slope remains 10 mV/dB at this output. This can be confusing because a decibel change on the optical side has a different meaning than on the electrical side. In either case, the logarithmic slope can always be expressed in units of millivolts per decade to help eliminate confusion. DECIBEL SCALING When power levels are expressed as decibels above a reference level (in dBm, for a reference of 1 mW), the logarithmic conversion has already been performed, and the log ratio in the previous expressions becomes a simple difference. Be careful in assigning variable names here, because P is often used to denote actual power as well as this same power expressed in decibels; however, these are numerically different quantities. BANDWIDTH AND NOISE CONSIDERATIONS OPTICAL MEASUREMENTS Response time and wideband noise of translinear log amps are a function of the signal current, IPD. Bandwidth becomes progressively lower as IPD is reduced, largely due to the effects of junction capacitances in the translinear device. When interpreting the IPD current in terms of optical power incident on a photodetector, it is necessary to be clear about the conversion (optical power to current) properties of a reverse biased photodiode. The units of this conversion are expressed in amps per watt and referred to as photodiode responsivity, ρ. For the typical InGaAs PIN photodiode, the responsivity is approximately 0.9 A/W. Figure 9 shows ac response curves for the ADL5303 at eight representative currents of 1 nA to 10 mA, using R1 = 750 Ω and C1 = 1000 pF. The values for R1 and C1 ensure stability over the full 160 dB dynamic range. More optimal values may be used for smaller subranges. A certain amount of experimental trial and error may be necessary to select the optimum input network component values for a given application. It is important to note that in purely electrical circuits, current and power are not related in this proportional manner. A current applied to a resistive load results in a power proportional to the square of the current, P = I2R. The difference in scaling for a photodiode is because IPD flow in a reverse-biased diode is largely dependent on the fixed built-in voltage of the PN junction and is relatively insensitive to the external bias voltage. In the detector diode, power dissipated is proportional to the IPD current and the relationship of IPD to the optical power, POPT, is preserved. The relationship between IPD and the voltage noise spectral density, SNSD, associated with the VBE of Q1, calculates to the following: IPD = ρPOPT SNSD = where: SNSD is nV/Hz. IPD is expressed in microamps. TA = 25°C. (3) The same relationship exists between the intercept current, IZ, and an equivalent intercept power, PZ, thus, IPZ = ρPZ 14.7 I PD (4) Rev. 0 | Page 10 of 24 (7) Data Sheet ADL5303 For an input of 1 nA, SNSD evaluates to almost 0.5 μV/√Hz; assuming a 20 kHz bandwidth at this current, the integrated noise voltage is 70 μV rms. However, this calculation is not complete. The basic scaling of the VBE is approximately 3 mV/dB; translated to 10 mV/dB, the noise predicted by Equation 7 must be multiplied by approximately 3.33. The additive noise effects associated with the reference transistor, Q2, and the temperature compensation circuitry must also be included. The final voltage noise spectral density presented at the VLOG pin varies inversely with IPD, but is not a simple square root relationship. Figure 10 shows the measured noise spectral density vs. frequency at the VLOG output, for the same nine-decade spaced values of IPD. CHIP ENABLE Power down the ADL5303 by taking the PWDN pin to a high logic level. The residual supply current in the disabled mode is typically 60 μA. Rev. 0 | Page 11 of 24 ADL5303 Data Sheet USING THE ADL5303 The slope can be lowered without limit by the addition of a shunt resistor, RS, from VLOG to ground. Because the resistance at this pin is trimmed to 5 kΩ, the accuracy of the modified slope depends on the external resistor. It is calculated by, The default configuration (see Figure 25) includes a 2.5:1 attenuator in the feedback path around the buffer. This increases the slope of 10 mV/dB at the VLOG pin to 25 mV/dB at VOUT. For the full dynamic range of 160 dB (80 dB optical), the output swing is 4.0 V, which can be accommodated by the rail-to-rail output stage when using the recommended 5 V supply. VY = The capacitor from VLOG to ground forms an optional single-pole low-pass filter. Because the resistance at this pin is trimmed to 5 kΩ, an accurate time constant can be realized. For example, with CFLT = 10 nF, the −3 dB corner frequency is 3.2 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are even more effective in reducing noise. A capacitor between VSUM and ground is essential for minimizing the noise on this node. When the bias voltage at either VPDB or VREF is not needed, these pins should be left unconnected. VY RS RS + 5 kΩ (8) For example, using RS = 3 kΩ, the slope is lowered to 75 mV per decade or 3.75 mV/dB. Table 4 provides a selection of suitable values for RS and the resulting slopes. Table 4. Examples of Lowering the Slope RS (kΩ) 3 5 15 VY (mV/decade) 75 100 150 In addition to uses in filter and comparator functions, the buffer amplifier provides the means to adjust both the slope and intercept, which require a minimal number of external components. The high input impedance at BFIN, low input offset voltage, large output swing, and wide bandwidth of this amplifier permit numerous transformations of the basic VLOG signal, using standard op amp circuit practices. For example, it has been noted that to raise the gain of the buffer, and therefore the slope, a feedback attenuator, RA and RB in Figure 25, should be inserted between VLOG and the inverting input BFNG pin. SLOPE AND INTERCEPT ADJUSTMENTS The choice of slope and intercept depends on the application. The versatility of the ADL5303 permits optimal choices to be made in two common situations. First, it allows an input current range of less than the full 160 dB to use the available voltage span at the output. Second, it allows this output voltage range to be optimally positioned to fit the input capacity of a subsequent ADC. In special applications, very high slopes, such as 1 V/decade, allow small subranges of IPD to be covered at high sensitivity. VP PWDN VPS2 VPS1 10 16 12 PDB BIAS VREF ADL5303 IPD 2 3 C1 1nF 4 6 NC ~10kΩ 0.5V 200mV/DEC VSUM C7 (CFILT) VLOG INPT 8 TEMPERATURE COMPENSATION BFIN 9 5kΩ VSUM BFNG 13 R18 (RB) 10kΩ C3 100nF R1 750 15 GND 7 ACOM 14 GND 11 R15 (RA) 15kΩ VOUT VOUT 500mV/DEC NC = NO CONNECT Figure 25. Basic Connections (R15, R18, C7 are Optional; R1 and C1 are the Default Values) Rev. 0 | Page 12 of 24 10661-025 NC 5 VREF VPDB Data Sheet ADL5303 buffer. Table 5 lists some examples of lowering the intercept combined with several slope variations. A wide range of gains may be used and the resistor magnitudes are not critical; their parallel sum should be about equal to the net source resistance at the noninverting input. When high gains are used, the output dynamic range is reduced; for a maximum swing of 4.8 V, it amounts to 4.8 V/VY decades. Thus, using a ratio of 3×, to set up a slope 30 mV/dB (600 mV/ decade), eight decades can be handled, whereas with a ratio of 5×, which sets up a slope of 50 mV/dB (1 V/decade), the dynamic range is 4.8 decades, or 96 dB. When using a lower supply voltage, the calculation proceeds in the same way, remembering to first subtract 0.2 V to allow for 0.1 V upper and lower headroom in the output swing. Table 5. Examples of Lowering the Intercept VY (mV/decade) 200 200 200 300 300 300 400 400 400 500 500 500 Alteration of the logarithmic intercept is only slightly more tricky. First, note that it is rarely necessary to lower the intercept below a value of 100 pA, because this merely raises all output voltages further above ground. However, where this is required, the first step is to raise the voltage, VLOG, by connecting a resistor, RZ, from VLOG to VREF (2 V) as shown in Figure 26. IZ (pA) 1 10 50 1 10 50 1 10 50 1 10 50 RA (kΩ) 20.0 10.0 3.01 10.0 8.06 6.65 11.5 9.76 8.66 16.5 14.3 13.0 I RLOG RZ × log10 PD + VREF × VOUT = G VY × (9) RLOG + RZ RZ + RLOG IZ where G = 1 + RA/RB and RLOG = 5 kΩ. VP PWDN VPS1 16 10 12 ADL5303 PDB IPD NC 5 2 3 C1 1nF 4 BIAS VREF VREF 6 VPDB ~10kΩ R14 (RZ) 0.5V VSUM VLOG INPT 8 TEMPERATURE COMPENSATION BFIN 5kΩ VSUM 9 BFNG 13 R18 (RB) C3 100nF R1 750Ω 7 ACOM 14 GND 11 R15 (RA) VOUT VOUT 500mV/DEC NC = NO CONNECT Figure 26. Method for Lowering the Intercept Rev. 0 | Page 13 of 24 10661-026 15 GND RZ (kΩ) 25 50 165 25 50 165 25 50 165 25 50 165 Use the following equation with Table 5: This has the effect of elevating, VLOG, for small inputs while lowering the slope to some extent because of the shunt effect of RZ on the 5 kΩ output resistance. If necessary, the slope may be increased as before, using a feedback attenuator around the VPS2 RB (kΩ) 100 100 100 12.4 12.4 12.4 8.2 8.2 8.2 8.2 8.2 8.2 ADL5303 Data Sheet Table 6. Examples of Raising the Intercept Generally, it is useful to raise the intercept. Keep in mind that this moves the VLOG line in Figure 26 to the right, lowering all output values. Figure 27 shows how raising the intercept is achieved. The feedback resistors, RA and RB, around the buffer are now augmented with a third resistor, RZ, placed between the BFNG and VREF pins. Adding a third resistor raises the zerosignal voltage on BFNG, which has the effect of pushing VOUT lower. Note that the addition of the RZ resistor also alters the feedback ratio. However, this change in feedback ratio is readily compensated in the design of the network. Table 6 lists the resistor values for representative intercepts. VY (mV/decade) 300 300 400 400 400 500 500 500 IZ (nA) 10 100 10 100 500 10 100 500 RA (kΩ) 7.5 8.25 10 9.76 9.76 12.4 12.4 11.5 R A RB = VREF × R A RB + RC RA R × RB and R A RB = A . RB RC RA × RB where G = 1 + VP PWDN VPS1 10 16 12 PDB BIAS VREF ADL5303 IPD 2 3 C1 1nF 4 VREF 6 VPDB ~10kΩ 0.5V VSUM VLOG INPT 8 TEMPERATURE COMPENSATION BFIN 5kΩ VSUM R13 (RC) 9 BFNG 13 C3 100nF R18 (RB) R1 750 15 GND 7 ACOM 14 GND 11 R15 (RA) VOUT VOUT 500mV/DEC NC = NO CONNECT Figure 27. Method for Raising the Intercept Rev. 0 | Page 14 of 24 10661-027 NC 5 RC (kΩ) 24.9 18.2 25.5 16.2 13.3 24.9 16.5 12.4 Use the following equation with Table 6: I VOUT = G VY × log 10 PD IZ VPS2 RB (kΩ) 37.4 130 16.5 25.5 36.5 12.4 16.5 20.0 (10) Data Sheet ADL5303 CHANGING THE VOLTAGE AT THE SUMMING NODE LOW SUPPLY SLOPE AND INTERCEPT ADJUSTMENT The default value of VSUM is determined by using a quarter of VREF (2 V). This can be altered by applying an independent voltage source to VSUM, or by adding an external resistive divider from VREF to VSUM. This network operates in parallel with the internal divider (40 kΩ and 13.3 kΩ), and the choice of external resistors should take this into account. In practice, the total resistance of the added string may be as low as 10 kΩ (consuming 400 μA from VREF). Low values of VSUM and thus VCE are not advised when large values of IPD are expected. When using the device with a supply of less than 4 V, it is necessary to reduce the slope and intercept at the VLOG pin to preserve good log conformance over the entire 160 dB operating range. The voltage at the VLOG pin is generated by an internal current source with an output current of 40 μA/decade feeding the internal laser trimmed output resistance of 5 kΩ. When the voltage at the VLOG pin exceeds VP − 2.3 V, the current source ceases to respond linearly to logarithmic increases in current. Avoid headroom issues by reducing the logarithmic slope and intercept at the VLOG pin and by connecting an external resistor, RS, from the VLOG pin to ground in combination with an intercept lowering resistor, RZ. The values shown in Figure 28 illustrate a good solution for a 3.0 V positive supply. The resulting logarithmic slope measured at VLOG is 62.5 mV/decade with a new intercept of 57 fA. The original logarithmic slope of 200 mV/decade can be recovered using voltage gain on the internal buffer amplifier. VP PWDN VPS2 VPS1 16 10 12 ADL5303 PDB IPD 2 3 C1 1nF 4 VREF VREF ~10kΩ 6 R14 (RZ) 15.4kΩ 0.5V VSUM VLOG INPT TEMPERATURE COMPENSATION VSUM 8 BFIN 5kΩ BFNG C7 (RS) 2.67kΩ 9 13 R18 (RB) 2.26kΩ C3 100nF R1 750Ω 15 GND 7 ACOM 14 GND 11 R15 (RA) 4.98kΩ VOUT VOUT 500mV/DEC NC = NO CONNECT Figure 28. Recommended Low Supply Application Circuit Rev. 0 | Page 15 of 24 10661-028 NC 5 BIAS VPDB ADL5303 Data Sheet USING THE ADAPTIVE BIAS range, the adaptive biasing function is valuable in minimizing dark current while preventing the loss of photodiode bias at high currents. Use of the adaptive bias feature is shown in Figure 29. For most photodiode applications, the placement of the anode somewhat above ground is acceptable, as long as the positive bias on the cathode is adequate to support the peak current for a particular diode, limited mainly by its series resistance. To address this matter, the ADL5303 provides for a diode bias that increases linearly with the current. This bias voltage appears at the VPDB pin, and varies from 0.6 V (reverse-biasing the diode by 0.1 V) for IPD = 100 pA and rises to 2.6 V (for a diode bias of 2 V) at IPD = 10 mA. This results in a constant internal junction bias of 0.1 V when the series resistance of the photodiode is 200 Ω. For optical power measurements over a wide dynamic Capacitor CPB, between the photodiode cathode at the VPDB pin and ground, is included to lower the impedance at this node and thereby improve the high frequency accuracy at current levels where the ADL5303 bandwidth is high. CPB also ensures a high frequency path for any high frequency modulation on the optical signal, which might not otherwise be accurately averaged. CPB is not necessary in all cases, and experimentation may be required to find an optimum value. VP PWDN VPS2 10 VPS1 16 12 ADL5303 CPB R25 PDB 5 IPD 2 3 C1 1nF 4 BIAS VREF VREF 6 NC VPDB ~10kΩ 0.5V VSUM C7 (CFILT) VLOG INPT 8 TEMPERATURE COMPENSATION BFIN 5kΩ VSUM 9 BFNG 13 R18 (RB) 10kΩ C3 100nF R1 750 15 GND 7 ACOM 14 GND 11 R15 (RA) 15kΩ VOUT VOUT 500mV/DEC NC = NO CONNECT Figure 29. Using the Adaptive Biasing Rev. 0 | Page 16 of 24 10661-029 LOCATION Data Sheet ADL5303 APPLICATIONS INFORMATION when not needed. Figure 30 shows its use as an inverting amplifier; this changes the polarity of the slope. The output can be repositioned to a positive value by applying a fraction of VREF to the BFIN pin. The full design for a practical application is left undefined in this brief illustration, but a few cases are discussed, as follows. Smaller input voltages can be measured accurately when aided by a small offset nulling voltage applied to VSUM. The minimum voltage that can be accurately measured is limited only by the drift in the input offset of the ADL5303. The specifications show the maximum spread over the full temperature and supply range. Over a limited temperature range and with a regulated supply, the offset drift is lower; in this situation, processing of inputs down to 5 mV is practicable. For example, if slope of −30 mV/dB is needed; a gain of 3 is required. Because VLOG exhibits a source resistance of 5 kΩ, RA must be 15 kΩ. A positive offset, VOS, is applied to the BFIN pin, as indicated in Figure 30. The resulting output voltage can be expressed as RESCALING The use of a much larger value for the intercept may be useful in certain situations. In this example, it has been moved up four decades, from the default value of 100 pA to the center of the full eight-decade range at 1 mA. Using a voltage input as previously described, this corresponds to an altered voltage mode intercept, VZ, which is 1 V for RIN = 1 MΩ. To take full advantage of the larger output swing, the gain of the buffer has been increased to 4.53, resulting in a scaling of 900 mV/decade zand a full-scale output of ±3.6 V. R I VOUT = − A VY × log10 PD 5 kΩ IZ The buffer is essentially an uncommitted op amp that can be used to support the operation of the ADL5303 in a variety of ways. It can be completely disconnected from the signal chain VP PWDN VPS1 10 16 12 PDB BIAS VREF ADL5303 IPD NC 5 2 3 C1 1nF 4 VREF 6 NC VPDB ~10kΩ 0.5V VSUM VLOG INPT 8 TEMPERATURE COMPENSATION BFIN 5kΩ VSUM VOS 9 BFNG 13 C3 100nF R1 750Ω GND 7 ACOM 14 GND 11 R15 (RA) VOUT VOUT NC = NO CONNECT Figure 30. Using the Buffer to Invert the Polarity of the Slope Rev. 0 | Page 17 of 24 10661-030 15 (11) When the gain is set to 13 (RA = 5 kΩ), the 2 V VREF can be tied directly to BFIN, in which case the starting point for the output response is at 4 V. However, because the slope in this case is only −0.2 V/decade, the full current range takes the output down by only 1.6 V. Clearly, a higher slope (or gain) is desirable; in which case, set VOS to a smaller voltage to avoid railing the output at low currents. If VOS = 1.2 V and G = 33, VOUT now starts at 4.8 V and falls through this same voltage toward ground with a slope of −0.6 V per decade, spanning the full range of IPD. INVERTING THE SLOPE VPS2 + VOS ADL5303 Data Sheet EVALUATION BOARD An evaluation board is available for the ADL5303, the schematic for which is shown in Figure 31, and the board layout is shown in Figure 32 and Figure 33. It can be configured for a wide variety of experiments. The board is factory set for photoconductive mode with a buffer gain of unity, providing a slope of 10 mV/dB and an intercept of 100 pA. By substituting resistor and capacitor values, all of the application circuits presented in this data sheet can be evaluated. The system is completed by the final buffer amplifier, which is an uncommitted op amp with a rail-to-rail output capability, a 10 MHz bandwidth, and good load driving capabilities. The buffer can be used to implement multipole low-pass filters for noise reduction. The buffer also facilitates modification of the output scaling and the intercept point using simple resistor divider networks and the 2 V output provided by the VREF pin. SHIELDS AND GUARDS Reducing errors from external sources in a current sensing circuit requires a different approach then the voltage sensing input of the typical high impedance op-amp circuit. Leakage can be a significant source of error for highly sensitive log amps, especially at the low end of their range. For example, a 1 GΩ leakage path to ground from the INPT input with a VSUM set to the default 0.5 V generates a 0.5 nA offset. The ADL5303 evaluation board makes extensive use of guards to reduce the effects of leakage at low input levels. It is important to carefully handle and clean the ADL5303 evaluation board to prevent contaminants from handling or improper washing of the PCB causing leakage currents. Circuit board designs for the ADL5303 must connect the EPAD to the VSUM pins to provide a continuous guard around the sensitive INPT pin to reduce the influence of surface contaminants. A common mistake for those unfamiliar with low level current sensing is to attach a high impedance scope probe or meter to measure the input for debug. This can cause significant error, as the typical 1M ~ 100 MΩ impedance of these probes sources/ sinks current from the input, depending on their bias. In instrumentation applications where measurements <1 nA are required, the use of triaxial cables and connectors is common to reduce leakage through the insulating dielectric by carrying a continuous guard from current source to sensing circuit on the intermediate conductor. This type of guarding circuit is different from a conventional electrostatic shield used in voltage sensing applications. An electrostatic shield relies on low impedance and the ability to flow current freely to minimize voltage induced on the shield that can capacitively couple into a high impedance input. A guard is actively driven to the same voltage as the current carrying center conductor eliminating leakage through the dielectric between the center conductor and the guard. The guard does not flow current other than the leakage from the guard to the outer shield. The guard is usually connected to a single end of the cable only because any significant current flow through the guard can couple inductively to the center conductor. Using the ADL5303 evaluation board, the guard can be driven either from the guard of an external current source or from the internal VSUM bias of the ADL5303. The ADL5303 evaluation board can bias the shield of a coaxial cable connected to the INPT input to the nominal VSUM voltage with Switch S1 but this requires careful consideration of the environment on the other side of the cable. For example if the ADL5303 evaluation board is configured for VSUM = 0.5 V connecting the other end of the INPT coaxial cable to an instrument with a ground referenced shield pulls VSUM to ground and collapses the input stage of the ADL5303. Floating the current source end of the shield provides a low leakage guard but a separate return path for the signal current must then be provided. If cable dielectric leakage is not a concern, the INPT can be connected directly to a coaxial cable with the shield providing a signal ground. Rev. 0 | Page 18 of 24 Figure 31. Schematic Rev. 0 | Page 19 of 24 0Ω R4 AGND R6 DNI R25 OR (CPB) DNI 0Ω 0Ω AGND R24 AGND R2 0Ω 0Ω R3 1 S2 R5 DNI GND2 R23 C1 1000pF R1 750Ω 2 3 DNI = NOT INSTALLED IN DEFAULT CONFIGURATION AGND VPDB INPT 1 S1 AGND 2 AGND AGND C3 0.1µF R7 DNI VPOS AGND R9 DNI R8 DNI 4 3 2 1 ACOM VREF 7 6 16 15 14 13 5 VSUM INPT VSUM NC PAD R12 0Ω PWDN VPDB 3 GND VREF R10 10kΩ GND ACOM 1000PF 8 9 10 11 12 0Ω R26 DNI R14 (RZ) DNI R13 (RC) BFIN VPS2 VOUT U1 AGND GND1 VPS1 BFNG VLOG VPOS AGND GND2 R11 DNI 0Ω R16 R15 (RA) 15kΩ 0Ω R17 VPOS C5 0.1µF 10kΩ R18 (RB) 0.1µF C6 0Ω R22 0Ω C7 (CFILT OR RS) 0.1µF R20 0Ω R19 DNI R21 AGND AGND AGND AGND C8 0.1µF VLOG_OUT BUFFER_OUT AGND AGND 10661-031 C2 Data Sheet ADL5303 Data Sheet 10661-033 10661-032 ADL5303 Figure 33. Component Side Silkscreen Figure 32. Component Side Layout Table 7. Evaluation Board Configuration Options Component VPOS, AGND S1 S2 R13 (RC), R14 (RZ) R5, R6, R7, R8, R9 R15 (RA), R18 (RB) Function Positive supply and ground pins. Device enable. When S1 is in the 0 position, the PWDN pin is connected to ground and the ADL5303 is in its normal operating mode. Guard/shield options. The shells of the SMA connectors used for the input and the photodiode bias can be set to the voltage on the VSUM pin or connected to ground. When S2 is in the 0 position, the SMA shell is connected to VSUM. Intercept adjustment. A dc offset can be applied to the input terminals of the buffer amplifier to adjust the effective logarithmic intercept. Bias adjustment. The voltage on the VSUM and INPT pins can be altered using appropriate resistor values. Slope adjustment. C3 C6 R25 (CPB ) C5, C7 (CFILT or RS), C8, R11, R16, R17, R19, R20 R1, C1 VSUM decoupling capacitor. Supply decoupling capacitor. Photodiode biaser decoupling. Provides high frequency decoupling. Output filtering. Allows implementation of a variety of filter configurations, from simple RC low-pass filters to three-pole Sallen and Key filters. R2, R3, R4, R23, R24, R21, R22, R12, R26 Isolation jumpers. Input filtering. Provides essential HF compensation at the input pin, INPT. Rev. 0 | Page 20 of 24 Default Condition S1 = installed S2 = installed R13 = open (Size 0603) R14 = open (Size 0603) R5, R6, R7 = open (Size 0603) R8, R9 = open (Size 0603) R15 = 15 kΩ (Size 0603) R18 = 10 kΩ (Size 0603) C3 = 0.1 μF (Size 0603) C6 = 0.1 μF (Size 0603) R25 = open (Size 0603) R11, R19, C5 = Open (Size 0603) R16, R17, R20 = 0 Ω (Size 0603) C7, C8 = 0.1 μF (Size 0603) R1 = 750 Ω (Size 0402) C1 = 1 nF (Size 0603) All = 0 Ω (Size 0603) Data Sheet ADL5303 OUTLINE DIMENSIONS PIN 1 INDICATOR 3.10 3.00 SQ 2.90 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 1.65 1.50 SQ 1.45 9 0.80 0.75 0.70 SEATING PLANE 4 8 5 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 01-26-2012-A TOP VIEW 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-27) Dimensions shown in millimeters ORDERING GUIDE Model1 ADL5303ACPZ-R2 ADL5303ACPZ-R7 ADL5303ACPZ-RL ADL5303-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ, 7” Tape and Reel 16-Lead LFCSP_WQ, 13” Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 21 of 24 Package Option CP-16-27 CP-16-27 CP-16-27 Branding H38 H38 H38 Ordering Quantity 250 1500 5000 ADL5303 Data Sheet NOTES Rev. 0 | Page 22 of 24 Data Sheet ADL5303 NOTES Rev. 0 | Page 23 of 24 ADL5303 Data Sheet NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10661-0-1/13(0) Rev. 0 | Page 24 of 24