Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF5271EC Rev. 4, 08/2009 MCF5271 Integrated Microprocessor Hardware Specification by: Microcontroller Solutions Group The MCF5271 family is a highly integrated implementation of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions of the MCF5271 family. The MCF5271 family includes the MCF5271 and MCF5270 microprocessors. The differences between these parts are summarized below in Table 1. This document is written from the perspective of the MCF5271 and unless otherwise noted, the information applies also to the MCF5270. The MCF5271 family combines low cost with high integration on the popular version 2 ColdFire core with over 144 (Dhrystone 2.1) MIPS at 150 MHz. Positioned for applications requiring a cost-sensitive 32-bit solution, the MCF5271 family features a 10/100 Ethernet MAC and optional hardware encryption to ensure the application can be connected and protected. In addition, the MCF5271 family features an enhanced multiply accumulate unit (eMAC), large on-chip memory (64 Kbytes SRAM, 8 Kbytes configurable cache), and a 32-bit SDR SDRAM memory controller. © Freescale Semiconductor, Inc., 2009. All rights reserved. Contents 1 2 3 4 5 6 7 8 9 MCF5271 Family Configurations . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 8 Mechanicals/Pinouts and Part Numbers . . . . . . . . . . . . 12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document Revision History . . . . . . . . . . . . . . . . . . . . . . 39 MCF5271 Family Configurations 1 MCF5271 Family Configurations Table 1. MCF5271 Family Configurations Module ColdFire V2 Core with EMAC and Hardware Divide MCF5270 MCF5271 x x System Clock 150 MHz Performance (Dhrystone/2.1 MIPS) Instruction/Data Cache 8 Kbytes Static RAM (SRAM) 64 Kbytes Interrupt Controllers (INTC) 2 2 Edge Port Module (EPORT) x x External Interface Module (EIM) x x 4-channel Direct-Memory Access (DMA) x x SDRAM Controller x x Fast Ethernet Controller (FEC) x x Hardware Encryption — x Watchdog Timer (WDT) x x Four Periodic Interrupt Timers (PIT) x x 32-bit DMA Timers 4 4 QSPI x x UART(s) 3 3 I2C x x General Purpose I/O Module (GPIO) x x JTAG - IEEE 1149.1 Test Access Port x x Package 2 144 160 QFP, 160 QFP, 196 MAPBGA 196 MAPBGA Block Diagram The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5271. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 2 Freescale Semiconductor Block Diagram SDRAMC QSPI EIM I2C_SDA I2C_SCL CHIP SELECTS (To/From SRAM backdoor) UnTXD UnRXD UnRTS EBI INTC0 Arbiter UnCTS INTC1 DTnOUT UART 0 UART 1 UART 2 I2 C QSPI SDRAMC PADI – Pin Muxing (To/From PADI) FAST ETHERNET CONTROLLER (FEC) DTnIN FEC D[31:0] (To/From PADI) 4 CH DMA DTIM 0 DTIM 1 DTIM 2 A[23:0] DTIM 3 R/W CS[3:0] (To/From PADI) TA TSIZ[1:0] JTAG_EN BDM MUX DREQ[2:0] DACK[2:0] TEA V2 ColdFire CPU DIV BS[3:0] EMAC JTAG TAP 64 Kbytes SRAM (8Kx16)x4 Watchdog Timer MDHA PORTS (GPIO) CIM (To/From Arbiter) SKHA RNGA 8 Kbytes CACHE (1Kx32)x2 PLL CLKGEN PIT0 PIT1 PIT2 PIT3 (To/From INTC) Edge Port Cryptography Modules Figure 1. MCF5271 Block Diagram MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 3 Features 3 Features For a detailed feature list see the MCF5271 Reference Manual (MCF5271RM). 4 Signal Descriptions This section describes signals that connect off chip, including a table of signal properties. For a more detailed discussion of the MCF5271 signals, consult the MCF5271 Reference Manual (MCF5271RM). 4.1 Signal Properties Table 4 lists all of the signals grouped by function. The “Dir” column is the direction for the primary function of the pin. Refer to Section 6, “Mechanicals/Pinouts and Part Numbers,” for package diagrams. NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality. Table 2. MCF5270 and MCF5271 Signal Information and Muxing Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA Reset RESET — — — I 83 N13 RSTOUT — — — O 82 P13 Clock EXTAL — — — I 86 M14 XTAL — — — O 85 N14 CLKOUT — — — O 89 K14 Mode Selection CLKMOD[1:0] — — — I 20,21 G5,H5 RCON — — — I 79 K10 126, 125, 124 B11, C11, D11 External Memory Interface and Ports A[23:21] PADDR[7:5] CS[6:4] — O MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 4 Freescale Semiconductor Signal Descriptions Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued) Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA Signal Name GPIO A[20:0] — — — O D[31:16] — — — O 22:30, 33:39 G1, G2, H1, H2, H3, H4, J1, J2, J3, J4, K1, K2, K3, K4, L1, L2 D[15:8] PDATAH[7:0] — — O 42:49 M1, N1, M2, N2, P2, L3, M3, N3 D[7:0] PDATAL[7:0] — — O 50:52, 56:60 P3, M4, N4, P4, L5, M5, N5, P5 BS[3:0] PBS[7:4] CAS[3:0] — O 143:140 B6, C6, D7, C7 OE PBUSCTL7 — — O 62 N6 TA PBUSCTL6 — — I 96 H11 TEA PBUSCTL5 DREQ1 — I — J14 R/W PBUSCTL4 — — O 95 J13 TSIZ1 PBUSCTL3 DACK1 — O — P6 TSIZ0 PBUSCTL2 DACK0 — O — P7 TS PBUSCTL1 DACK2 — O 97 H13 TIP PBUSCTL0 DREQ0 — O — H12 123:115, A12, B12, C12, 112:106, 102:98 A13, B13, B14, C13, C14, D12, D13, D14, E11, E12, E13, E14, F12, F13, F14, G11, G12, G13 Chip Selects CS[7:4] PCS[7:4] — — O — B9, A10, C10, A11 CS[3:2] PCS[3:2] SD_CS[1:0] — O 132,131 A9, C9 CS1 PCS1 — — O 130 B10 CS0 — — — O 129 D10 SDRAM Controller SD_WE PSDRAM5 — — O 92 K13 SD_SCAS PSDRAM4 — — O 91 K12 SD_SRAS PSDRAM3 — — O 90 K11 SD_CKE PSDRAM2 — — O — E8 — — O — L12, L13 SD_CS[1:0] PSDRAM[1:0] MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 5 Signal Descriptions Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA External Interrupts Port IRQ[7:3] PIRQ[7:3] — — I IRQ7=63 IRQ4=64 N7, M7, L7, P8, N8 IRQ2 PIRQ2 DREQ2 — I — M8 IRQ1 PIRQ1 — — I 65 L8 FEC EMDC PFECI2C3 I2C_SCL U2TXD O 151 D4 EMDIO PFECI2C2 I2C_SDA U2RXD I/O 150 D5 ECOL — — — I 9 E2 ECRS — — — I 8 E1 ERXCLK — — — I 7 D1 ERXDV — — — I 6 D2 ERXD[3:0] — — — I 5:2 D3, C1, C2, B1 ERXER — — — O 159 B2 ETXCLK — — — I 158 A2 ETXEN — — — I 157 C3 ETXER — — — O 156 B3 ETXD[3:0] — — — O 155:152 A3, A4, C4, B4 I2C I2C_SDA PFECI2C1 — — I/O — J12 I2C_SCL PFECI2C0 — — I/O — J11 — — DMA DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1, TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2, TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0. QSPI QSPI_CS1 PQSPI4 SD_CKE — O 139 B7 QSPI_CS0 PQSPI3 — — O 146 A6 QSPI_CLK PQSPI2 I2C_SCL — O 147 C5 QSPI_DIN PQSPI1 I2C_SDA — I 148 B5 QSPI_DOUT PQSPI0 — — O 149 A5 MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 6 Freescale Semiconductor Signal Descriptions Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA UARTs U2TXD PUARTH1 — — O — A8 U2RXD PUARTH0 — — I — A7 U1CTS PUARTL7 U2CTS — I 136 B8 U1RTS PUARTL6 U2RTS — O 135 C8 U1TXD PUARTL5 — — O 133 D9 U1RXD PUARTL4 — — I 134 D8 U0CTS PUARTL3 — — I 12 F3 U0RTS PUARTL2 — — O 15 G3 U0TXD PUARTL1 — — O 14 F1 U0RXD PUARTL0 — — I 13 F2 DMA Timers DT3IN PTIMER7 U2CTS QSPI_CS2 I — H14 DT3OUT PTIMER6 U2RTS QSPI_CS3 O — G14 DT2IN PTIMER5 DREQ2 DT2OUT I 66 M9 DT2OUT PTIMER4 DACK2 — O — L9 DT1IN PTIMER3 DREQ1 DT1OUT I 61 L6 DT1OUT PTIMER2 DACK1 — O — M6 DT0IN PTIMER1 DREQ0 — I 10 E4 DT0OUT PTIMER0 DACK0 — O 11 F4 BDM/JTAG2 DSCLK — TRST — O 70 N9 PSTCLK — TCLK — O 68 P9 BKPT — TMS — O 71 P10 DSI — TDI — I 73 M10 DSO — TDO — O 72 N10 JTAG_EN — — — I 78 K9 DDATA[3:0] — — — O — M12, N12, P12, L11 PST[3:0] — — — O 77:74 M11, N11, P11, L10 MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 7 Design Recommendations Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA F5 Test TEST — — — I 19 PLL_TEST — — — I — Power Supplies VDDPLL — — — I 87 M13 VSSPLL — — — I 84 L14 OVDD — — — I 1, 18, 32, 41, 55, E5, E7, E10, F7, 69, 81, 94, 105, F9, G6, G8, H7, 114, 128, 138, H8, H9, J6, J8, 145 J10, K5, K6, K8 VSS — — — I 17, 31, 40, 54, A1, A14, E6, E9, 67, 80, 88, 93, F6, F8, F10, G7, 104, 113, 127, G9, H6, J5, J7, 137, 144, 160 J9, K7, P1, P14 VDD — — — I 16, 53, 103 D6, F11, G4, L4 1 Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL, PBUSCTL[4:0], PADDR, PBS, PSDRAM. 2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 5 Design Recommendations 5.1 Layout • • • 5.2 • Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5271. See application note AN1259, System Design and Layout Techniques for Noise Reduction in Processor-Based Systems. Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing. Power Supply 33 μF, 0.1 μF, and 0.01 μF across each power supply MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 8 Freescale Semiconductor Design Recommendations 5.2.1 Supply Voltage Sequencing and Separation Cautions DC Power Supply Voltage Figure 2 shows situations in sequencing the I/O VDD (OVDD), PLL VDD (VDDPLL), and Core VDD (VDD). OVDD is specified relative to VDD. OVDD, VDDPLL 3.3V Supplies Stable 2.5V 1.5V VDD 1 2 0 Time Notes: 1. VDD should not exceed OVDD or VDDPLL by more than 0.4 V at any time, including power-up. 2. Recommended that VDD should track OVDD/VDDPLL up to 0.9 V, then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (OVDD, VDD, or VDDPLL) by more than 0.5 V at any time, including during power-up. 4. Use 1 ms or slower rise time for all supplies. Figure 2. Supply Voltage Sequencing and Separation Cautions 184.108.40.206 Power Up Sequence If OVDD is powered up with VDD at 0 V, then the sense circuits in the I/O pads cause all pad output drivers connected to the OVDD to be in a high impedance state. There is no limit on how long after OVDD powers up before VDD must power up. VDD should not lead the OVDD or VDDPLL by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 μs to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. Use 1 ms or slower rise time for all supplies. 2. VDD and OVDD/VDDPLL should track up to 0.9 V, then separate for the completion of ramps with OVDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. 220.127.116.11 Power Down Sequence If VDD is powered down first, then sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after VDD powers down before OVDD/VDDPLL must power down. VDD should not lag OVDD or VDDPLL going low by more than 0.4 V during power down or there MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 9 Design Recommendations will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop VDD to 0 V. 2. Drop OVDD/VDDPLL supplies. 5.3 • • Decoupling Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package. 0.1 μF and 0.01 μF at each supply input 5.4 • Buffering Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses when excessive loading is expected. See Section 7, “Electrical Characteristics.” 5.5 • Pull-up Recommendations Use external pull-up resistors on unused inputs. See pin table. 5.6 • • • • • • • • Clocking Recommendations Use a multi-layer board with a separate ground plane. Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible. Do not run a high frequency trace around crystal circuit. Ensure that the ground for the bypass capacitors is connected to a solid ground trace. Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal. Tie the ground pin to the most solid ground in the system. Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. Tie XTAL to ground when an external oscillator is clocking the device. 5.7 5.7.1 18.104.22.168 Interface Recommendations SDRAM Controller SDRAM Controller Signals in Synchronous Mode Table 3 shows the behavior of SDRAM signals in synchronous mode. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 10 Freescale Semiconductor Design Recommendations Table 3. Synchronous DRAM Signal Connections Signal Description SD_SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals. SD_SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM. DRAMW DRAM read/write. Asserted for write operations and negated for read operations. SD_CS[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF5271. One SD_CS signal selects one SDRAM block and connects to the corresponding CS signals. SD_CKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality. BS[3:0] Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. CLKOUT Bus clock output. Connects to the CLK input of SDRAMs. 22.214.171.124 Address Multiplexing See the SDRAM controller module chapter in the MCF5271 Reference Manual for details on address multiplexing. 5.7.2 Ethernet PHY Transceiver Connection The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Table 4. Table 4. MII Mode Signal Description MCF5271 Pin Transmit clock ETXCLK Transmit enable ETXEN Transmit data ETXD[3:0] Transmit error ETXER Collision ECOL Carrier sense ECRS Receive clock ERXCLK Receive enable ERXDV Receive data ERXD[3:0] MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 11 Mechanicals/Pinouts and Part Numbers Table 4. MII Mode (continued) Signal Description MCF5271 Pin Receive error ERXER Management channel clock EMDC Management channel serial data EMDIO The serial mode interface operates in what is generally referred to as AMD mode. The MCF5271 configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5. Table 5. Seven-Wire Mode Configuration Signal Description MCF5271 Pin Transmit clock ETXCLK Transmit enable ETXEN Transmit data ETXD Collision ECOL Receive clock ERXCLK Receive enable ERXDV Receive data ERXD Unused, configure as PB14 ERXER Unused input, tie to ground ECRS Unused, configure as PB[13:11] ERXD[3:1] Unused output, ignore ETXER Unused, configure as PB[10:8] ETXD[3:1] Unused, configure as PB15 EMDC Input after reset, connect to ground EMDIO Refer to the M5271EVB evaluation board user’s manual for an example of how to connect an external PHY. Schematics for this board are accessible at the MCF5271 site by navigating to: http://www.freescale.com/coldfire. 5.7.3 BDM Use the BDM interface as shown in the M5271EVB evaluation board user’s manual. The schematics for this board are accessible at the Freescale website at: http://www.freescale.com/coldfire. 6 Mechanicals/Pinouts and Part Numbers This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5271 devices. See Table 4 for a list the signal names and pin locations for each device. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 12 Freescale Semiconductor Mechanicals/Pinouts and Part Numbers 6.1 Pinout—196 MAPBGA The following figure shows a pinout of the MCF5270/71CVMxxx package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A VSS ETXCLK ETXD3 ETXD2 QSPI_ DOUT QSPI_CS0 U2RXD U2TXD CS3 CS6 CS4 A20 A17 VSS A B ERXD0 ERXER ETXER ETXD0 QSPI_DIN BS3 QSPI_CS1 U1CTS CS7 CS1 A23 A19 A16 A15 B C ERXD2 ERXD1 ETXEN ETXD1 QSCK BS2 BS0 RTS1 CS2 CS5 A22 A18 A14 A13 C D ERXCLK ERXDV ERXD3 EMDC EMDIO Core VDD_4 BS1 U1RXD1 U1TXD CS0 A21 A12 A11 A10 D E ECRS ECOL NC TIN0 VDD VSS VDD SD_CKE VSS VDD A9 A8 A7 A6 E F U0TXD U0RXD U0CTS DTOUT0 TEST VSS VDD VSS VDD VSS Core VDD_3 A5 A4 A3 F G D31 D30 U0RTS Core VDD_1 CLK MOD1 VDD VSS VDD VSS NC A2 A1 A0 DTOUT3 G H D29 D28 D27 D26 CLK MOD0 VSS VDD VDD VDD NC TA TIP TS DTIN3 H J D25 D24 D23 D22 VSS VDD VSS VDD VSS VDD I2C_SCL I2C_SDA R/W TEA J K D21 D20 D19 D18 VDD VDD VSS VDD JTAG_EN RCON SD_ RAS SD_ CAS SD_ WE CLKOUT K L D17 D16 D10 Core VDD_2 D3 DTIN1 IRQ5 IRQ1 DTOUT2 PST0 DDATA0 SD_ CS1 SD_ CS0 VSSPLL L M D15 D13 D9 D6 D2 DTOUT1 IRQ6 IRQ2 DTIN2 TDI/DSI PST3 DDATA3 VDDPLL EXTAL M N D14 D12 D8 D5 D1 OE IRQ7 IRQ3 TRST/ DSCLK TDO/DSO PST2 DDATA2 RESET XTAL N P VSS D11 D7 D4 D0 TSIZ1 TSIZ0 IRQ4 TCLK/ PSTCLK TMS/ BKPT PST1 DDATA1 RSTOUT VSS P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Figure 3. MCF5270/71CVMxxx Pinout (196 MAPBGA) MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 13 Mechanicals/Pinouts and Part Numbers 6.2 Package Dimensions—196 MAPBGA Figure 4 shows MCF5270/71CVMxxx package dimensions. X D Y Laser mark for pin 1 identification in this area NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. M K E Millimeters DIM Min Max A 1.25 1.60 A1 0.27 0.47 A2 M b TOL 13X e S 14 13 12 11 10 9 6 5 4 3 2 Metalized mark for pin 1 identification in this area 1 1.16 REF 0.45 0.55 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC A B C 5 D S E 13X e F A 0.20 Z A2 G H J K L M A1 Z 0.10 Z 196X 4 Detail K Rotated 90° Clockwise N P 3 196X b 0.15 Z X Y View M-M 0.08 Z Figure 4. 196 MAPBGA Package Dimensions (Case No. 1128A-01) MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 14 Freescale Semiconductor Mechanicals/Pinouts and Part Numbers 6.3 Pinout—160 QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MCF5271 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A17 A16 A15 A14 A13 A12 O-VDD VSS A11 A10 A9 A8 A7 A6 A5 O-VDD VSS Core_Vdd_3 A4 A3 A2 A1 A0 TS TA R/W O-VDD VSS SD_WE SD_SCAS SD_SRAS CLKOUT VSS VDDPLL EXTAL XTAL VSSPLL RESET RSTOUT O-VDD O-VDD DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 Core Vdd_2 VSS O-VDD DATA4 DATA3 DATA2 DATA1 DATA0 DTIN1 OE IRQ7 IRQ4 IRQ1 DTIN2 VSS TCLK\PSTCLK O-VDD TRST/DSCLK TMS\BKPT TDO/DSO TDI/DSI PST0 PST1 PST2 PST3 JTAG_EN RCON VSS 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 O-VDD ERXD0 ERXD1 ERXD2 ERXD3 ERXDV ERXCLK ECRS ECOL U0TIN U0TOUT U0CTS U0RXD U0TXD U0RTS Core VDD_1 VSS O-VDD TEST CLKMOD1 CLKMOD0 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 VSS O-VDD DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 VSS 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VSS ERXER ETXCLK ETXEN ETXER ETXD3 ETXD2 ETXD1 ETXD0 EMDC EMDIO QSPI_DOUT QSPI_DIN QSPI_CLK QSPI_CS0 O-VDD VSS BS3 BS2 BS1 BS0 QSPI_CS1/SD_CKE O-VDD VSS U1CTS U1RTS U1RXD U1TXD CS3 CS2 CS1 CS0 O-VDD VSS A23 A18 A21 A20 A19 A18 Figure 5 shows a pinout of the MCF5271CABxxx package. Figure 5. MCF5270/71CABxxx Pinout (160 QFP) MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 15 Mechanicals/Pinouts and Part Numbers 6.4 Package Dimensions—160 QFP Figure 6 shows MCF5270/71CAB80 package dimensions. L B H V B 0.20 (0.008) M A-B H 0.20 (0.008) B M L 0.20 (0.008) –B– –A– –A–, –B–, –D– A-B S A-B S D S D S Y P DETAIL A G DETAIL A Z A 0.20 (0.008) M C 0.20 (0.008) S A-B BASE METAL D S A-B N S 0.20 (0.008) M C A-B S J D S F DETAIL C D 0.13 (0.005) M –H– C A-B S D S SECTION B–B M × TOP & BOTTOM U× C E NOTES T –H– R Q× W –C– K H X 0.110 (0.004) DETAIL C 1. DIMENSIONING AND TOLERINCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLAN -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MILLIMETERS DIM MIN MAX A 27.90 28.10 27.90 28.10 B 3.35 3.85 C D 0.22 0.38 3.20 3.50 E 0.22 0.33 F 0.65 BSC G H 0.25 0.35 J 0.11 0.23 K 0.70 0.90 25.35 BSC L 16° M 5° 0.11 0.19 N 0.325 BSC P ° Q 7° 0 R 0.13 0.30 S 31.00 31.40 0.13 — T U — 0° V 31.00 31.40 0.4 — W 1.60 REF X Y 1.33 REF 1.33 REF Z INCHES MIN MAX 1.098 1.106 1.098 1.106 0.132 1.106 0.009 0.015 0.126 0.138 0.009 0.013 0.026 REF 0.010 0.014 0.004 0.009 0.028 0.035 0.998 REF 5° 16° 0.004 0.007 0.013 REF 0° 7° 0.005 0.012 1.220 1.236 0.005 — 0° — 1.220 1.236 0.016 — 0.063 REF 0.052 REF 0.052 REF Case 864A-03 Figure 6. 160 QFP Package Dimensions MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 16 Freescale Semiconductor Electrical Characteristics 6.5 Ordering Information Table 6. Orderable Part Numbers Freescale Part Number Description Package Speed Lead-Free? Temperature MCF5270AB100 MCF5270 RISC Microprocessor 160 QFP 100MHz Yes 0° to +70° C MCF5270CAB100 MCF5270 RISC Microprocessor 160 QFP 100MHz Yes -40° to +85° C MCF5270VM100 MCF5270 RISC Microprocessor 196 MAPBGA 100MHz Yes 0° to +70° C MCF5270CVM150 MCF5270 RISC Microprocessor 196 MAPBGA 150MHz Yes -40° to +85° C MCF5271CAB100 MCF5271 RISC Microprocessor 160 QFP 100MHz Yes -40° to +85° C MCF5271CVM100 MCF5271 RISC Microprocessor 196 MAPBGA 100MHz Yes -40° to +85° C MCF5271CVM150 MCF5271 RISC Microprocessor 196 MAPBGA 150MHz Yes -40° to +85° C 7 Electrical Characteristics This chapter contains electrical specification tables and reference timing diagrams for the MCF5271 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5271. NOTE The parameters specified in this processor document supersede any values found in the module specifications. 7.1 Maximum Ratings Table 7. Absolute Maximum Ratings1, 2 Rating Symbol Value Unit Core Supply Voltage VDD – 0.5 to +2.0 V Pad Supply Voltage OVDD – 0.3 to +4.0 V VDDPLL – 0.3 to +4.0 V VIN – 0.3 to + 4.0 V ID 25 mA TA (TL - TH) – 40 to 85 °C Tstg – 65 to 150 °C PLL Supply Voltage Digital Input Voltage 3 Instantaneous Maximum Current Single pin limit (applies to all pins) 3,4,5 Operating Temperature Range (Packaged) Storage Temperature Range 1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 17 Electrical Characteristics 2 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or OVDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to VSS and OVDD. 5 Power supply must maintain regulation within operating OVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > OVDD) is greater than IDD, the injection current may flow out of OVDD and could result in external power supply going out of regulation. Insure external OVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power (ex; no clock).Power supply must maintain regulation within operating OVDD range during instantaneous and operating maximum current conditions. 7.2 Thermal Characteristics The below table lists thermal resistance values. Table 8. Thermal Characteristics Characteristic 2 4 5 Unit θJMA 321,2 401,2 °C/ W Four layer board (2s2p) θJMA 291,2 361,2 °C/ W Junction to board θJB 203 253 °C/ W Junction to case θJC 104 104 °C/ W Junction to top of package Ψjt 21,5 21,5 °C/ W Maximum operating junction temperature Tj 104 105 oC Junction to ambient (@200 ft/min) 3 196 160QFP MAPBGA Four layer board (2s2p) Junction to ambient, natural convection 1 Symbol θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Motorola recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D × Θ JMA ) (1) Where: MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 18 Freescale Semiconductor Electrical Characteristics TA= Ambient Temperature, °C ΘJMA= Package Thermal Resistance, Junction-to-Ambient, °C/W PD= PINT + PI/O PINT= IDD × VDD, Watts - Chip Internal Power PI/O= Power Dissipation on Input and Output Pins — User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K ÷ ( T J + 273°C ) (2) Solving equations 1 and 2 for K gives: K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 7.3 DC Electrical Specifications Table 9. DC Electrical Specifications1 Characteristic Symbol Min Typical Max Unit Core Supply Voltage VDD 1.4 — 1.6 V Pad Supply Voltage OVDD 3.0 — 3.6 V PLL Supply Voltage VDDPLL 3.0 — 3.6 V Input High Voltage VIH 0.7 × OVDD — 3.65 V Input Low Voltage VIL VSS – 0.3 — 0.35 × OVDD V VHYS 0.06 × OVDD — — mV Input Leakage Current Vin = VDD or VSS, Input-only pins Iin –1.0 — 1.0 μA High Impedance (Off-State) Leakage Current Vin = VDD or VSS, All input/output and output pins IOZ –1.0 — 1.0 μA Output High Voltage (All input/output and all output pins) IOH = –5.0 mA VOH OVDD - 0.5 — — V Output Low Voltage (All input/output and all output pins) IOL = 5.0mA VOL — — 0.5 V Weak Internal Pull Up Device Current, tested at VIL Max.2 IAPU –10 — – 130 μA Input Capacitance 3 All input-only pins All input/output (three-state) pins Cin Input Hysteresis — — — pF 7 7 MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 19 Electrical Characteristics Table 9. DC Electrical Specifications1 (continued) Characteristic Symbol Load Capacitance4 Low drive strength High drive strength CL Core Operating Supply Current 5 Master Mode IDD Pad Operating Supply Current Master Mode Low Power Modes 2 3 4 5 6 7 8 Typical Max Unit — — 25 50 pF pF — 135 150 mA — — 100 TBD — — mA μA 1.0 10 mA mA OIDD DC Injection Current 3, 6, 7, 8 VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3 Single Pin Limit Total processor Limit, Includes sum of all stressed pins 1 Min IIC –1.0 –10 Refer to Table 10 for additional PLL specifications. Refer to the MCF5271 signals section for pins having weak internal pull-up devices. This parameter is characterized before qualification rather than 100% tested. pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. See High Speed Signal Propagation: Advanced Black Magic by Howard W. Johnson for design guidelines. Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. All functional non-supply pins are internally clamped to VSS and their respective VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock. 7.4 Oscillator and PLLMRFM Electrical Characteristics Table 10. HiP7 PLLMRFM Electrical Specifications1 Num 1 2 3 Characteristic PLL Reference Frequency Range Crystal reference External reference 1:1 mode (NOTE: fsys/2 = 2 × fref_1:1) Core frequency CLKOUT Frequency 2 External reference On-Chip PLL Frequency Self Clocked Mode Frequency 5 Crystal Start-up Time 5, 6 Min. Value Max. Value fref_crystal fref_ext fref_1:1 8 8 24 25 25 75 fsys/2 0 fref ÷ 32 150 75 75 MHz MHz MHz 4, 5 fLOR 100 1000 kHz fSCM 10.25 15.25 MHz tcst — 10 ms Unit MHz fsys Loss of Reference Frequency 3, 5 4 Symbol MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 20 Freescale Semiconductor Electrical Characteristics Table 10. HiP7 PLLMRFM Electrical Specifications1 (continued) Num 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Characteristic Symbol XTAL Load Capacitance5 5, 7,13 Min. Value Max. Value Unit 5 30 pF — 750 μs — — 11 750 ms μs 7 PLL Lock Time 8 Power-up To Lock Time 5, 6,8 With Crystal Reference (includes 5 time) Without Crystal Reference9 tlplk 9 1:1 Mode Clock Skew (between CLKOUT and EXTAL) 10 tskew –1 1 ns 10 Duty Cycle of reference 5 tdc 40 60 % 11 Frequency un-LOCK Range fUL –3.8 4.1 % fsys/2 12 Frequency LOCK Range fLCK –1.7 2.0 % fsys/2 13 CLKOUT Period Jitter, 5, 6, 8,11, 12 Measured at fsys/2 Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Cjitter — — 5.0 .01 % fsys/2 14 Frequency Modulation Range Limit13,14 (fsys/2 Max must not be exceeded) Cmod 0.8 2.2 %fsys/2 15 ICO Frequency. fico = fref × 2 × (MFD+2) 15 fico 48 150 MHz tlpll All values given are initial design targets and subject to change. All internal registers retain data at 0 Hz. “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings. This parameter is guaranteed by characterization before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time. tlpll = (64 * 4 * 5 + 5 τ) Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10-6 2(MFD + 2). PLL is operating in 1:1 PLL mode. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz. Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation range determined by hardware design. fsys/2 = fico / (2 * 2RFD) MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 21 Electrical Characteristics 7.5 External Interface Timing Characteristics Table 11 lists processor bus input timings. NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values. Table 11. Processor Bus Input Timing Specifications Characteristic1 Name freq System bus frequency B0 CLKOUT period Symbol Min Max Unit fsys/2 50 75 MHz tcyc — 1/75 ns Control Inputs B1a Control input valid to CLKOUT high2 tCVCH 9 — ns B1b BKPT valid to CLKOUT high3 tBKVCH 9 — ns B2a CLKOUT high to control inputs invalid2 tCHCII 0 — ns tBKNCH 0 — ns B2b CLKOUT high to asynchronous control input BKPT invalid3 Data Inputs B4 Data input (D[31:0]) valid to CLKOUT high tDIVCH 4 — ns B5 CLKOUT high to data input (D[31:0]) invalid tCHDII 0 — ns 1 Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line environment.. 2 TEA and TA pins are being referred to as control inputs. 3 Refer to figure A-19. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 22 Freescale Semiconductor Electrical Characteristics Timings listed in Table 11 are shown in Figure 7. * The timings are also valid for inputs sampled on the negative clock edge. 1.5V CLKOUT(75MHz) TSETUP THOLD Input Setup And Hold Invalid 1.5V Valid 1.5V Invalid trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time CLKOUT Vh = VIH Vl = VIL B4 B5 Inputs Figure 7. General Input Timing Requirements 7.6 Processor Bus Output Timing Specifications Table 12 lists processor bus output timings. Table 12. External Bus Output Timing Specifications Name Characteristic Symbol Min Max Unit Control Outputs B6a CLKOUT high to chip selects valid 1 tCHCV — 0.5tCYC +5 ns B6b CLKOUT high to byte enables (BS[3:0]) valid2 tCHBV — 0.5tCYC +5 ns B6c CLKOUT high to output enable (OE) valid3 tCHOV — 0.5tCYC +5 ns B7 CLKOUT high to control output (BS[3:0], OE) invalid tCHCOI 0.5tCYC+1.5 — ns B7a CLKOUT high to chip selects invalid tCHCI 0.5tCYC+1.5 — ns MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 23 Electrical Characteristics Table 12. External Bus Output Timing Specifications (continued) Name Characteristic Symbol Min Max Unit Address and Attribute Outputs B8 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid tCHAV — 9 ns B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid tCHAI 1.5 — ns Data Outputs 1 2 3 B11 CLKOUT high to data output (D[31:0]) valid tCHDOV — 9 ns B12 CLKOUT high to data output (D[31:0]) invalid tCHDOI 1.5 — ns B13 CLKOUT high to data output (D[31:0]) high impedance tCHDOZ — 9 ns CS transitions after the falling edge of CLKOUT. BS transitions after the falling edge of CLKOUT. OE transitions after the falling edge of CLKOUT. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 24 Freescale Semiconductor Electrical Characteristics Read/write bus timings listed in Table 12 are shown in Figure 8, Figure 9, and Figure 10. S1 S0 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKOUT B7a B7a CSn B6a B6a B8 B8 B9 A[23:0] TSIZ[1:0] B8 B9 TS B9 B8 B9 TIP B8 B6c B0 B7 OE B9 R/W (H) B8 B6b B6b BS[3:0] B7 B7 B11 B4 B12 D[31:0] B5 B13 TA (H) TEA (H) Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 25 Electrical Characteristics Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 12. S0 S1 S2 S3 S4 S5 S0 S1 CLKOUT B6a B7a CSn B8 B9 A[23:0] TSIZ[1:0] B8 B9 TS B8 B9 TIP B6c OE B7 R/W (H) B6b B7 BS[3:0] B5 B4 D[31:0] B2a TA B1a TEA (H) Figure 9. SRAM Read Bus Cycle Terminated by TA MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 26 Freescale Semiconductor Electrical Characteristics Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 12. S0 S1 S2 S3 S4 S5 S0 S1 CLKOUT B6a B7a CSn B8 B9 A[23:0] TSIZ[1:0] B8 B9 TS B8 TIP B9 B6c B7 OE R/W (H) B6b B7 BS[3:0] D[31:0] TA (H) B1a TEA B2a Figure 10. SRAM Read Bus Cycle Terminated by TEA MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 27 Electrical Characteristics Figure 11 shows an SDRAM read cycle. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SD_CKE D3 D1 A[23:0] Row Column D2 D4 D4 SD_SRAS D2 SD_CAS1 D4 D2 D4 SDWE D5 D[31:0] D6 D2 RAS[1:0] CAS[3:0] ACTV 1 NOP READ NOP NOP PALL DACR[CASL] = 2 Figure 11. SDRAM Read Cycle Table 13. SDRAM Timing NUM 1 Characteristic Symbol Min Max Unit D1 CLKOUT high to SDRAM address valid tCHDAV — 9 ns D2 CLKOUT high to SDRAM control valid tCHDCV — 9 ns D3 CLKOUT high to SDRAM address invalid tCHDAI 1.5 — ns D4 CLKOUT high to SDRAM control invalid tCHDCI 1.5 — ns D5 SDRAM data valid to CLKOUT high tDDVCH 4 — ns D6 CLKOUT high to SDRAM data invalid tCHDDI 1.5 — ns D71 CLKOUT high to SDRAM data valid tCHDDVW — 9 ns D81 CLKOUT high to SDRAM data invalid tCHDDIW 1.5 — ns D7 and D8 are for write cycles only. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 28 Freescale Semiconductor Electrical Characteristics Figure 12 shows an SDRAM write cycle. 0 1 2 3 4 5 6 7 8 9 10 11 12 SD_CKE D3 D1 Row A[23:0] Column D4 D2 SD_SRAS D2 SD_SCAS1 D4 SD_WE D7 D[31:0] D2 D8 RAS[1:0] D4 D2 CAS[3:0] ACTV 1 DACR[CASL] NOP WRITE NOP PALL =2 Figure 12. SDRAM Write Cycle 7.7 General Purpose I/O Timing Table 14. GPIO Timing1 NUM 1 Characteristic Symbol Min Max Unit G1 CLKOUT High to GPIO Output Valid tCHPOV — 10 ns G2 CLKOUT High to GPIO Output Invalid tCHPOI 1.5 — ns G3 GPIO Input Valid to CLKOUT High tPVCH 9 — ns G4 CLKOUT High to GPIO Input Invalid tCHPI 1.5 — ns GPIO pins include: INT, UART, Timer, DREQn and DACKn pins. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 29 Electrical Characteristics CLKOUT G2 G1 GPIO Outputs G3 G4 GPIO Inputs Figure 13. GPIO Timing 7.8 Reset and Configuration Override Timing Table 15. Reset and Configuration Override Timing (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1 NUM 1 2 Characteristic Symbol Min Max Unit R1 RESET Input valid to CLKOUT High tRVCH 9 — ns R2 CLKOUT High to RESET Input invalid tCHRI 1.5 — ns tRIVT 5 — tCYC 2 R3 RESET Input valid Time R4 CLKOUT High to RSTOUT Valid tCHROV — 10 ns R5 RSTOUT valid to Config. Overrides valid tROVCV 0 — ns R6 Configuration Override Setup Time to RSTOUT invalid tCOS 20 — tCYC R7 Configuration Override Hold Time after RSTOUT invalid tCOH 0 — ns R8 RSTOUT invalid to Configuration Override High Impedance tROICZ — 1 tCYC All AC timing is shown with respect to 50% VDD levels unless otherwise noted. During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. CLKOUT R1 R2 R3 RESET R4 R4 RSTOUT R8 R5 R6 R7 Configuration Overrides*: (RCON, Override pins]) Figure 14. RESET and Configuration Override Timing Refer to the chip configuration module (CCM) chapter in the device’s reference manual for more information. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 30 Freescale Semiconductor Electrical Characteristics I2C Input/Output Timing Specifications 7.9 Table 16 lists specifications for the I2C input timing parameters shown in Figure 15. Table 16. I2C Input Timing Specifications between I2C_SCL and I2C_SDA Num Characteristic Min Max Units I1 Start condition hold time 2 — tcyc I2 Clock low period 8 — tcyc I3 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 ms I4 Data hold time 0 — ns I5 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 1 ms I6 Clock high time 4 — tcyc I7 Data setup time 0 — ns I8 Start condition setup time (for repeated start condition only) 2 — tcyc I9 Stop condition setup time 2 — tcyc Table 17 lists specifications for the I2C output timing parameters shown in Figure 15. Table 17. I2C Output Timing Specifications between I2C_SCL and I2C_SDA Num Characteristic Min Max Units I11 Start condition hold time 6 — tcyc I2 1 Clock low period 10 — tcyc I3 2 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — — µs I4 1 Data hold time 7 — tcyc I5 3 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 3 ns I6 1 Clock high time 10 — tcyc I7 1 Data setup time 2 — tcyc I8 1 Start condition setup time (for repeated start condition only) 20 — tcyc I9 1 Stop condition setup time 10 — tcyc 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 17 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 15 shows timing for the values in Table 16 and Table 17. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 31 Electrical Characteristics I2 I6 I5 I2C_SCL I1 I4 I3 I8 I9 I7 I2C_SDA Figure 15. I2C Input/Output Timings 7.10 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 7.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK) The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the ERXCLK frequency. Table 18 lists MII receive channel timings. Table 18. MII Receive Signal Timing Num Characteristic Min Max Unit M1 ERXD[3:0], ERXDV, ERXER to ERXCLK setup 5 — ns M2 ERXCLK to ERXD[3:0], ERXDV, ERXER hold 5 — ns M3 ERXCLK pulse width high 35% 65% ERXCLK period M4 ERXCLK pulse width low 35% 65% ERXCLK period Figure 16 shows MII receive signal timings listed in Table 18. M3 ERXCLK (input) M4 ERXD[3:0] (inputs) ERXDV ERXER M1 M2 Figure 16. MII Receive Signal Timing Diagram MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 32 Freescale Semiconductor Electrical Characteristics 7.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK) Table 19 lists MII transmit channel timings. The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the ETXCLK frequency. Table 19. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 ETXCLK to ETXD[3:0], ETXEN, ETXER invalid 5 — ns M6 ETXCLK to ETXD[3:0], ETXEN, ETXER valid — 25 ns M7 ETXCLK pulse width high 35% 65% ETXCLK period M8 ETXCLK pulse width low 35% 65% ETXCLK period Figure 17 shows MII transmit signal timings listed in Table 19. M7 ETXCLK (input) M5 M8 ETXD[3:0] (outputs) ETXEN ETXER M6 Figure 17. MII Transmit Signal Timing Diagram 7.10.3 MII Async Inputs Signal Timing (ECRS and ECOL) Table 20 lists MII asynchronous inputs signal timing. Table 20. MII Async Inputs Signal Timing Num M9 Characteristic Min Max Unit 1.5 — ETXCLK period ECRS, ECOL minimum pulse width Figure 18 shows MII asynchronous input timings listed in Table 20. ECRS, ECOL M9 Figure 18. MII Async Inputs Timing Diagram MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 33 Electrical Characteristics 7.10.4 MII Serial Management Channel Timing (EMDIO and EMDC) Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 21. MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 EMDC falling edge to EMDIO output invalid (minimum propagation delay) 0 — ns M11 EMDC falling edge to EMDIO output valid (max prop delay) — 25 ns M12 EMDIO (input) to EMDC rising edge setup 10 — ns M13 EMDIO (input) to EMDC rising edge hold 0 — ns M14 EMDC pulse width high 40% 60% MDC period M15 EMDC pulse width low 40% 60% MDC period Figure 19 shows MII serial management channel timings listed in Table 21. M14 M15 EMDC (output) M10 EMDIO (output) M11 EMDIO (input) M12 M13 Figure 19. MII Serial Management Channel Timing Diagram MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 34 Freescale Semiconductor Electrical Characteristics 7.11 32-Bit Timer Module AC Timing Specifications Table 22 lists timer module AC timings. Table 22. Timer Module AC Timing Specifications 0–66 MHz Name Characteristic Unit Min Max T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — tCYC T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — tCYC 7.12 QSPI Electrical Specifications Table 23 lists QSPI timings. Table 23. QSPI Modules AC Timing Specifications Name Characteristic Min Max Unit QS1 QSPI_CS[1:0] to QSPI_CLK 1 510 tcyc QS2 QSPI_CLK high to QSPI_DOUT valid. — 10 ns QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold) 2 — ns QS4 QSPI_DIN to QSPI_CLK (Input setup) 9 — ns QS5 QSPI_DIN to QSPI_CLK (Input hold) 9 — ns The values in Table 23 correspond to Figure 20. QS1 QSPI_CS[1:0] QSPI_CLK QS2 QSPI_DOUT QS3 QS4 QS5 QSPI_DIN Figure 20. QSPI Timing MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 35 Electrical Characteristics 7.13 JTAG and Boundary Scan Timing Table 24. JTAG and Boundary Scan Timing Characteristics1 Num 1 Symbol Min Max Unit J1 TCLK Frequency of Operation fJCYC DC 1/4 fsys/2 J2 TCLK Cycle Period tJCYC 4 — tCYC J3 TCLK Clock Pulse Width tJCW 26 — ns J4 TCLK Rise and Fall Times tJCRF 0 3 ns J5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 4 — ns J6 Boundary Scan Input Data Hold Time after TCLK Rise tBSDHT 26 — ns J7 TCLK Low to Boundary Scan Output Data Valid tBSDV 0 33 ns J8 TCLK Low to Boundary Scan Output High Z tBSDZ 0 33 ns J9 TMS, TDI Input Data Setup Time to TCLK Rise tTAPBST 4 — ns J10 TMS, TDI Input Data Hold Time after TCLK Rise tTAPBHT 10 — ns J11 TCLK Low to TDO Data Valid tTDODV 0 26 ns J12 TCLK Low to TDO High Z tTDODZ 0 8 ns J13 TRST Assert Time tTRSTAT 100 — ns J14 TRST Setup Time (Negation) to TCLK High tTRSTST 10 — ns JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it. J2 J3 J3 VIH TCLK (input) J4 VIL J4 Figure 21. Test Clock Input Timing MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 36 Freescale Semiconductor Electrical Characteristics TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 22. Boundary Scan (JTAG) Timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 23. Test Access Port Timing TCLK J14 TRST J13 Figure 24. TRST Timing MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 37 Electrical Characteristics 7.14 Debug AC Timing Specifications Table 25 lists specifications for the debug AC timing parameters shown in Figure 26. Table 25. Debug AC Timing Specification 150 MHz Num 1 Characteristic Units Min Max DE0 PSTCLK cycle time — 0.5 tcyc DE1 PST valid to PSTCLK high 4 — ns DE2 PSTCLK high to PST invalid 1.5 — ns DE3 DSCLK cycle time 5 — tcyc DE4 DSI valid to DSCLK high 1 — tcyc DE51 DSCLK high to DSO invalid 4 — tcyc DE6 BKPT input data setup time to CLKOUT rise 4 — ns DE7 CLKOUT high to BKPT high Z 0 10 ns DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. Figure 25 shows real-time trace timing for the values in Table 25. PSTCLK DE0 DE1 DE2 PST[3:0] DDATA[3:0] Figure 25. Real-Time Trace AC Timing Figure 26 shows BDM serial port AC timing for the values in Table 25. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 38 Freescale Semiconductor Documentation CLKOUT DE6 BKPT DE7 DE5 DSCLK DE3 Current DSI Next DE4 Past DSO Current Figure 26. BDM Serial Port AC Timing 8 Documentation Documentation regarding the MCF5271 and their development support tools is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale web address at http://www.freescale.com/coldfire. 9 Document Revision History The below table provides a revision history for this document. Table 26. MCF5271EC Revision History Rev. No. Substantive Change(s) 0 Initial release 1 • Fixed several clock values. • Updated Signal List table 1.1 • Removed duplicate information in the module description sections. The information is all in the Signals Description Table. 1.2 • Removed detailed signal description section. This information can be found in the MCF5271RM Chapter 2. • Removed detailed feature list. This information can be found in the MCF5271RM Chapter 1. • Changed instances of Motorola to Freescale • Added values for ‘Maximum operating junction temperature’ in Table 8. • Added typical values for ‘Core operating supply current (master mode)’ in Table 9. • Added typical values for ‘Pad operating supply current (master mode)’ in Table 9. • Removed unnecessary PLL specifications, #6-9, in Table 10. MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 39 Document Revision History Table 26. MCF5271EC Revision History (continued) Rev. No. Substantive Change(s) 1.3 • Device is now available in 150 MHz versions. Updated specs where necessary to reflect this improvement. • Added 2 new part numbers to Table 6: MCF5270CVM150 and MCF5271CVM150. • Removed features list. This information can be found in the MCF5271RM. • Removed SDRAM address multiplexing section. This information can be found in the MCF5271RM. 1.4 • Added Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions.” • Updated 196MAPBGA package dimensions, Figure 4. 2 • • • • • • Table 2: Changed SD_CKE pin location from 139 to “—” for the 160QFP device. Table 2: Changed QSPI_CS1 pin location from “—” to 139 for the 160QFP device. Table 2: Changed DT3IN pin’s alternate 2 function from “—” to QSPI_CS2. Table 2: Changed DT3OUT pin’s alternate 2 function from “—” to QSPI_CS3. Figure 5: Changed pin 139 label from “SD_CKE/QSPI_CS1” to “QSPI_CS1/SD_CKE”. Removed second sentence from Section 7.10.1, “MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK),” and Section 7.10.2, “MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK),” regarding no minimum frequency requirement for TXCLK. • Removed third and fourth paragraphs from Section 7.10.2, “MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK),” as this feature is not supported on this device. 3 • Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions” changed PLLVDD to VDDPLL to match rest of document. • Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions” Changed VDDPLL voltage level from 1.5V to 3.3V throughout section. • Section 126.96.36.199, “Power Up Sequence” first bullet, changed “Use 1 µs” to “Use 1 ms”. • Corrected position of spec D5 in Figure 11. • Figure 3: Corrected M4 ball location from DATA5 to DATA6, changed DATAn labels to Dn for consistency • Table 14: Added DACKn and DREQn to footnote. • Table 9, added PLL supply voltage row 4 • Added part number MCF5270CAB100 in Table 6 MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 40 Freescale Semiconductor Document Revision History MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 41 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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