Freescale Semiconductor Data Sheet: Advance Information MCF5208EC Rev. 2, 12/2008 MCF5208 ColdFire® Microprocessor Data Sheet Supports MCF5207 & MCF5208 by: Microcontroller Division The MCF5207 and MCF5208 devices are highly-integrated, 32-bit microprocessors based on the version 2 ColdFire microarchitecture. Both devices contain a 16-Kbyte internal SRAM, an 8-Kbyte configurable cache, a 2-bank SDR/DDR SDRAM controller, a 16-channel DMA controller, up to three UARTs, a queued SPI, a low-power management modeule, and other peripherals that enable the MCF5207 and MCF5208 for use in industrial control and connectivity applications. The MCF5208 device also features a 10/100 Mbps fast ethernet controller. This document provides detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF5207 and MCF5208 microprocessors. It was written from the perspective of the MCF5208 device. See the following section for a summary of differences between the two devices. © Freescale Semiconductor, Inc., 2008. All rights reserved. Table of Contents 1 2 3 4 5 6 MCF5207/8 Device Configurations......................2 Ordering Information ...........................................2 Signal Descriptions..............................................3 Mechanicals and Pinouts ....................................8 Electrical Characteristics ...................................17 Revision History ................................................43 MCF5207/8 Device Configurations 1 MCF5207/8 Device Configurations The following table compares the two devices described in this document: Table 1. MCF5207 & MCF5208 Configurations Module MCF5207 MCF5208 Version 2 ColdFire Core with EMAC (Enhanced Multiply-Accumulate Unit) • • Core (System) Clock up to 166.67 MHz Peripheral and External Bus Clock (Core clock ÷ 2) up to 83.33 MHz Performance (Dhrystone/2.1 MIPS) up to 159 Instruction/Data Cache 8 Kbytes Static RAM (SRAM) 16 Kbytes SDR/DDR SDRAM Controller • • Fast Ethernet Controller (FEC) — • Low-Power Management Module • • UARTs 3 3 I • • QSPI • • 32-bit DMA Timers 4 4 Watchdog Timer (WDT) • • Periodic Interrupt Timers (PIT) 4 4 Edge Port Module (EPORT) • • Interrupt Controllers (INTC) 1 1 16-channel Direct Memory Access (DMA) • • FlexBus External Interface • • General Purpose I/O Module (GPIO) • • • • 144 LQFP 144 MAPBGA 160 QFP 196 MAPBGA 2C JTAG - IEEE® 1149.1 Test Access Port Package 2 Ordering Information Table 2. Orderable Part Numbers Freescale Part Number Description Speed Temperature MCF5207CAG166 MCF5207 RISC Microprocessor, 144 LQFP 166.67 MHz –40° to +85° C MCF5207CVM166 MCF5207 RISC Microprocessor, 144 MAPBGA 166.67 MHz –40° to +85° C MCF5208CAB166 MCF5208 RISC Microprocessor, 160 QFP 166.67 MHz –40° to +85° C MCF5208CVM166 MCF5208 RISC Microprocessor, 196 MAPBGA 166.67 MHz –40° to +85° C MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 2 Freescale Semiconductor Signal Descriptions 3 Signal Descriptions The following table lists all the MCF5208 pins grouped by function. The Dir column is the direction for the primary function of the pin only. Refer to Section 4, “Mechanicals and Pinouts” for package diagrams. For a more detailed discussion of the MCF5208 signals, consult the MCF5208 Reference Manual (MCF5208RM). NOTE In this table and throughout this document, a single signal within a group is designated without square brackets (i.e., A23), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO default to their GPIO functionality. MCF5207 144 LQFP RESET2 — — — I EVDD 82 J10 90 J14 RSTOUT — — — O EVDD 74 M12 82 N14 Signal Name GPIO Alternate 1 Alternate 2 Dir.1 Voltage Domain Table 3. MCF5207/8 Signal Information and Muxing MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA Reset Clock EXTAL — — — I EVDD 78 K12 86 L14 XTAL — — — O EVDD 80 J12 88 K14 FB_CLK — — — O SDVDD 34 L1 40 N1 Mode Selection RCON2 — — — I EVDD 144 C4 160 C3 DRAMSEL — — — I EVDD 79 H10 87 K11 FlexBus A[23:22] — FB_CS[5:4] — O SDVDD 118, 117 B9, A10 126, 125 B11, A11 A[21:16] — — — O SDVDD 116–114, 112, 108, 107 C9, A11, B10, A12, C11, B11 124, 123, 122, 120, 116, 115 B12, A12, A13, B13, B14, C13 A[15:14] — SD_BA[1:0]3 — O SDVDD 106, 105 B12, C12 114, 113 C14, D12 A[13:11] — SD_A[13:11]3 — O SDVDD 104–102 D11, E10, D12 112, 111, 110 D13, D14, E11 A10 — — — O SDVDD 101 C10 109 E12 MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 3 Signal Descriptions Dir.1 Voltage Domain Table 3. MCF5207/8 Signal Information and Muxing (continued) MCF5207 144 LQFP MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA O SDVDD 100–91 E11, D9, E12, F10, F11, E9, F12, G10, G12, F9 108–99 E13, E14, F11–F14, G11–G14 I/O SDVDD 21–28, 40–47 F1, F2, G1, G2, G4, G3, H1, H2, K3, L2, L3, K2, M3, J4, M4, K4 27–34, 46–53 J4–J1, K4–K1, M3, N3, M4, N4, P4, L5, M5, N5 — I/O SDVDD 8–15, 51–58 B2, B1, C2, C1, D2, D1, E2, E1, L5, K5, L6, J6, M6, J7, L7, K7 16–23, 57–64 F3–F1, G4–G1, H1, N6, P6, L7, M7, N7, P7, N8, P8 SD_DQM[3:0]3 — O SDVDD 20, 48, 18, 50 F4, L4, E3, J5 26, 54, 24, 56 H2, P5, H4, M6 PBUSCTL3 — — O SDVDD 60 J8 66 M8 TA2 PBUSCTL2 — — I SDVDD 90 G11 98 H14 R/W PBUSCTL1 — — O SDVDD 59 K6 65 L8 TS PBUSCTL0 DACK0 — O SDVDD 4 B3 12 E3 Signal Name GPIO Alternate 1 Alternate 2 A[9:0] — SD_A[9:0]3 — D[31:16] — SD_D[31:16]4 — D[15:0] — FB_D[31:16]4 BE/BWE[3:0] PBE[3:0] OE Chip Selects FB_CS[3:2] PCS[3:2] — — O SDVDD 119, 120 D7, A9 — C11, A10 FB_CS1 PCS1 SD_CS1 — O SDVDD 121 C8 127 B10 FB_CS0 — — — O SDVDD 122 B8 128 C10 SDRAM Controller SD_A10 — — — O SDVDD 37 M1 43 N2 SD_CKE — — — O SDVDD 6 C3 14 E1 SD_CLK — — — O SDVDD 31 J1 37 L1 SD_CLK — — — O SDVDD 32 K1 38 M1 SD_CS0 — — — O SDVDD 7 A1 15 F4 SD_DQS[3:2] — — — O SDVDD 19, 49 F3, M5 25, 55 H3, L6 SD_SCAS — — — O SDVDD 38 M2 44 P2 SD_SRAS — — — O SDVDD 39 J2 45 P3 SD_SDR_DQS — — — O SDVDD 29 H3 35 L3 SD_WE — — — O SDVDD 5 D3 13 E2 MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 4 Freescale Semiconductor Signal Descriptions GPIO Alternate 1 Alternate 2 Voltage Domain Signal Name Dir.1 Table 3. MCF5207/8 Signal Information and Muxing (continued) MCF5207 144 LQFP MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA External Interrupts Port5 IRQ72 PIRQ72 IRQ4 2 2 DREQ0 IRQ1 2 2 — — PIRQ4 PIRQ1 2 — I EVDD 134 A5 142 C7 — I EVDD 133 C6 141 D7 — I EVDD 132 B6 140 D8 FEC PFECI2C3 I2C_SCL2 U2TXD O EVDD — — 148 D6 FEC_MDIO PFECI2C2 2 I2C_SDA U2RXD I/O EVDD — — 147 C6 FEC_TXCLK PFECH7 — — I EVDD — — 157 B3 — PFECH6 — U1RTS O EVDD 142 A2 — — FEC_TXEN PFECH6 — U1RTS O EVDD — — 158 A2 FEC_TXD0 PFECH5 — — O EVDD — — 3 B1 FEC_COL PFECH4 — — I EVDD — — 7 D3 FEC_RXCLK PFECH3 — — I EVDD — — 154 B4 FEC_RXDV PFECH2 — — I EVDD — — 153 A4 FEC_RXD0 PFECH1 — — I EVDD — — 152 D5 FEC_CRS PFECH0 — — I EVDD — — 8 D2 FEC_TXD[3:1] PFECL[7:5] — — O EVDD — — 6–4 C1, C2, B2 — PFECL4 — U0RTS O EVDD 141 D5 — — FEC_TXER PFECL4 — U0RTS O EVDD — — 156 A3 FEC_RXD[3:2] PFECL[3:2] — — I EVDD — — 149–150 A5, B5 — PFECL1 — U1CTS I EVDD 139 B4 — — FEC_RXD1 PFECL1 — U1CTS I EVDD — — 151 C5 — PFECL0 — U0CTS I EVDD 140 E4 — — FEC_RXER PFECL0 — U0CTS I EVDD — — 155 C4 FEC_MDC Note: The MCF5207 does not contain an FEC module. However, the UART0 and UART1 control signals (as well as their GPIO signals) are available by setting the appropriate FEC GPIO port registers. I2C I2C_SDA2 PFECI2C02 U2RXD2 — I/O EVDD — — — D1 2 2 2 — I/O EVDD — — — E4 I2C_SCL PFECI2C1 U2TXD DMA DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 5 Signal Descriptions GPIO MCF5207 144 LQFP U2RTS O EVDD 126 A8 132 D10 2 — O EVDD 127 C7 133 A9 2 Alternate 1 Alternate 2 Dir.1 Signal Name Voltage Domain Table 3. MCF5207/8 Signal Information and Muxing (continued) MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA QSPI QSPI_CS2 QSPI_CLK PQSPI3 PQSPI0 DACK0 I2C_SCL QSPI_DOUT PQSPI1 I2C_SDA — O EVDD 128 A7 134 B9 QSPI_DIN PQSPI2 DREQ02 U2CTS I EVDD 129 B7 135 C9 Note: The QSPI_CS1 and QSPI_CS0 signals are available on the U1CTS, U1RTS, U0CTS, or U0RTS pins for the 196 and 160-pin packages. UARTs U1CTS PUARTL7 DT1IN QSPI_CS1 I EVDD — — 136 D9 U1RTS PUARTL6 DT1OUT QSPI_CS1 O EVDD — — 137 C8 U1TXD PUARTL5 — — O EVDD 131 A6 139 A8 U1RXD PUARTL4 — — I EVDD 130 D6 138 B8 U0CTS PUARTL3 DT0IN QSPI_CS0 I EVDD — — 76 N12 U0RTS PUARTL2 DT0OUT QSPI_CS0 O EVDD — — 77 P12 U0TXD PUARTL1 — — O EVDD 71 L10 79 P13 U0RXD PUARTL0 — — I EVDD 70 M10 78 N13 Note: The UART2 signals are multiplexed on the DMA Timers, QSPI, FEC, and I2C pins. For the MCF5207 devices, the UART0 and UART1 control signals are multiplexed internally on the FEC signals. DMA Timers DT3IN PTIMER3 DT3OUT U2CTS I EVDD 135 B5 143 B7 DT2IN PTIMER2 DT2OUT U2RTS I EVDD 136 C5 144 A7 DT1IN PTIMER1 DT1OUT U2RXD I EVDD 137 A4 145 A6 DT0IN PTIMER0 DT0OUT U2TXD I EVDD 138 A3 146 B6 BDM/JTAG6 JTAG_EN7 — — — I EVDD 83 J11 91 J13 DSCLK — TRST2 — I EVDD 76 K11 84 L12 — TCLK 2 — O EVDD 64 M7 70 P9 BKPT — TMS2 — I EVDD 75 L12 83 M14 DSI — TDI2 — I EVDD 77 H9 85 K12 DSO — TDO — O EVDD 69 M9 75 M12 DDATA[3:0] — — — O EVDD — K9, L9, M11, M8 — P11, N11, M11, P10 PST[3:0] — — — O EVDD — L11, L8, K10, K8 — N10, M10, L10, L9 PSTCLK MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 6 Freescale Semiconductor Signal Descriptions GPIO Alternate 1 Alternate 2 ALLPST — — — Voltage Domain Signal Name Dir.1 Table 3. MCF5207/8 Signal Information and Muxing (continued) MCF5207 144 LQFP MCF5207 144 MAPBGA MCF5208 160 QFP MCF5208 196 MAPBGA O EVDD 67 — 73 — Test TEST7 — — — I EVDD 109 — — C12 PLL_TEST — — — I EVDD — — — M13 Power Supplies EVDD — — — — — 1, 33, 63, 66, 72, 81, 87, 125 E5–E6, F5, G8–G9, H7–H8 2, 9, 69, 72, E5–E7, F5, 80, 89, 95, F6, G5, H10, 131 J9, J10, K8–K10, K13, M9 IVDD — — — — — 30, 68, 84, 113, 143 D4, D8, H4, H11, J9 36, 74, 92, 121, 159 J12, D4, D11, H11, L4, L11, PLL_VDD — — — — — 86 H12 94 H13 SD_VDD — — — — — 3, 17, 35, 61, E7–E8, F8, 11, 39, 41, E8–E10, F9, 89, 110, 123 G5, H5–H6, 67, 97, 118, F10, G10, J3 129 H5, J5, J6, K5–K7, L2 VSS — — — — — 2, 16, 36, 62, D10, F6–F7, 1, 10, 42, 68, 65, 73, 88, G6–G7 71, 81, 96, 111, 124 117, 119, 130 PLL_VSS — — — — — 85 — 93 A1, A14, F7–F8, G6–G9, H6–H9, J7–J8, L13, M2, N9, P1, P14 H12 NOTES: 1 Refers to pin’s primary function. 2 Pull-up enabled internally on this signal for this mode. 3 The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor when accessing SDRAM memory space and are included here for completeness. 4 Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins. 5 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions. 6 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 7 Pull-down enabled internally on this signal for this mode. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 7 Mechanicals and Pinouts 4 Mechanicals and Pinouts Drawings in this section show the pinout and the packaging and mechanical characteristics of the MCF5207 and MCF5208 devices. NOTE The mechanical drawings are the latest revisions at the time of publication of this document. The most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire. 4.1 Pinout—144 LQFP RCON IVDD U1RTS U0RTS U0CTS U1CTS DT0IN DT1IN DT2IN DT3IN IRQ7 IRQ4 IRQ1 U1TXD U1RXD QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS2 EVDD VSS SD_VDD FB_CS0 FB_CS1 FB_CS2 FB_CS3 A23 A22 A21 A20 A19 IVDD A18 VSS SD_VDD TEST 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 • 144 Figure 1 shows a pinout of the MCF5207CAG166 device. EVDD 1 108 A17 EVSS 2 107 A16 SD_VDD 3 106 A15 TS 4 105 A14 SD_WE 5 104 A13 SD_CKE 6 103 A12 SD_CS 7 102 A11 D15 8 101 A10 D14 9 100 A9 D13 10 99 A8 D12 11 98 A7 D11 D10 12 97 A6 13 96 A5 D9 14 95 A4 D8 15 94 A3 EVSS 16 93 A2 SD_VDD 17 92 A1 BE/BWE1 18 91 A0 SD_DQS3 19 90 TA BE/BWE3 20 89 SD_VDD D31 21 88 VSS D30 22 87 EVDD D29 23 86 PLL_VDD D28 24 85 PLL_VSS D27 25 84 IVDD D26 26 83 JTAG_EN D25 27 82 RESET EVDD D24 28 81 SD_SDR_DQS 29 80 XTAL IVDD 30 79 DRAMSEL SD_CLK 31 78 EXTAL SD_CLK 32 77 TDI/DSI 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 D20 D19 D18 D17 D16 BE/BWE2 SD_DQS2 BE/BWE0 D7 D6 D5 D4 D3 D2 D1 D0 R/W OE SD_VDD VSS EVDD TCLK/PSTCLK VSS EVDD ALL_PST IVDD TDO/DSO U0RXD U0TXD EVDD 42 D21 41 VSS D22 RSTOUT 73 40 74 36 D23 35 VSS 39 SD_VDD SD_RAS TMS/BKPT 38 TRST/DSCLK 75 37 76 34 SD_A10 33 FB_CLK SD_CAS SD_VDD Figure 1. MCF5207CAG166 Pinout Top View (144 LQFP) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 8 Freescale Semiconductor Mechanicals and Pinouts 4.2 Package Dimensions—144 LQFP Figure 2 and Figure 3 show MCF5207CAB166 package dimensions. Figure 2. MCF5207CAB166 Package Dimensions (Sheet 1 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 9 Mechanicals and Pinouts View A Section A-A Rotated 90× CW 144 Places View B Figure 3. MCF5207CAB166 Package Dimensions (Sheet 2 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 10 Freescale Semiconductor Mechanicals and Pinouts 4.3 Pinout—144 MAPBGA The pinout of the MCF5207CVM166 device is shown below. 1 2 3 4 5 6 7 8 9 10 11 12 A SD_CS U1RTS DT0IN DT1IN IRQ7 U1TXD QSPI_ DOUT QSPI_CS2 FB_CS2 A22 A20 A18 A B D14 D15 TS U1CTS DT3IN IRQ1 QSPI_DIN FB_CS0 A23 A19 A16 A15 B C D12 D13 SD_CKE RCON DT2IN IRQ4 QSPI_ CLK FB_CS1 A21 A10 A17 A14 C D D10 D11 SD_WE IVDD U0RTS U1RXD FB_CS3 IVDD A8 VSS A13 A11 D E D8 D9 BE/BWE1 U0CTS EVDD EVDD SD_VDD SD_VDD A4 A12 A9 A7 E F D31 D30 SD_DQS3 BE/BWE3 EVDD VSS VSS SD_VDD A0 A6 A5 A3 F G D29 D28 D26 D27 SD_VDD VSS VSS EVDD EVDD A2 TA A1 G H D25 D24 SD_SDR_ DQS IVDD SD_VDD SD_VDD EVDD EVDD TDI/DSI DRAM SEL IVDD PLL_VDD H J SD_CLK SD_RAS SD_VDD D18 BE/BWE0 D4 D2 OE IVDD RESET JTAG_EN XTAL J K SD_CLK D20 D23 D16 D6 R/W D0 PST0 DDATA3 PST1 TRST/ DSCLK EXTAL K L FB_CLK D22 D21 BE/BWE2 D7 D5 D1 PST2 DDATA2 U0TXD PST3 TMS/ BKPT L M SD_A10 SD_CAS D19 D17 SD_DQS2 D3 TCLK/ PSTCLK DDATA0 TDO/DSO U0RXD DDATA1 RSTOUT M 1 2 3 4 5 6 7 8 9 10 11 12 Figure 4. MCF5207CVM166 Pinout Top View (144 MAPBGA) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 11 Mechanicals and Pinouts 4.4 Package Dimensions—144 MAPBGA Figure 5 shows the MCF5207CAB166 package dimensions. Figure 5. MCF5207CAB166 Package Dimensions (144 MAPBGA) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 12 Freescale Semiconductor Mechanicals and Pinouts 4.5 Pinout—160 QFP DT1IN DT2IN DT3IN IRQ7 IRQ4 IRQ1 U1TXD U1RXD U1RTS U1CTS QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS2 EVDD VSS SD_VDD FB_CS0 FB_CS1 A23 A22 A21 A20 A19 IVDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 FEC_RXD2 DT0IN FEC_RXD1 150 145 FEC_RXD0 151 FEC_MDIO FEC_RXDV 152 146 FEC_RXCLK 153 FEC_MDC FEC_RXER 154 147 FEC_TXER 155 FEC_RXD3 FEC_TXCLK 156 148 FEC_TXEN 157 149 IVDD 158 RCON 160 • 159 Figure 6 shows a pinout of the MCF5208CAB166 device. VSS 1 120 A18 EVDD 2 119 VSS FEC_TXD0 3 118 SD_VDD FEC_TXD1 4 117 VSS FEC_TXD2 5 116 A17 FEC_TXD3 6 115 A16 FEC_COL 7 114 A15 FEC_CRS 8 113 A14 EVDD 9 112 A13 VSS 10 111 A12 SD_VDD 11 110 A11 TS SD_WE 12 109 A10 13 108 A9 SD_CKE 14 107 A8 SD_CS 15 106 A7 D15 16 105 A6 D14 17 104 A5 D13 18 103 A4 D12 19 102 A3 D11 20 101 A2 D10 21 100 A1 D9 22 99 A0 D8 23 98 TA SD_VDD BE/BWE1 24 97 SD_DQS3 25 96 VSS BE/BWE3 26 95 EVDD PLL_VDD D31 27 94 D30 28 93 PLL_VSS D29 29 92 IVDD D28 30 91 JTAG_EN D27 31 90 RESET EVDD D26 32 89 D25 33 88 XTAL D24 34 87 DRAMSEL SD_SDR_DQS 35 86 EXTAL IVDD 36 85 TDI/DSI 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 D20 D19 D18 D17 D16 BE/BWE2 SD_DQS2 BE/BWE0 D7 D6 D5 D4 D3 D2 D1 D0 R/W OE SD_VDD VSS EVDD TCLK/PSTCLK VSS EVDD ALL_PST IVDD TDO/DSO U0CTS U0RTS U0RXD U0TXD EVDD 48 47 D22 D21 46 D23 VSS 45 81 SD_RAS 40 44 RSTOUT FB_CLK SD_CAS 82 43 39 SD_A10 TMS/BKPT SD_VDD 42 TRST/DSCLK 41 84 83 VSS 37 38 SD_VDD SD_CLK SD_CLK Figure 6. MCF5208CAB166 Pinout Top View (160 QFP) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 13 Mechanicals and Pinouts 4.6 Package Dimensions—160 QFP The package dimensions of the MCF5208CAB166 device are shown in the figures below. Top View Figure 7. MCF5208CAB166 Package Dimensions (Sheet 1 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 14 Freescale Semiconductor Mechanicals and Pinouts SECTION B-B DETAIL A Figure 8. MCF5208CAB166 Package Dimensions (Sheet 2 of 2) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 15 Mechanicals and Pinouts 4.7 Pinout—196 MAPBGA Figure 9 shows a pinout of the MCF5208CVM166 device. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A VSS FEC_ TXEN FEC_ TXER FEC_ RXDV FEC_ RXD3 DT1IN DT2IN U1TXD QSPI_ CLK FB_CS2 A22 A20 A19 VSS A B FEC_ TXD0 FEC_ TXD1 FEC_ TXCLK FEC_ RXCLK FEC_ RXD2 DT0IN DT3IN U1RXD QSPI_ DOUT FB_CS1 A23 A21 A18 A17 B C FEC_ TXD3 FEC_ TXD2 RCON FEC_ RXER FEC_ RXD1 FEC_ MDIO IRQ7 U1RTS QSPI_ DIN FB_CS0 FB_CS3 TEST A16 A15 C D I2C_SDA FEC_ CRS FEC_ COL IVDD FEC_ RXD0 FEC_ MDC IRQ4 IRQ1 U1CTS QSPI_ CS2 IVDD A14 A13 A12 D E SD_CKE SD_WE TS I2C_SCL EVDD EVDD EVDD SD_VDD SD_VDD SD_VDD A11 A10 A9 A8 E F D13 D14 D15 SD_CS EVDD EVDD VSS VSS SD_VDD SD_VDD A7 A6 A5 A4 F G D9 D10 D11 D12 EVDD VSS VSS VSS VSS SD_VDD A3 A2 A1 A0 G H D8 BE/ BWE3 SD_ DQS3 BE/ BWE1 SD_VDD VSS VSS VSS VSS EVDD IVDD PLL_ VSS PLL_ VDD TA H J D28 D29 D30 D31 SD_VDD SD_VDD VSS VSS EVDD EVDD NC IVDD JTAG_ EN RESET J K D24 D25 D26 D27 SD_VDD SD_VDD SD_VDD EVDD EVDD EVDD DRAM SEL TDI/ DSI EVDD XTAL K SD_SDR _DQS IVDD D18 SD_ DQS2 D5 R/W PST0 PST1 IVDD TRST/ DSCLK VSS EXTAL L TMS/ BKPT M L SD_CLK SD_VDD M SD_CLK VSS D23 D21 D17 BE/ BWE0 D4 OE EVDD PST2 DDATA1 TDO/ DSO PLL_ TEST N FB_CLK SD_A10 D22 D20 D16 D7 D3 D1 VSS PST3 DDATA2 U0CTS U0RXD P VSS D19 BE/ BWE2 D6 D2 D0 TCLK/ PSTCLK DDATA0 DDATA3 U0RTS U0TXD VSS 4 5 6 7 8 9 10 11 12 13 14 1 SD_CAS SD_RAS 2 3 RSTOUT N Figure 9. MCF5208CVM166 Pinout Top View (196 MAPBGA) MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 16 Freescale Semiconductor P Electrical Characteristics 4.8 Package Dimensions—196 MAPBGA The package dimensions for the MCF5208CVM166 device is shown below. Top View Bottom View Figure 10. MCF5208CVM166 Package Dimensions (196 MAPBGA) 5 Electrical Characteristics 5.1 Maximum Ratings Table 4. Absolute Maximum Ratings1, 2 Rating Symbol Value Unit Core Supply Voltage IVDD – 0.5 to +2.0 V CMOS Pad Supply Voltage EVDD – 0.3 to +4.0 V DDR/Memory Pad Supply Voltage SDVDD – 0.3 to +4.0 V PLL Supply Voltage PLLVDD – 0.3 to +2.0 V VIN – 0.3 to +3.6 V ID 25 mA Digital Input Voltage 3 Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 17 Electrical Characteristics Table 4. Absolute Maximum Ratings1, 2 (continued) Operating Temperature Range (Packaged) TA (TL - TH) – 40 to 85 °C Tstg – 55 to 150 °C Storage Temperature Range NOTES: 1 Functional operating conditions are given in Section 5.4, “DC Electrical Specifications”. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or EVDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to VSS and EVDD. 5 Power supply must maintain regulation within operating EV DD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Ensure external EVDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. 5.2 Thermal Characteristics Table 5 lists thermal resistance values Table 5. Thermal Characteristics Characteristic Symbol 196MBGA 144MBGA 160QFP 144LQFP Unit Junction to ambient, natural convection Four layer board (2s2p) θJMA 471,2 471,2 491,2 651,2 °C/W Junction to ambient (@200 ft/min) Four layer board (2s2p) θJMA 431,2 431,2 441,2 581,2 °C/W Junction to board θJB 363 363 403 503 °C/W Junction to case θJC 224 224 394 194 °C/W Junction to top of package Ψjt 61,5 61,5 121,6 51,7 °C/W Maximum operating junction temperature Tj 105 105 105 105 o C NOTES: 1 θ JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 18 Freescale Semiconductor Electrical Characteristics 3 4 5 6 7 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D × Θ JMA ) Eqn. 1 Where: TA = Ambient Temperature, °C QJMA = Package Thermal Resistance, Junction-to-Ambient, ×C/W PD = PINT + PI/O PINT = IDD × IVDD, Watts - Chip Internal Power PI/O = Power Dissipation on Input and Output Pins — User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: K P D = --------------------------------( T J + 273°C ) Eqn. 2 Solving equations 1 and 2 for K gives: 2 K = P D × ( T A × 273°C ) + Q JMA × P D Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 5.3 ESD Protection Table 6. ESD Protection Characteristics1, 2 Characteristics ESD Target for Human Body Model Symbol Value Unit HBM 2000 V NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 19 Electrical Characteristics 2 5.4 A device is defined as a failure if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. DC Electrical Specifications Table 7. DC Electrical Specifications Characteristic Symbol Min Max Unit Core Supply Voltage IVDD 1.4 1.6 V PLL Supply Voltage PLLVDD 1.4 1.6 V EVDD 3.0 3.6 V 1.70 2.25 3.0 1.95 2.75 3.6 CMOS Pad Supply Voltage SDRAM and FlexBus Supply Voltage Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDVDD V CMOS Input High Voltage EVIH 2 EVDD + 0.3 V CMOS Input Low Voltage EVIL VSS - 0.3 0.8 V CMOS Output High Voltage IOH = –5.0 mA EVOH EVDD - 0.4 — V CMOS Output Low Voltage IOL = 5.0 mA EVOL — 0.4 V SDRAM and FlexBus Input High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDVIH 1.35 1.7 2 SDVDD + 0.3 SDVDD + 0.3 SDVDD + 0.3 SDRAM and FlexBus Input Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDVIL VSS - 0.3 VSS - 0.3 VSS - 0.3 0.45 0.8 0.8 SDRAM and FlexBus Output High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOH = –5.0 mA for all modes SDVOH SDVDD - 0.35 2.1 2.4 — — — SDRAM and FlexBus Output Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOL = 5.0 mA for all modes SDVOL — — — 0.3 0.3 0.5 –1.0 1.0 Input Leakage Current Vin = IVDD or VSS, Input-only pins Iin V V V V μA MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 20 Freescale Semiconductor Electrical Characteristics Table 7. DC Electrical Specifications (continued) Characteristic Symbol Min Max Unit Weak Internal Pull Up Device Current, tested at VIL Max.1 IAPU -10 - 130 μA Input Capacitance 2 All input-only pins All input/output (three-state) pins Cin — — 7 7 pF NOTES: 1 Refer to the signals section for pins having weak internal pull-up devices. 2 This parameter is characterized before qualification rather than 100% tested. 5.4.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 11 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible. 10 Ω Board VDD PLL VDD Pin 10 µF 0.1 µF GND Figure 11. System PLL VDD Power Filter 5.4.2 Supply Voltage Sequencing and Separation Cautions The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 5.4.2.1 Power Up Sequence If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must power up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on the internal ESD protection clamp diodes. 5.4.2.2 Power Down Sequence If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 21 Electrical Characteristics 0.4 V during power down or there is an undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is: 1. Drop IVDD/PLLVDD to 0 V. 2. Drop EVDD/SDVDD supplies. 5.5 Current Consumption All of the below current consumption data is lab data measured on a single device using an evaluation board. Table 8 shows the typical current consumption in low-power modes at various fsys/2 frequencies. Current measurements are taken after executing a STOP instruction. Table 8. Current Consumption in Low-Power Mode1,2 Mode Stop Mode 3 (Stop 11)5 Stop Mode 2 (Stop 10)5 Stop Mode 1 (Stop 01)5 Stop Mode 0 (Stop 00)5 Wait/Doze Run Voltage (V) Typical3 (mA) 44 MHz 56 MHz 64 MHz 3.3 1.33 2.5 15.19 1.5 0.519 3.3 1.93 2.5 15.19 1.5 1.25 3.3 1.83 2.5 15.23 Peak4 (mA) 72 MHz 83.33 MHz 83.33 MHz 1.5 8.24 10.22 9.55 10.61 12.1 12.1 3.3 2.23 2.33 2.41 2.5 2.61 2.61 2.5 16.2 16.47 16.62 16.91 17.24 17.24 1.5 8.32 10.32 9.66 10.73 12.25 12.25 3.3 2.23 2.33 2.41 2..5 2.6 4.07 2.5 16.2 16.48 16.62 16.91 17.24 18.77 1.5 11.53 14.36 14.29 15.92 18.21 35.45 3.3 6.79 9.02 14.56 19.54 29.12 30.43 2.5 16.17 16.48 16.64 16.89 17.23 18.76 1.5 16.29 20.36 21.13 23.57 27.0 44.1 NOTES: 1 All values are measured with a 3.30V EVDD, 2.50V SDVDD, and 1.5V IVDD power supplies. Tests performed at room temperature with pins configured for high drive strength. 2 Refer to the Power Management chapter in the MCF5208 Reference Manual for more information on low-power modes. 3 All peripheral clocks except UART0, FlexBus, INTC, reset controller, PLL, and Edge Port off before entering low-power mode. All code executed from flash. 4 Peak current measured while running a while(1) loop with all modules active. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 22 Freescale Semiconductor Electrical Characteristics 5 See the description of the low-power control register (LCPR) in the MCF5208 Reference Manual for more information on stop modes 0–3. The figure below illustrates the power consumption in a graphical format. Power Consumption (mW) 250 Stop 0 - Flash 200 Stop 1 - Flash Stop 2 - Flash 150 Stop 3 - Flash Wait/Doze - Flash 100 Run - Flash 50 0 44 48 56 64 72 83.33 83.33(peak) fsys/2 (MHz) Figure 12. Current Consumption in Low-Power Modes Table 9. Typical Active Current Consumption Specifications1 fsys/2 Frequency 1 MHz 2 MHz 4 MHz 44 MHz 48 MHz Voltage (V) Typical2 Active (mA) Peak3 Active (mA) SRAM Flash 3.3 2.04 2.12 2.28 2.5 15.24 15.32 15.24 1.5 1.30 1.41 1.49 3.3 2.23 2.40 3.57 2.5 15.26 15.42 15.26 1.5 1.71 1.92 2.09 3.3 2.60 2.95 3.58 2.5 15.30 15.61 15.30 1.5 2.49 2.95 3.29 3.3 7.61 17.67 25.34 2.5 16.13 19.49 16.95 1.5 24.04 28.72 39.02 3.3 8.16 26.21 34.45 2.5 16.28 20.06 17.17 1.5 26.05 31.13 42.30 MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 23 Electrical Characteristics Table 9. Typical Active Current Consumption Specifications1 (continued) fsys/2 Frequency Voltage (V) 56 MHz 64 MHz 72 MHz 83.33 MHz Typical2 Active (mA) Peak3 Active (mA) SRAM Flash 3.3 10.09 30.71 38.97 2.5 16.43 20.71 17.65 1.5 30.07 35.90 47.90 3.3 15.72 31.37 42.10 2.5 16.56 21.08 17.95 1.5 32.19 38.72 53.50 3.3 20.97 31.40 48.80 2.5 16.87 21.70 18.20 1.5 35.90 43.20 59.50 3.3 31.37 25.83 48.60 2.5 17.21 22.80 18.83 1.5 41.10 49.40 67.50 NOTES: 1 All values are measured with a 3.30V EV , 2.50V SDV , and 1.5V IV DD DD DD power supplies. Tests performed at room temperature with pins configured for high drive strength. 2 CPU polling a status register. All peripheral clocks except UART0, FlexBus, INTC, reset controller, PLL, and edge port disabled. 3 Peak current measured while running a while(1) loop with all modules active. 5.6 Oscillator and PLL Electrical Characteristics Table 10. PLL Electrical Characteristics Num 1 Characteristic PLL Reference Frequency Range Crystal reference External reference Symbol Min. Value Max. Value Unit fref_crystal fref_ext 12 12 251 401 MHz MHz fsys fsys/2 488 x 10-6 244 x 10-6 166.66 83.33 MHz MHz tcst — 10 ms 2 Core frequency CLKOUT Frequency2 3 Crystal Start-up Time3, 4 4 EXTAL Input High Voltage Crystal Mode5 All other modes (External, Limp) VIHEXT VIHEXT VXTAL + 0.4 EVDD/2 + 0.4 — — V V EXTAL Input Low Voltage Crystal Mode5 All other modes (External, Limp) VILEXT VILEXT — — VXTAL - 0.4 EVDD/2 - 0.4 V V 5 7 PLL Lock Time 3, 6 tlpll — 50000 CLKIN 8 Duty Cycle of reference 3 tdc 40 60 % MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 24 Freescale Semiconductor Electrical Characteristics Table 10. PLL Electrical Characteristics (continued) Num Characteristic Symbol Min. Value Max. Value Unit IXTAL 1 3 mA 9 XTAL Current 10 Total on-chip stray capacitance on XTAL CS_XTAL 1.5 pF 11 Total on-chip stray capacitance on EXTAL CS_EXTAL 1.5 pF 12 Crystal capacitive load CL See crystal spec 13 Discrete load capacitance for XTAL CL_XTAL 2*CL CS_XTAL CPCB_XTAL7 pF 14 Discrete load capacitance for EXTAL CL_EXTAL 2*CL CS_EXTAL CPCB_EXTAL7 pF 17 CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter Cjitter — — 10 TBD % fsys/2 % fsys/2 18 Frequency Modulation Range Limit 3, 10, 11 (fsysMax must not be exceeded) Cmod 0.8 2.2 %fsys/2 19 VCO Frequency. fvco = (fref * PFD)/4 fvco 350 540 MHz NOTES: 1 The maximum allowable input clock frequency when booting with the PLL enabled is 24 MHz. For higher input clock frequencies, the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency. 2 All internal registers retain data at 0 Hz. 3 This parameter is guaranteed by characterization before qualification rather than 100% tested. 4 Proper PC board layout procedures must be followed to achieve specifications. 5 This parameter is guaranteed by design rather than 100% tested. 6 This specification is the PLL lock time only and does not include oscillator start-up time. 7 C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. 10 Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz. 11 Modulation range determined by hardware design. 5.7 External Interface Timing Characteristics Table 11 lists processor bus input timings. NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the FB_CLK output. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 25 Electrical Characteristics All other timing relationships can be derived from these values. Timings listed in Table 11 are shown in Figure 14 and Figure 15. * The timings are also valid for inputs sampled on the negative clock edge. 1.5V FB_CLK(75MHz) TSETUP THOLD Input Setup And Hold Invalid 1.5V Valid 1.5V Invalid trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time FB_CLK Vh = VIH Vl = VIL FB4 FB5 Inputs Figure 13. General Input Timing Requirements 5.7.1 FlexBus FlexBus is a multi-function external bus interface provided to interface to slave-only devices up to a maximum bus frequency of 83.33 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FB_CS[5:0]) that can be configured to be distributed between the FlexBus or SDRAM memory interfaces. Chip-select FB_CS[0] can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 26 Freescale Semiconductor Electrical Characteristics 5.7.1.1 FlexBus AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock. Table 11. FlexBus AC Timing Specifications Num Characteristic Symbol Min Frequency of Operation FB1 Clock Period (FB_CLK) FB2 Max Unit Notes 83.33 Mhz fsys/2 ns tcyc tFBCK 12 Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) tFBCHDCV — 7.0 ns 1 FB3 Data, and Control Output Hold ((A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE) tFBCHDCI 1 — ns 1, 2 FB4 Data Input Setup tDVFBCH 3.5 — ns FB5 Data Input Hold tDIFBCH 0 — ns FB6 Transfer Acknowledge (TA) Input Setup tCVFBCH 4 — ns FB7 Transfer Acknowledge (TA) Input Hold tCIFBCH 0 — ns NOTES: 1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8, “SDRAM Bus” for SD_CS[1:0] timing. 2 The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more information. NOTE The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read and write bus cycles the address signals are indeterminate. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 27 Electrical Characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[23:0] FB_A[23:0] FB2 FB_D[31:X] FB5 ADDR[31:X] DATA FB4 FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB6 FB7 FB_TA Figure 14. FlexBus Read Timing S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[23:0] FB_A[23:0] FB2 FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB6 FB7 FB_TA Figure 15. Flexbus Write Timing 5.8 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for Class I or Class II drive strength. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 28 Freescale Semiconductor Electrical Characteristics 5.8.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The SDRAM controller is a DDR controller with an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read. The ColdFire processor accomplishes this by asserting a signal called SD_SDR_DQS during read cycles. Take care during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS signal and its usage. Table 12. SDR Timing Specifications Symbol Characteristic Symbol Frequency of Operation Min Max Unit Notes 60 83.33 MHz 1 SD1 Clock Period (tCK) tSDCK 12 16.67 ns 2 SD3 Pulse Width High (tCKH) tSDCKH 0.45 0.55 SD_CLK 3 SD4 Pulse Width Low (tCKL) tSDCKL 0.45 0.55 SD_CLK 3 SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid (tCMV) tSDCHACV — 0.5 × SD_CLK + 1.0 ns SD6 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold (tCMH) tSDCHACI 2.0 — ns SD7 SD_SDR_DQS Output Valid (tDQSOV) tDQSOV — Self timed ns 4 SD8 SD_DQS[3:2] input setup relative to SD_CLK (tDQSIS) tDQVSDCH 0.25 × SD_CLK 0.40 × SD_CLK ns 5 SD9 SD_DQS[3:2] input hold relative to SD_CLK (tDQSIH) tDQISDCH SD10 Data (D[31:0]) Input Setup relative to SD_CLK (reference only) (tDIS) tDVSDCH 0.25 × SD_CLK — ns SD11 Data Input Hold relative to SD_CLK (reference only) (tDIH) tDISDCH 1.0 — ns SD12 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output tSDCHDMV Valid (tDV) — 0.75 × SD_CLK + 0.5 ns SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output tSDCHDMI Hold (tDH) 1.5 — ns Does not apply. 0.5 SD_CLK fixed width. 6 7 NOTES: 1 The device supports the same frequency of operation for FlexBus and SDRAM as that of the internal bus clock. Please see the PLL chapter of the MCF5208 Reference Manual for more information on setting the SDRAM clock rate. 2 SD_CLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat. 5 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat. 6 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. 7 Because a read cycle in SDR mode continues using the DQS circuit within the device, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec is provided as guidance. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 29 Electrical Characteristics SD2 SD1 SD_CLK SD3 SD5 SD_CSn SD_RAS SD_CAS SD_WE CMD SD4 A[23:0] SD_BA[1:0] ROW COL SD11 SDDM SD12 WD1 D[31:0] WD2 WD3 WD4 Figure 16. SDR Write Timing SD2 SD1 SD_CLK SD_CSn, SD_RAS, SD_CAS, SD_WE A[23:0], SD_BA[1:0] SD5 SD3 CMD 3/4 MCLK Reference SD4 ROW COL tDQS SDDM SD6 SD_SDR_DQS (Measured at Output Pin) Board Delay SD_DQS[3:2] SD8 (Measured at Input Pin) SD7 Board Delay Delayed SD_CLK SD9 D[31:0] from Memories WD1 NOTE: Data driven from memories relative to delayed memory clock. WD2 WD3 WD4 SD10 Figure 17. SDR Read Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 30 Freescale Semiconductor Electrical Characteristics 5.8.2 DDR SDRAM AC Timing Characteristics When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early board design. Please contact your local Freescale representative if questions develop. Table 13. DDR Timing Specifications Num Characteristic Symbol Min Max Unit Notes — Frequency of Operation — 60 83.33 Mhz 1 DD1 Clock Period (SD_CLK) tDDCK 12 16.67 ns 2 DD2 Pulse Width High tDDCKH 0.45 0.55 SD_CLK 3 DD3 Pulse Width Low tDDCKL 0.45 0.55 SD_CLK 3 DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Valid tSDCHACV — 0.5 × SD_CLK + 1.0 ns 4 DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold tSDCHACI 2.0 — ns — DD6 Write Command to first DQS Latching Transition tCMDVDQ 1.25 SD_CLK — DD7 Data and Data Mask Output Setup (DQ-->DQS) Relative to DQS (DDR Write Mode) tDQDMV 1.5 — ns 5 DD8 Data and Data Mask Output Hold (DQS-->DQ) Relative to DQS (DDR Write Mode) tDQDMI 1.0 — ns 7 DD9 Input Data Skew Relative to DQS (Input Setup) tDVDQ — 1 ns 8 DD10 Input Data Hold Relative to DQS. tDIDQ 0.25 × SD_CLK + 0.5ns — ns 9 DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH 0.5 — ns — DD12 DQS input read preamble width (tRPRE) tDQRPRE 0.9 1.1 SD_CLK — DD13 DQS input read postamble width (tRPST) tDQRPST 0.4 0.6 SD_CLK — DD14 DQS output write preamble width (tWPRE) tDQWPRE 0.25 — SD_CLK — DD15 DQS output write postamble width (tWPST) tDQWPST 0.4 0.6 SD_CLK — 6 NOTES: 1 The frequency of operation is 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same frequency as the internal bus clock. 2 SD_CLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and voltage variations. 5 This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. 6 The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 31 Electrical Characteristics 7 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0]. 8 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 9 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid. DD1 DD2 SD_CLK DD3 SD_CLK DD5 SD_CSn, SD_WE, SD_RAS, SD_CAS CMD DD4 A[13:0] DD6 ROW COL DD7 DM3/DM2 DD8 SD_DQS3/SD_DQS2 DD7 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 DD8 Figure 18. DDR Write Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 32 Freescale Semiconductor Electrical Characteristics DD1 DD2 SD_CLK DD3 SD_CLK CL=2 DD5 SD_CSn, SD_WE, SD_RAS, SD_CAS CMD CL=2.5 DD4 A[13:0] ROW COL DD9 DQS Read Preamble CL = 2 SD_DQS3/SD_DQS2 DQS Read Postamble DD10 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble CL = 2.5 SD_DQS3/SD_DQS2 D[31:24]/D[23:16] WD1 WD2 WD3 WD4 Figure 19. DDR Read Timing 5.9 General Purpose I/O Timing Table 14. GPIO Timing1 Num Characteristic Symbol Min Max Unit G1 FB_CLK High to GPIO Output Valid tCHPOV — 8 ns G2 FB_CLK High to GPIO Output Invalid tCHPOI 1.5 — ns G3 GPIO Input Valid to FB_CLK High tPVCH 8 — ns G4 FB_CLK High to GPIO Input Invalid tCHPI 1.5 — ns NOTES: 1 GPIO spec cover: IRQn, UART and Timer pins. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 33 Electrical Characteristics FB_CLK G2 G1 GPIO Outputs G3 G4 GPIO Inputs Figure 20. GPIO Timing 5.10 Reset and Configuration Override Timing Table 15. Reset and Configuration Override Timing Num Characteristic Symbol Min Max Unit R1 RESET Input valid to FB_CLK High tRVCH 9 — ns R2 FB_CLK High to RESET Input invalid tCHRI 1.5 — ns R3 RESET Input valid Time 1 tRIVT 5 — tCYC R4 FB_CLK High to RSTOUT Valid tCHROV — 10 ns R5 RSTOUT valid to Config. Overrides valid tROVCV 0 — ns R6 Configuration Override Setup Time to RSTOUT invalid tCOS 20 — tCYC R7 Configuration Override Hold Time after RSTOUT invalid tCOH 0 — ns R8 RSTOUT invalid to Configuration Override High Impedance tROICZ — 1 tCYC NOTES: 1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. FB_CLK R1 R2 R3 RESET R4 R4 RSTOUT R8 R5 R6 R7 Configuration Overrides*: (RCON, Override pins) Figure 21. RESET and Configuration Override Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 34 Freescale Semiconductor Electrical Characteristics NOTE Refer to the MCF5208 Reference Manual for more information. 5.11 I2C Input/Output Timing Specifications Table 16 and Table 17 list specifications for the I2C input and output timing parameters. Table 16. I2C Input Timing Specifications between I2C_SCL and I2C_SDA Num Characteristic Min Max Unit I1 Start condition hold time 2 — tcyc I2 Clock low period 8 — tcyc I3 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 ms I4 Data hold time 0 — ns I5 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 1 ms I6 Clock high time 4 — tcyc I7 Data setup time 0 — ns I8 Start condition setup time (for repeated start condition only) 2 — tcyc I9 Stop condition setup time 2 — tcyc Table 17. I2C Output Timing Specifications between I2C_SCL and I2C_SDA Num I11 I2 1. I3 2 I4 1. I5 3 Characteristic Min Max Unit Start condition hold time 6 — tcyc Clock low period 10 — tcyc I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — — µs Data hold time 7 — tcyc I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 3 ns 1. Clock high time 10 — tcyc I7 1. Data setup time 2 — tcyc Start condition setup time (for repeated start condition only) 20 — tcyc Stop condition setup time 10 — tcyc I6 I8 1. I9 1. NOTES: 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table A-16. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table A-16 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 35 Electrical Characteristics I2 I6 I5 I2C_SCL I1 I4 I3 I8 I9 I7 I2C_SDA Figure 22. I2C Input/Output Timings 5.12 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V. 5.12.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV, FEC_RXER, and FEC_RXCLK) The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_RXCLK frequency. Table 18 lists MII receive channel timings. Table 18. MII Receive Signal Timing Num Characteristic Min Max Unit M1 FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup 5 — ns M2 FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold 5 — ns M3 FEC_RXCLK pulse width high 35% 65% FEC_RXCLK period M4 FEC_RXCLK pulse width low 35% 65% FEC_RXCLK period Figure 23 shows MII receive signal timings listed in Table 18. M3 FEC_RXCLK (input) M4 FEC_RXD[3:0] (inputs) FEC_RXDV FEC_RXER M1 M2 Figure 23. MII Receive Signal Timing Diagram MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 36 Freescale Semiconductor Electrical Characteristics 5.12.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK) Table 19 lists MII transmit channel timings. The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. In addition, the processor clock frequency must exceed twice the FEC_TXCLK frequency. Table 19. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid 5 — ns M6 FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid — 25 ns M7 FEC_TXCLK pulse width high 35% 65% FEC_TXCLK period M8 FEC_TXCLK pulse width low 35% 65% FEC_TXCLK period Figure 24 shows MII transmit signal timings listed in Table 19. M7 FEC_TXCLK (input) M5 M8 FEC_TXD[3:0] (outputs) FEC_TXEN FEC_TXER M6 Figure 24. MII Transmit Signal Timing Diagram 5.12.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL) Table 20 lists MII asynchronous inputs signal timing. Table 20. MII Async Inputs Signal Timing Num M9 Characteristic Min Max Unit 1.5 — FEC_TXCLK period FEC_CRS, FEC_COL minimum pulse width Figure 25 shows MII asynchronous input timings listed in Table 20. FEC_CRS FEC_COL M9 Figure 25. MII Async Inputs Timing Diagram MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 37 Electrical Characteristics 5.12.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 21. MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) 0 — ns M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay) — 25 ns M12 FEC_MDIO (input) to FEC_MDC rising edge setup 10 — ns M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns M14 FEC_MDC pulse width high 40% 60% FEC_MDC period M15 FEC_MDC pulse width low 40% 60% FEC_MDC period Figure 26 shows MII serial management channel timings listed in Table 21. M14 M15 FEC_MDC (output) M10 FEC_MDIO (output) M11 FEC_MDIO (input) M12 M13 Figure 26. MII Serial Management Channel Timing Diagram MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 38 Freescale Semiconductor Electrical Characteristics 5.13 32-Bit Timer Module AC Timing Specifications Table 22 lists timer module AC timings. Table 22. Timer Module AC Timing Specifications Name Characteristic Unit Min Max T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — tCYC T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — tCYC 5.14 QSPI Electrical Specifications Table 23 lists QSPI timings. Table 23. QSPI Modules AC Timing Specifications Name Characteristic Min Max Unit QS1 QSPI_CS[3:0] to QSPI_CLK 1 510 tcyc QS2 QSPI_CLK high to QSPI_DOUT valid. — 10 ns QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold) 1.5 — ns QS4 QSPI_DIN to QSPI_CLK (Input setup) 9 — ns QS5 QSPI_DIN to QSPI_CLK (Input hold) 9 — ns The values in Table 23 correspond to Figure 27. QS1 QSPI_CS[3:0] QSPI_CLK QS2 QSPI_DOUT QS3 QS4 QS5 QSPI_DIN Figure 27. QSPI Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 39 Electrical Characteristics 5.15 JTAG and Boundary Scan Timing Table 24. JTAG and Boundary Scan Timing Characteristics1 Num Symbol Min Max Unit J1 TCLK Frequency of Operation fJCYC DC 1/4 fsys/2 J2 TCLK Cycle Period tJCYC 4 — tCYC J3 TCLK Clock Pulse Width tJCW 26 — ns J4 TCLK Rise and Fall Times tJCRF 0 3 ns J5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 4 — ns J6 Boundary Scan Input Data Hold Time after TCLK Rise tBSDHT 26 — ns J7 TCLK Low to Boundary Scan Output Data Valid tBSDV 0 33 ns J8 TCLK Low to Boundary Scan Output High Z tBSDZ 0 33 ns J9 TMS, TDI Input Data Setup Time to TCLK Rise tTAPBST 4 — ns J10 TMS, TDI Input Data Hold Time after TCLK Rise tTAPBHT 10 — ns J11 TCLK Low to TDO Data Valid tTDODV 0 26 ns J12 TCLK Low to TDO High Z tTDODZ 0 8 ns J13 TRST Assert Time tTRSTAT 100 — ns J14 TRST Setup Time (Negation) to TCLK High tTRSTST 10 — ns NOTES: 1 JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it. J2 J3 J3 VIH TCLK (input) J4 VIL J4 Figure 28. Test Clock Input Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 40 Freescale Semiconductor Electrical Characteristics TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 29. Boundary Scan (JTAG) Timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 30. Test Access Port Timing TCLK J14 TRST J13 Figure 31. TRST Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 41 Electrical Characteristics 5.16 Debug AC Timing Specifications Table 25 lists specifications for the debug AC timing parameters shown in Figure 32. Table 25. Debug AC Timing Specification Num Characteristic Min Max Unit D0 PSTCLK cycle time 1 1 tSYS D1 PSTCLK rising to PSTDDATA valid — 3.0 ns D2 PSTCLK rising to PSTDDATA invalid 1.5 — ns D3 DSI-to-DSCLK setup 1 — PSTCLK D41 DSCLK-to-DSO hold 4 — PSTCLK D5 DSCLK cycle time 5 — PSTCLK D6 BKPT assertion time 1 — PSTCLK NOTES: 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK. D0 PSTCLK D2 D1 PSTDDATA[7:0] Figure 32. Real-Time Trace AC Timing D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 33. BDM Serial Port AC Timing MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 42 Freescale Semiconductor Revision History 6 Revision History Table 26. Revision History Revision Number Date 0 5/23/2005 • Initial Release 0.1 6/16/2005 • Corrected 144QFP pinout in Figure 1. Pins 139-142 incorrectly showed FEC functionality, which are actually UART 0/1 clear-to-send and request-to-send signals. • Changed maximum core frequency in Table 10, spec #2, from 240MHz to 166.67MHz. Also, changed symbols in table: fcore -> fsys and fsys -> fsys/2 for consistency throughout document and reference manual. 0.2 8/26/2005 • Changed ball M9 from SD_VDD to EVDD in Figure 9. • Table 3: Pin 33 for 144 LQFP package should be EVDD instead of SD_VDD. BE/BWE[3:0] for 144 LQFP should be “20, 48, 18, 50“ instead of “18, 20, 48, 50” Cleaned up various electrical specifications: • Table 4: Added DDR/Memory pad supply voltage spec, changed “clock synthesizer supply voltage” to “PLL supply voltage”, changed min PLLVDD from -0.5 to -0.3, changed max VIN from 4.0 to 3.6, changed minimum Tstg from -65 to -55, • Table 5: Changed TBD values in Tj entry to 105°C. • Table 7: Changed minimum core supply voltage from 1.35 to 1.4 and maximum from 1.65 to 1.6, added PLL supply voltage entry, added pad supply entries for mobile-DDR, DDR, and SDR, changed minimum input high voltage from 0.7xEVDD to 2 and maximum from 3.65 to EVDD+0.05, changed minimum input low voltage from VSS-0.3 to -0.05 and maximum from 0.35xEVDDto 0.8, added input high/low voltage entries for DDR and mobile-DDR, removed high impedance leakage current entry, changed minimum output high voltage from EVDD-0.5 to EVDD-0.4, added DDR/bus output high/low voltage entries, removed load capacitance and DC injection current entries. • Added filtering circuits and voltage sequencing sections: Section 5.4.1, “PLL Power Filtering,” and Section 5.4.2, “Supply Voltage Sequencing and Separation Cautions.” • Removed “Operating Conditions” table from Section 5.6, “Oscillator and PLL Electrical Characteristics,” because it is redundant with Table 7. • Table 11: Changed minimum core frequency to TBD, removed external reference and on-chip PLL frequency specs to have only a CLKOUT frequency spec of TBD to 83.33MHz, removed loss of reference frequency and self-clocked mode frequency entries, in EXTAL input high/low voltage entries changed “All other modes (Dual controller (1:1), Bypass, External)” to “All other modes (External, Limp)”, removed XTAL output high/low voltage entries, removed power-up to lock time entry, removed last 5 entries (frequency un-lock range, frequency lock range, CLKOUT period jitter, frequency modulation range limit, and ICO frequency) 0.3 9/07/2005 • • • • Substantive Changes Corrected DRAMSEL footnote #3 in Table 3. Updated Table 3 with 144MAPBGA pin locations. Added 144MAPBGA ballmap to Section 4.3, “Pinout—144 MAPBGA.” Changed J12 from PLL_VDD to IVDD in Figure 9. MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 43 Revision History Table 26. Revision History (continued) Revision Number Date Substantive Changes 0.4 10/10/2005 • Figure 1 and Table 3: Changed pin 33 from EVDD to SD_VDD • Figure 4 and Table 3: Changed ball D10 from TEST to VSS • Figure 6 and Table 3: Changed pin 39 from EVDD to SD_VDD and pin 117 from TEST to VSS 0.5 3/29/2006 • Added “top view” and “bottom view” labels where appropriate to mechanical drawings and pinouts. • Updated mechanical drawings to latest available, and added note to Section 4, “Mechanicals and Pinouts.” 0.6 7/21/2006 • Corrected cross-reference to Figure 9 in Section 4.7, “Pinout—196 MAPBGA.” • Corrected L3 label in Figure 9 from SD_DR_DQS to SD_SDR_DQS. • Corrected L6 label in Figure 9 from SD_DQS0 to SD_DQS2 and H3 from SD_DQS1 to SD_DQS3. • Removed second sentence from Section 5.12.2, “MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK),” regarding no minimum frequency requirement for TXCLK. • Removed third and fourth paragraphs from Section 5.12.2, “MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK),” as this feature is not supported on this device. 1 3/28/2007 • Removed preliminary designation from Section 5, “Electrical Characteristics.” • Updated Section 5.2, “Thermal Characteristics.” • Updated Section 5.4, “DC Electrical Specifications.” • Added Section 5.5, “Current Consumption.” • Updated Section 5.6, “Oscillator and PLL Electrical Characteristics.” • Made some corrections to the drawings in Section 5.8, “SDRAM Bus.” • Edited for grammar, punctuation, spelling, style, and format. - JD 2 12/4/2008 • Updated FlexBus read and write timing diagrams in Figure 14 and Figure 15. Changed the following specs in Table 12 and Table 13: • Minimum frequency of operation from TBD to 60MHz • Maximum clock period from TBD to 16.67 ns MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 44 Freescale Semiconductor Revision History MCF5208 ColdFire® Microprocessor Data Sheet, Rev. 2 Freescale Semiconductor 45 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2008. All rights reserved. MCF5208EC Rev. 2 12/2008