ATMEL AT17C020-10JI

Features
• EE Reprogrammable 2,097,152 x 1 bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX® Devices,
•
•
•
•
•
•
•
•
ORCA® FPGAs, Xilinx XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs
Cascadable Read Back to Support Additional Configurations or
Future Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in PLCC Package (Pin Compatible across Product Family)
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Available in 3.3V ± 10% LV and 5V ± 5% C Versions
System-friendly READY Pin
Low-power Standby Mode
Description
The AT17C020 and AT17LV020 (high-density AT17 Series) FPGA Configuration
EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the popular
20-pin PLCC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough
memory to configure one or multiple smaller FPGAs. The user can select the polarity
of the reset function by programming internal EEPROM bytes. These devices also
support a system-friendly READY pin, which signifies a “good” power level to the
FPGA and can be used to ensure reliable system power-up.
2-megabit
FPGA
Configuration
EEPROM
Memory
AT17C020
AT17LV020
The AT17 Series Configurators can be programmed with industry-standard programmers or Atmel’s ATDH2200E Programming System.
Pin Configurations
18
17
16
15
14
9
10
11
12
13
4
5
6
7
8
NC
SER_EN
NC
READY
CEO(A2)
NC
GND
NC
NC
NC
CLK
NC
RESET/OE
NC
CE
3
2
1
20
19
NC
DATA
NC
VCC
NC
PLCC
Rev. 1239D–05/01
1
Block Diagram
CEO (A2)
FPGA Master Serial
Mode Summary
The I/O and logic functions of the FPGA and their associated interconnections are
established by a configuration program. The program is loaded either automatically
upon power-up, or on command, depending on the state of the FPGA mode pins. In
Master Mode, the FPGA automatically loads the configuration program from an external
memory. The AT17 Serial Configuration EEPROM has been designed for compatibility
with the Master Serial Mode.
This document discusses the AT40K FPGA interface. For more details or AT6K FPGA
applications, please reference “AT40K Series Configuration” or “AT6000 Series Configuration” application notes.
Controlling the Highdensity AT17 Series
Serial EEPROMs
During Configuration
Most connections between the FPGA device and the AT17 Serial EEPROM are simple
and self-explanatory:
•
The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices.
•
The master FPGA CCLK output drives the CLK input of the AT17 Series
Configurator.
•
The CEO output of any AT17C/LV020 drives the CE input of the next AT17C/LV020
in a cascade chain of EEPROMs.
•
SER_EN must be connected to VCC, (except during ISP).
The READY pin is available as an open-collector indicator of the device’s RESET status; it is driven Low while the device is in its POWER-ON RESET cycle and released
(tri-stated) when the cycle is complete.
There are two different ways to use the inputs CE and OE.
2
AT17C/LV020
AT17C/LV020
Condition 1
The simplest connection is to have the FPGA CON pin drive both CE and RESET/OE(1)
in parallel. Due to its simplicity, however, this method will fail if the FPGA receives an
external reset condition during the configuration cycle. If a system reset is applied to the
FPGA, it will abort the original configuration and then reset itself for a new configuration,
as intended. Of course, the AT17 Series Configurator does not see the external reset
signal and will not reset its internal address counters and, consequently, will remain out
of sync with the FPGA for the remainder of the configuration cycle.
Note:
1. For this condition, the reset polarity of the EEPROM must be set active High.
Figure 1. Condition 2 Connection
AT17C/LV020
AT40K
RESET
RESET
M2
M1
M0
D<0>
CCLK
CON
INIT
DATA
CLK
CE
RESET/OE
VCC
SER_EN
READY
GND
Notes:
Condition 2
1. Use of the READY pin is optional.
2. Reset polarity must be set to active Low.
The FPGA CON pin drives only the CE input of the AT17 Series Configurator, while the
OE input is driven by the FPGA INIT pin (Figure 1). This connection works under all normal circumstances, even when the user aborts a configuration before CON has gone
High. A Low level on the RESET/OE(1) input – during FPGA reset – clears the Configurator’s internal address pointer, so that the reconfiguration starts at the beginning.
Note:
1. For this condition, the reset polarity of the EEPROM must be set active Low.
The AT17 Series Configurator does not require an inverter for either condition since the
RESET polarity is programmable.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger
configuration memories, cascaded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock signal to the Configurator
asserts its CEO output Low and disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded Configurators are
reset if the RESET/OE on each Configurator is driven to its active (default High) level.
If the address counters are not to be reset upon completion, then the RESET/OE inputs
can be tied to its inactive (default Low) level. For more details on programming the
EEPROM’s reset polarity, please reference “Programming Specification for Atmel’s
FPGA Configuration EEPROMs”.
AT17 Series Reset
Polarity
The AT17 Series Configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry standard programmer
algorithms. For more details on programming the EEPROM’s reset polarity, please ref-
3
erence the “Programming Specification for Atmel’s FPGA Configuration EEPROMs”
application note.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. See the “Programming
Specification for Atmel's FPGA Configuration EEPROMs” application note for further
information. The AT17C parts are read/write at 5V nominal. The AT17LV parts are
read/write at 3.3V nominal.
Standby Mode
The AT17C/LV020 enters a low-power standby mode whenever CE is asserted High. In
this mode, the Configurator consumes less than 0.5 mA of current at 5.0 volts with
CMOS level inputs. The output remains in a high impedance state regardless of the
state of the OE input.
Pin Configurations
20-pin
PLCC
Name
I/O
2
DATA
I/O
4
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
6
RESET/OE
I
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
8
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low-power standby mode. Note that this pin will not enable/disable the device in
the 2-wire Serial Programming Mode (i.e., when SER_EN is Low).
10
GND
Description
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
CEO
O
Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit read
from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until
OE goes High. Thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low; see the “Programming Specification” application note for more
details).
15
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released when powerup is complete. (Recommend a 4.7 KΩ pull-up on this pin if used).
17
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode.
20
VCC
14
4
+3.3V/+5V power supply pin.
AT17C/LV020
AT17C/LV020
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .............................-0.1V to VCC + 0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or
any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
Operating Conditions
AT17C020
Symbol
VCC
Description
AT17LV020
Min
Max
Min/
Max
Units
Commercial
Supply voltage relative to GND,
-0°C to +70°C
4.75
5.25
3.0
3.6
V
Industrial
Supply voltage relative to GND,
-40°C to +85°C
4.5
5.5
3.0
3.6
V
Military
Supply voltage relative to GND,
-55°C to +125°C
4.5
5.5
3.0
3.6
V
5
DC Characteristics
VCC = 5V ± 5% Commercial, 5V ± 10% Industrial/Military
Symbol
Description
Min
Max
Units
VIH
High-level input voltage
2.0
VCC
V
VIL
Low-level input voltage
0.0
0.8
V
VOH
High-level output voltage (IOH = -4 mA)
VOL
Low-level output voltage (IOL = +4 mA)
VOH
High-level output voltage (IOH = -4 mA)
VOL
Low-level output voltage (IOL = +4 mA)
VOH
High-level output voltage (IOH = -4 mA)
VOL
Low-level output voltage (IOL = +4 mA)
0.4
V
ICCA
Supply current, active mode
10.0
mA
IL
Input or output leakage current (VIN = VCC or GND)
20.0
µA
Commercial
0.5
mA
ICCS1
Supply current, standby mode, CMOS
Industrial/Military
0.75
mA
ICCS2
Supply current, standby mode, TTL
Comm./Industrial
1.0
mA
3.86
V
Commercial
0.32
3.76
V
V
Industrial
0.37
3.7
V
V
Military
-20.0
DC Characteristics
VCC = 3.3V ± 10%
Symbol
Description
Min
Max
Units
VIH
High-level input voltage
2.0
VCC
V
VIL
Low-level input voltage
0.0
0.8
V
VOH
High-level output voltage (IOH = -2.5 mA)
VOL
Low-level output voltage (IOL = +3 mA)
VOH
High-level output voltage (IOH = -2 mA)
VOL
Low-level output voltage (IOL = +3 mA)
VOH
High-level output voltage (IOH = -2 mA)
VOL
Low-level output voltage (IOL = +2.5 mA)
0.4
V
ICCA
Supply current, active mode
5.0
mA
IL
Input or output leakage current (VIN = VCC or GND)
20.0
µA
Commercial
0.2
mA
ICCS
Supply current, standby mode
Industrial/Military
0.2
mA
6
AT17C/LV020
2.4
V
Commercial
0.4
2.4
V
V
Industrial
0.4
2.4
V
V
Military
-2.00
AT17C/LV020
AC Characteristics
CE
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
AC Characteristics When Cascading
RESET/OE
CE
CLK
TCDF
DATA
LAST BIT
TOCK
FIRST BIT
TOOE
TOCE
CEO
TOCE
7
.
AC Characteristics for AT17C020
VCC = 5V ± 5% Commercial, VCC = 5V ± 10% Industrial/Military
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
(2)
TCE
TCAC
(2)
Min
Max
Industrial/Military(1)
Max
Units
30.0
35.0
ns
CE to Data Delay
45.0
45.0
ns
CLK to Data Delay
50.0
50.0
ns
TOH
Data Hold From CE, OE or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
20.0
20.0
ns
THC
CLK High Time
20.0
20.0
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
20.0
25.0
ns
THCE
CE Hold Time from CLK (to guarantee proper counting)
0.0
0.0
ns
THOE
OE High Time (guarantees counter is reset)
20.0
20.0
ns
FMAX
MAX Input Clock Frequency
12.5
12.5
MHz
Notes:
0.0
Min
0.0
50.0
ns
50.0
ns
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
AC Characteristics for AT17C020 When Cascading
VCC = 5V± 5% Commercial/VCC = 5V ± 10% Industrial/Military
Commercial
Symbol
Description
TCDF (3)
CLK to Data Float Delay
TOCK(2)
TOCE(2)
TOOE(2)
FMAX
Notes:
8
Max
Units
50.0
50.0
ns
CLK to CEO Delay
35.0
40.0
ns
CE to CEO Delay
40.0
80.0
ns
RESET/OE to CEO Delay
30.0
30.0
ns
MAX Input Clock Frequency
Min
12.5
Max
Industrial/Military(1)
Min
12.5
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
AT17C/LV020
MHz
AT17C/LV020
AC Characteristics for AT17LV020
VCC = 3.3V ± 10%
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
(2)
TCE
TCAC
(2)
Min
Max
Industrial/Military(1)
Max
Units
5.00
55.0
ns
CE to Data Delay
55.0
60.0
ns
CLK to Data Delay
55.0
60.0
ns
TOH
Data Hold From CE, OE or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
25.0
25.0
ns
THC
CLK High Time
25.0
25.0
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
30.0
35.0
ns
THCE
CE Hold Time from CLK (to guarantee proper counting)
0.0
0.0
ns
THOE
OE High Time (guarantees counter is reset)
25.0
25.0
ns
FMAX
MAX Input Clock Frequency
12.5
7.5
MHz
Notes:
0.0
Min
0.0
50.0
ns
50.0
ns
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
AC Characteristics for AT17LV020 When Cascading
VCC = 3.3V ± 10%
Commercial
Symbol
Description
TCDF(3)
CLK to Data Float Delay
TOCK(2)
TOCE(2)
TOOE(2)
FMAX
Notes:
Max
Units
50.0
50.0
ns
CLK to CEO Delay
50.0
55.0
ns
CE to CEO Delay
40.0
80.0
ns
RESET/OE to CEO Delay
35.0
35.0
ns
MAX Input Clock Frequency
Min
12.5
Max
Industrial/Military(1)
Min
7.5
MHz
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
9
Ordering Information - 5V Devices
Memory Size
Ordering Code
Package
Operation Range
2Mb
AT17C020-10JC
20J
Commercial
(0°C to 70°C)
AT17C020-10JI
20J
Industrial
(-40°C to 85°C)
Ordering Information - 3.3V Devices
Memory Size
Ordering Code
Package
Operation Range
2Mb
AT17LV020-10JC
20J
Commercial
(0°C to 70°C)
AT17LV020-10JI
20J
Industrial
(-40°C to 85°C)
Package Type
20J
10
20-lead, Plastic J-leaded Chip Carrier (PLCC)
AT17C/LV020
AT17C/LV020
Packaging Information
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
11
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
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FLEX is the registered trademark of Altera Corporation.
ORCA is the registered trademark of Lucent Technologies, Inc.
Spartan and Virtex are the registered trademarks of Xilinx, Inc.
Other terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1239D–05/01/xM