Features • • • • • • • • • • • Reference Oscillator up to 15 MHz (Tuned) Oscillator Buffer Output (for AM Up/Down Conversion) Two Programmable 16-bit Dividers Fine-tuning Steps Possible Fast Response Time due to Integrated Loop Push-pull Stage 3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers Acceptable) Four Programmable Switching Outputs (Open Drain) Three DACs for Software Controlled Tuner Alignment Low-power Consumption High S/N Ratio Integrated Band Gap – only One Supply Voltage Necessary Description The U4256BM-R is a synthesizer IC for FM receivers and an AM up-convertion system in BICMOS technology. Together with the AM/FM IC T4258 or U4255BM, it performs a complete AM/FM car radio front-end, which is recommended also for RDS (Radio Data System) applications. It is controlled by a 3-wire bus and also contains switches and Digital to Analog Converters (DACs) for software-controlled alignment of the AM/FM tuner. The U4256BM-R is the pin-compatible succesor IC of U4256BM-N. Frequency Synthesizer for Radio Tuning U4256BM-R Preliminary Pin Configuration CLK DATA OSCIN OSCOUT 17 16 15 14 13 12 4 5 6 9 DAC3 VS SWO1 7 8 DAC2 SWO2 SWO3 SWO4 10 U4256BM-R 11 GND EN 18 3 DAC1 V5 FMOSCIN 19 2 PD MX2LO GNDan 20 1 PDO Figure 1. Pinning SSO20 Rev. 4562C–AUDR–08/04 1 Pin Description Pin Symbol 1 PDO Phase detector output Function 2 PD Pulsed current output 3 DAC1 Digital-to-analog converter 1 4 DAC2 Digital-to-analog converter 2 5 DAC3 6 VS 7 SWO1 Switching output 1 8 SWO2 Switching output 2 9 SWO3 Switching output 3 10 SWO4 Switching output 4 Digital-to-analog converter 3 Supply voltage analog part 11 GND 12 OSCOUT Reference oscillator output Ground, digital part 13 OSCIN Reference oscillator input 14 V5 15 MX2LO 16 DATA Data input 17 CLK Clock 18 EN 19 FMOSCIN 20 GNDan Capacitor band gap Oscillator buffer output Enable FM-oscillator input Ground, analog part Figure 2. Block Diagram SWO1 SWO2 SWO3 SWO4 7 8 9 10 Tuning OSCIN OSCOUT MX2LO CLK DATA EN 13 12 15 Oscillator Switching outputs DAC3 3-bit V OSC buffer 17 16 18 3Wbus interface Rdivider FMOSCIN 19 FMpreamp Ndivider Phase detector 20 2 14 V5 DAC2 4 DAC1 3 V 2 DAC1 PDO PD 6 11 GND DAC2 Ref 1 Current sources DAC3 Ref DAC AM/FM Bandgap GNDan 5 VS U4256BM-R 4562C–AUDR–08/04 U4256BM-R Functional Description For a tuned FM-broadcast receiver, the following parts are needed: • Voltage-Controlled Oscillator (VCO) • Antenna Amplifier Tuned Circuit • RF Amplifier Tuned Circuit Typical modern receivers with electronic tuning are tuned to the desired FM frequency by the frequency synthesizer IC U4256BM-R. The special design allows the user to build software-controlled tuner alignment systems. Two programmable DACs (Digital-toAnalog Converter) support the computer-controlled alignment. The output of the PLL is a tuning voltage which is connected to the VCO of the receiver IC. The output of the VCO is equal to the desired station frequency plus the IF (10.7 MHz). The RF and the oscillator signal (VCO) are both input to the mixer that translates the desired FM channel signal to the fixed IF signal. For FM, the double-conversion system of the receiver requires exactly 10.7 MHz for the first IF frequency, which determines the center frequency of the software-controlled integrated second IF filter. If this oscillator tuning feature is not used, the internal capacities have to be switched off and the oscillator has to be operated with high-quality external capacities to ensure that the operational frequency is exactly 10.250 MHz. When dimensioning the oscillator circuit, it is important that the additional capacities enable the oscillator to operate through its complete tracking range. The oscillating ability depends very strongly on the used crystal oscillator. Initializing the oscillator should be established without switching any additional capacities to guarantee that the oscillator starts to operate properly. Due to the lower quality of the integrated capacities compared to discrete capacities, the amount of the switched integrated capacities should always be minimized. (If necessary reduce tracking range or use another crystal oscillator.) The U4256BM-R has a very fast response time of maximum 800 µs (at 2 mA, fStep = 50 kHz, measured on MPX signal). It performs a high signal to noise ratio. Only one supply voltage is necessary, due to a integrated band gap. Input/Output Interface Circuits PDO (Pin 1) PDO is the buffer amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. PD (Pin 2) PD is the current charge pump output of the PLL. The current can be controlled by setting the Bits. The loop filter has to be designed corresponding to the choosen pump current and the internal reference frequency. A recommendation can be found in the application circuit. The charge-pump current can be choosen by setting the Bits 71 and 70 as following: IPD (µA) B71 B70 25 0 0 100 0 1 500 1 0 2000 1 1 3 4562C–AUDR–08/04 Figure 3. Internal Components at PDO Connection VS VS VS PDO PD FMOSCIN (Pin 19) FMOSCIN is the preamplifier input for the FM oscillator signal. Figure 4. Internal Components at FMOSCIN V5 FMOSCIN MX2LO (Pin 15) MX2LO is the buffered output of the crystal oscillator. This signal can be used as a reference frequency for U4255BM or T4258. The oscillator buffer output can be switched by the OSCB Bit as following (Bit 69) MX2LO AC Voltage B69 ON 0 OFF 1 Figure 5. Internal Components at MX2LO V5 V5 OSCIN MX2LO 4 U4256BM-R 4562C–AUDR–08/04 U4256BM-R Function of DAC1, 2 in FM and AM Mode (Pin 3 and Pin 4) For automatic tuner alignment, the DAC1 and DAC2 of the U4256BM-R can be controlled by setting gain of VPDO and offset values. The following figure shows the principle of the operation. In FM Mode the gain is in the range of 0.69 × V(PDO) to 2.16 × V(PDO). The offset range is +0.56 V to -0.59 V. For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filters. For alignment, offset and gain is set for having the best tuner tracking. Figure 6. Principle Operation for Alignment Bit 34 PDO (FM) Gain +/- DAC1,2 Vref (AM) (3 V) Offset The DAC mode can be controlled by setting the Bit 34 as following: DAC Mode B34 FM 0 AM 1 If Bit 34 = 1 (AM Mode), the DAC1, DAC2 can be used as standard DAC converters. The internal voltage of 3 V is connected to the gain- and offset-input of DAC1 and DAC2 (only in AM Mode). The gain is in the range of 0.46 × 3 V to 3.03 × 3 V. The offset range is +1.46 V to -1.49 V. Figure 7. Internal Components at DAC1,2 Output VS DAC1,2 5 4562C–AUDR–08/04 DAC 1, 2 in FM Mode (Pin 3 and Pin 4) The gains of DAC1 and DAC2 have a range of 0.69 × V(PDO) to 2.16 × V(PDO). V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps. So one step is approximately (2.16 - 0.46) × V(PDO) / 255 = 0.005764 × V(PDO). The gain of DAC1 can be controlled by the Bits 36 to 43 (G-20 to G-27) and the gain of DAC2 by the Bits 0 to 7 (G20 to G-27) as following: Gain DAC1 Approximately B43 B42 B41 B40 B39 B38 B37 B36 Decimal Gain Gain DAC2 Approximately 0.69 × V(PDO) B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 0 Decimal Gain 0 0.69576 × V(PDO) 0.70153 × V(PDO) 0.70729 × V(PDO) ... 0.99549 × V(PDO) ... 2.14847 × V(PDO) 2.15424 × V(PDO) 2.16 × V(PDO) 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 1 1 ... 0 ... 0 1 1 1 0 1 ... 1 ... 1 0 1 1 2 3 ... 53 ... 253 254 255 Offset = 31 (intermediate position) The offset of DAC1 and DAC2 has a range of 0.56 V to -0.59 V. This range is divided into 64 steps. So one step is approximately 1.15 V/ 63 = 18.25 mV. The offset DAC1 can be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8 to 13 (O-20 to O-25) as following: Offset DAC1 Approximately Offset DAC2 Approximately 0.56 V 0.5417 V 0.5235 V 0.5052 V ... +0.0059 V ... 0.5535 V -0.5717 V -0.59 V B49 B48 B47 B46 B45 B44 B13 0 B12 0 B11 0 B10 0 B9 0 B8 0 Decimal Gain Decimal Gain 0 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 1 1 ... 1 ... 0 1 1 1 0 1 ... 1 ... 1 0 1 1 2 3 ... 31 ... 61 62 63 Gain = 53 (intermediate position) 6 U4256BM-R 4562C–AUDR–08/04 U4256BM-R DAC 1, 2 in AM Mode (Pin 3 and Pin 4) In AM mode the DAC input voltage V(PDO) is internal connected to 3 V. The gains of DAC1 and DAC2 have a range of 0.46 × 3 V to 3.03 × 3 V. V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps. So one step is approximately (3.03 - 0.46) × 3 V/255 = 0.01007 × 3 V. The gain of DAC1 can be controlled by the Bits 36 to 43 (G-2 0 to G-2 7 ) and the gain of DAC2 by the Bits 0 to 7 (G-2 0 to G-2 7 ) as following: Gain DAC1 Approximately B43 B42 B41 B40 B39 B38 B37 B36 Decimal Gain Gain DAC2 Approximately 0.4607 × 3 V B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 0 Decimal Gain 0 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 1 1 ... 0 ... 0 1 1 1 0 1 ... 1 ... 1 0 1 1 2 3 ... 53 ... 253 254 255 0.4710 × 0.4812 × 0.4915 × ... 1.0029 × ... 3.0097 × 3.0196 × 3.0296 × 3V 3V 3V 3V 3V 3V 3V Offset = 31 (intermediate position) Remark: V(PDO) is 3 V in AM mode. The offset of DAC1 and DAC2 has a range of +1.46 V to -1.49 V. This range is divided into 64 steps. So one step is approximately 2.95 V/ 63 = 46.8 mV. The offset DAC1 can be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8 to 13 (O-20 to O-25) as following: Offset DAC1 Approximately Offset DAC2 Approximately 1.4606 V 1.4138 V 1.3665 V 1.3196 V ... -0.0079 V ... -1.3975 V -1.4447 V -1.4917 V B49 B48 B47 B46 B45 B44 B13 0 B12 0 B11 0 B10 0 B9 0 B8 0 Decimal Gain Decimal Gain 0 0 0 0 ... 0 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 0 0 ... 1 ... 1 1 1 0 1 1 ... 1 ... 0 1 1 1 0 1 ... 1 ... 1 0 1 1 2 3 ... 31 ... 61 62 63 Gain = 53 (intermediate position) 7 4562C–AUDR–08/04 DAC3 (Pin 5) The DAC3 output voltage can be controlled by the Bits P-20 to P-22 (Bits 66 to 68) as following: DAC3 Offset Approximately B68 B67 B66 0.55 V 0 0 0 1.25 V 0 0 1 1.90 V 0 1 0 2.60 V 0 1 1 3.30 V 1 0 0 4.10 V 1 0 1 4.80 V 1 1 0 5.45 V 1 1 1 Figure 8. Internal Components at DAC3 VS DAC3 EN, DATA, CLK (Pin 16-18) All functions can be controlled via a 3-wire bus consisting of ENABLE, DATA and CLOCK. The bus is designed for microcontrollers which operate with 3 V supply voltage. Details of the data transfer protocol are shown in the table ‘3-wire Bus Description’. Figure 9. Internal Components at EN, DATA, CLK V5 EN DATA CLK 8 U4256BM-R 4562C–AUDR–08/04 U4256BM-R SWO1, 2, 3 and 4 (Pin 7-10) All switching outputs are ‘open drain’ and can be set and reset by software control. Details are described in the data transfer protocol. The switching output SWO1 to SWO4 can be controlled as following (Bits 30 to 33): Switch Output B30 + X SWOx = ON (switch to GND) 0 SWOx = OFF 1 X = 0 to 3 Figure 10. Internal Components at SWO1, 2, 3 and 4 SWO1 SWO2 SWO3 SWO4 OSCIN, OSCOUT (Pin 12 and Pin 13) I A crystal resonator (up to 15 MHz) is connected between OSCIN and OSCOUT in order to generate the reference frequency. By using the U4256BM-R in connection with U4255BM or T4258, the crystal frequency must be 10.25 MHz. The complete application circuit is shown in Figure 15. If a reference is available, it can be applied at OSCIN. The minimum voltage should be 100 mVrms. In this case, Pin OSCOUT has to be open. The tuning capacity for the crystal oscillator has a range of 0.5 pF to 71.5 pF. The values are coded binary. The tuning can be controlled by the Bits 78 to 85 as following: B85 = 1 [pF] B85 = 0 [pF] B84 B83 B82 B81 B80 B79 B78 0 0.5 1.0 1.5 ... 63.0 63.5 8.0 8.5 9.0 19.5 ... 71.0 71.5 1 1 1 1 ... 0 0 1 1 1 1 ... 0 0 1 1 1 1 ... 0 0 1 1 1 1 ... 0 0 1 1 1 1 ... 0 0 1 1 0 0 ... 0 0 1 0 1 0 ... 0 0 9 4562C–AUDR–08/04 Figure 11. Internal Components at OSCIN and OSCOUT V5 OSCIN V5 OSCOUT Figure 12. Internal Connection of Tuning Capacity for Crystal Oscillator Cx1 Cx2 INV 8pF 32pF ... 0.5 pF 0.5 pF 32pF 8pF ... B78 B84 B85 10 U4256BM-R 4562C–AUDR–08/04 U4256BM-R Application Information Figure 13. FMOSCIN Sensitivity Vi (mVrms on 50 Ω) 150 100 50 0 0 3-wire Bus Description 20 40 60 80 100 120 Frequency (MHz) 140 160 The register settings of U4256BM-R are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all the bits of one register. The different registers available (see table Data Transfer) are addressed by the length of the command (number of transmitted bits) and by two address bits, that are unique to each register of a given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a rising edge on the enable line (EN) and ends with a falling edge on EN. EN has to be kept HIGH during the bus command. The sequence of transmitted bits during one command starts with the LSB of the first byte and ends with the MSB of the last byte of the register addressed. To transmit one bit (0/1) DATA has to be set to the appropriate value (LOW/HIGH) and a LOW to HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW to HIGH transitions on CLK during the HIGH period of EN is used to determine the length of the command. The bus protocol and the register addressing of U4256BM-R are compatible to the addressing used in U4255BM and T4258. That means U4256BM-R and U4255BM (or T4258) can be operated on the same 3-wire bus as shown in the application circuit. 11 4562C–AUDR–08/04 Figure 14. 3-wire Bus Timing Diagram tF tR VHIGH Enable VLOW tHEN tS tR tF VHIGH Data VLOW tHDA tS tR tF VHIGH Clock VLOW tH tL Figure 15. 3-wire Pulse Diagram 16-bit command EN DATA LSB BYTE 1 MSB LSB BYTE 2 MSB CLK 24-bit command EN DATA LSB MSB LSB BYTE 1 BYTE 2 MSB LSB BYTE 3 MSB CLK e.g. R-Divider 20 21 22 23 24 25 26 27 R-Divider 12 28 29 2 10 2 11 2 12 2 13 2 14 2 15 P-2 0 1 2 P-2 P-2 DAC3 OSCB IPD Status 0 0 0 Addr. U4256BM-R 4562C–AUDR–08/04 U4256BM-R Data Transfer Table 1. Control Registers A MSB BYTE 3 ADDR. 0 LSB STATUS 0 0 IPD B71 B70 MSB BYTE 2 LSB DAC3 MSB BYTE 1 LSB R-Divider OSCB 0=on, 1=off P-22 P-21 P-20 215 214 213 212 210 211 29 28 27 26 25 24 23 22 21 20 B69 B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50 LSB MSB LSB MSB B MSB BYTE 3 ADDR. 0 1 BYTE 2 STATUS 1 0 B35 AM=1 SWO4 SWO3 SWO2 SWO1 FM=0 0=on, 0=on, 0=on, 0=on, DAC 1=off 1=off 1=off 1=off B34 B33 BYTE 1 LSB N-Divider B32 B31 215 214 213 212 210 211 29 28 27 26 25 24 23 22 21 20 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 LSB MSB C MSB BYTE 2 ADDR. 0 0 BYTE 1 DAC1 OFFSET LSB DAC1 GAIN O-25 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 LSB MSB D MSB BYTE 2 ADDR. 0 1 BYTE 1 DAC2 OFFSET LSB DAC2 GAIN O-25 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 LSB MSB E MSB BYTE 2 ADDR. 1 0 BYTE 1 Oscillator tuning function LSB Not used 8pF 32pF 16pF 8pF 4pF 2pF 1pF 0.5pF X X X X X X B85 B84 B83 B82 B81 B80 B79 B78 B77 B76 B75 B74 B73 B72 Absolute Maximum Ratings Parameters Symbol Value Unit Analog supply voltage Pin 6 VS 8 to 12 V Input voltage BUS Pins 16, 17 and 18 VI -0.3 to +5.3 V Output current switches (see Figure 10) Pins 7, 8, 9 and 10 IO -1 to +5 mA Drain voltage switches Pins 7, 8, 9 and 10 VOD 15 V Ambient temperature range Tamb -40 to +85 °C Storage temperature range Tstg -40 to +125 °C Tj 125 °C VESD 300 V Junction temperature Electrostatic handling M.M. 13 4562C–AUDR–08/04 Thermal Resistance Parameters Symbol Value Unit RthJA 140 K/W Junction ambient, when soldering to PCB Operating Range All voltages are referred to GND (Pin 11) Parameters Supply voltage range Symbol Min. Typ. Max. Unit VS 8 8.5 12 V Tamb -40 +85 °C MHz Pin 6 Ambient temperature Input frequency FMOSCIN Pin 19 fin 70 160 SF 2 65535 fXTAL 0.1 15 Programmable N, R divider Crystal reference oscillator Pins 12 and 13 MHz Electrical Characteristics Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C. No. 1 1.1 2 2.1 3 3.1 4 Parameters Min. Typ. Max. Unit Type* 6 VS 8 8.5 12 V A 6 IS 5 10 25 mA A f = 0.1 to 15 MHz 13 OSC 100 mVrms B At Pin15: 47 pF and 1 kΩ 15 vMX2LO 80 120 200 mVpp B 15 VMX2LO 1.8 2.0 2.2 V A 19 FMOSC FMOSC 40 150 mVrms mVrms B 2 ± IPD 20 25 30 µA A 2 ± IPD 80 100 120 µA A 2 ± IPD 400 500 600 µA A 2 ± IPD 1500 2000 2400 µA A 2 ± IPDL 20 nA A Analog supply voltage Analog supply current OSCIN Input voltage OSC Buffer (MX2LO) 4.2 Output DC voltage 6 Symbol Supply Current Output AC voltage 5.1 Pin Supply Voltage 4.1 5 Test Conditions FMOSCIN Input voltage f = 70 to 120 MHz f = 120 to 160 MHz Pulsed Current Output PD 6.1 Output current Bit 71, 70 = ‘00’ PD = 2.5 V 6.2 Output current Bit 71, 70 = ‘01’ PD = 2.5 V 6.3 Output current Bit 71, 70 = ‘10’ PD = 2.5 V 6.4 Output current Bit 71, 70 = ‘11’ PD = 2.5 V 6.5 Leakage current PD = 2.5 V *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 14 U4256BM-R 4562C–AUDR–08/04 U4256BM-R Electrical Characteristics (Continued) Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C. No. 7 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* PDO 7.1 Saturation voltage HIGH 3, 4 8.0 8.5 V A 7.2 Saturation voltage LOW 3, 4 0 0.4 V A 100 nA A 400 mV A ±1 mA C VS-0.6 V A 8 SWO1, SWO2, SWO3, SWO4 (Open Drain) 8.1 Output leakage current HIGH Pin 7,8,9,10 over R against 8.5 V 7, 8, 9, 10 ISWOH 8.2 Output voltage LOW I = 1 mA 7, 8, 9, 10 VSWOL 9 DAC1, DAC2 9.1 Output current 3, 4 IDAC1, 2 9.2 Output voltage 3, 4 VDAC1, 2 9.3 Maximum offset range (FM) offset = 0, gain = 53 9.4 Minimum offset range (FM) offset = 63, gain = 53 9.5 Maximum gain range (FM) gain = 255, offset = 31 9.6 Minimum gain range (FM) gain = 0, offset = 31 10 DAC3 100 0.3 3, 4 0.45 0.56 0.65 V A 3, 4 -0.45 -0.57 -0.65 V A 3, 4 0.63 0.69 0.75 A 3, 4 2.1 2.16 2.23 A 10.1 Output current 5 IDAC3 ±1 mA C 10.2 Output voltage Bit 68-66: 000 5 VDAC3 0.4 0.55 0.7 V A 10.3 Output voltage Bit 68-66: 001 5 VDAC3 1.1 1.25 1.4 V A 10.4 Output voltage Bit 68-66: 010 5 VDAC3 1.8 1.90 2.1 V A 10.5 Output voltage Bit 68-66: 011 5 VDAC3 2.4 2.60 2.8 V A 10.6 Output voltage Bit 68-66: 100 5 VDAC3 3.2 3.30 3.5 V A 10.7 Output voltage Bit 68-66: 101 5 VDAC3 3.8 4.10 4.3 V A 10.8 Output voltage Bit 68-66: 110 5 VDAC3 4.5 4.80 5.0 V A 10.9 Output voltage Bit 68-66: 111 5 VDAC3 5.2 5.45 5.7 V A 16-18 VBUSH VBUSL 2.7 -0.3 5.3 0.8 V V A 1.0 MHz A 250 250 ns ns D 11 3-wire Bus, ENABLE, DATA, CLOCK 11.1 Input voltage HIGH LOW 11.2 Clock frequency 11.3 Period of CLK HIGH LOW 17 tH tL 11.4 Rise time EN, DATA, CLK 16-18 tr 400 ns D 11.5 Fall time EN, DATA, CLK 16-18 tf 100 ns D 17 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 15 4562C–AUDR–08/04 Electrical Characteristics (Continued) Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C. No. Parameters 11.6 Set-up time 11.7 11.8 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 16-18 ts 100 ns D Hold time EN 18 tHEN 250 ns D Hold time DATA 16 tHDA 0 ns D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Figure 16. Application Circuit EN CLK DATA GND C 12 R5 C9 5.1 k *) 100 nF *) *) depends on crystal C8 47 pF 20 C1 19 18 17 R2 16 10.25 MHz 15 14 13 BUS 12 11 OSC 600 10 pF LOGIC fOSC FM DAC's Switches VCO 1 2 3 5 4 Vtune 6 C 16 R4 8.2 k 8 9 10 SWO1 SWO2 SWO3 SWO4 C6 C 15 330 pF C 14 C7 10 nF 7 C5 C4 10 nF 10 nF 100 nF 100 mF R3 10 nF DAC1 100 DAC2 DAC3 VS 8 ... 12 V 16 U4256BM-R 4562C–AUDR–08/04 4562C–AUDR–08/04 FM 75 Ohm Ant R307 47 T111 J109 T302 BC848 R105 100 C311 100n D302 S391D BC 858C S391D 4u7 L301 D301 220n 10n C315 C302 R306 470k 220n 2k2 R115 1k R103 1k 10n R104 470 F102 68k R102 390 R313 470n C111 C112 10u 2u2 C106 L102 10p 3p9 C102 2 43 F101 S391D 10n D103 C103 D101 BB804 27p C104 C56 10n 18p C107 1n 6p8 BB804 D102 1 44 100p C in F201 F201 C108 C109 C113 100n 10n C209 T101 BFR93A R112 47k 12p C306 C117 T102 BC858 100uH C316 R308 T301 L303 2m2 2k2 R311 6p8 C319 L302 R29 10 4 41 68k R122 68k 5 40 R121 C314 10n C110 4n7 3 42 10n C307 100n C201 C308 100n 6 39 R34 27 7 38 12 C116 100n C115 100n R151 8k2 14 31 15 30 C152 330p 1n C134 R131 5k6 BB804 F131 1 20 47p 22p C131C132 13 32 220n C207 220n C208 D131 C133 6p8 220n 11 22u 10 C114 9 33 U4255BM 10u 35 34 C205 10n C206 1k5 R305 X301 C203 8 C204 470n 37 36 1u R111 200k C202 KR201 R304 1k3 3 18 17 28 C158 10n 10n C151 2 19 16 29 KR202 4 20 25 15 1n 10n C312 8 13 9 12 Q151 10 11 12p* 12p* 10,25MHz C153 C154 22 23 F302 R106 10 C157 SWO1 SWO3 SWO2 SWO4 7 10n 6 14 100n 10n DAC3 5 21 24 C155 U4256BM 16 10n C156 19 26 R303 1k C310 C309 220n C159 17 18 27 KF302 GND EN CLK DATA IF2OUT INT DEV MULTIP VS (+8,5V...10,5V) METER ADJAC MPX *depends on Q151 R152 10 10 R407 U4256BM-R Figure 17. Application Board Schematic 17 Ordering Information Extended Type Number Package Remarks U4256BM-RFS SSO20 Tube U4256BM-RSG3 SSO20 Taped and reeled Package Information 5.7 5.3 Package SSO20 Dimensions in mm 6.75 6.50 4.5 4.3 1.30 0.15 0.05 0.25 0.65 5.85 20 0.15 6.6 6.3 11 technical drawings according to DIN specifications 1 18 10 U4256BM-R 4562C–AUDR–08/04 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom AAvenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 e-mail [email protected] Web Site http://www.atmel.com © Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel ® is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4562C–AUDR–08/04 xM