Order this document by MC34270/D The MC34270 and MC34271 are low power dual switching voltage regulators, specifically designed for handheld and laptop applications, to provide several regulated output voltages using a minimum of external parts. Two uncommitted switching regulators feature a very low standby bias current of 5.0 µA, and an operating current of 7.0 mA capable of supplying output currents in excess of 200 mA. Both devices have three additional features. The first is an ELD Output that can be used to drive a backlight or a liquid crystal display. The ELD output frequency is the clock divided by 256. The second feature allows four additional output bias voltages, in specific proportions to VB, one of the switching regulated output voltages. It allows use of mixed logic circuitry and provides a voltage bias for N–Channel load control MOSFETs . The third feature is an Enable input that allows a logic level signal to turn–“off” or turn–“on” both switching regulators. Due to the low bias current specifications, these devices are ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable. LIQUID CRYSTAL DISPLAY AND BACKLIGHT INTEGRATED CONTROLLER SEMICONDUCTOR TECHNICAL DATA t 32 1 MC34270 and MC34271 Features: FB SUFFIX PLASTIC PACKAGE CASE 873 Uncommitted Switching Regulators Allow Both Positive and Negative Supply Voltages Logic Enable Allows Microprocessor Control of All Outputs Synchronizable to External Clock Mode Commandable for ELD and LCD Interface Frequency Synchronizable PIN CONNECTIONS MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 31 30 29 28 27 26 25 RT Gnd VA Vref EN1 EN2 MOSFET is a trademark of Motorola, Inc. 32 Sync Auxiliary Output Bias Voltages Enable Load Control via N–Channel FETs SW1 1 DS1 DS2 24 2 Ref1 Ref2 23 3 FB1 FB2 22 Symbol Value Unit VDD 16 Vdc PD 1.43 W RθJA RθJC 100 60 °C/W °C/W ISL & ISB 500 mA Output #1 and #2 “Off”–State Voltage VSL 60 Vdc Feedback Enable MOSFETs “Off”–State Voltage VLF 20 Vdc Operating Junction Temperature TJ 125 °C Operating Ambient Temperature TA 0 to +70 °C Device Tstg – 55 to +150 °C MC34270FB Output #1 and #2 Switch Current Storage Temperature Range S2 19 7 D1 D2 18 8 Drv1 V0 6 S1 V1 SS2 20 V2 5 SS1 V3 Power Dissipation and Thermal Characteristics Maximum Power Dissipation Case 873 Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Comp2 21 4 Comp1 V4 Input Voltage VDD Rating Mode • • • • • Low Standby Bias Current of 5.0 µA ELD • • 9 10 11 12 13 14 15 16 ORDERING INFORMATION MC34271FB Operating Temperature Range TA = 0° to +70°C Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA VB 17 Package QFP–32 QFP–32 Rev 1 1 MC34270 MC34271 Representative Block Diagram Vin SW1 VDD 32 EL Panel On/Off EL Control EN1 D1 Circuit #1 PWM 7 S1 26 6 ELD Drv1 9 8 Sync 31 ÷2 OSC ELD EN VDD 27 Ref1 FB1 11 Vin Mode 10 RT 30 VRef VDD D2 Vref 1.25 V 18 Circuit #2 PWM 2 S2 19 3 Comp1 VB 4 µP Control 17 EN2 25 V0 From DAC VB VB 16 Ref2 FB2 23 V1 22 Comp2 15 V0 V1 21 V2 V2 14 BIAS Output Buffers VA = 5.0 V 28 BIAS V3 13 V4 Gnd 29 12 V3 V4 This device contains 350 active transistors. 2 MOTOROLA ANALOG IC DEVICE DATA MC34270 MC34271 ELECTRICAL CHARACTERISTICS (VDD = 6.0 V, for typical values TA = Low to High [Note 1], for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Vref 1.225 1.250 1.275 V Line Regulation (VDD = 5.0 V to 12.5 V) Regline – 2.0 10 mV Load Regulation (IO = 0 to 120 µA) Regload – 2.0 10 mV Vref 1.215 – 1.285 V Input Offset Voltage (VCM = 1.25 V) VIO – 1.0 10 mV Input Bias Current (VCM = 1.25 V) IIB – 120 600 nA Open Loop Voltage Gain (VCM = 1.25 V, VCOMP = 2.0 V) AVOL 80 100 – dB Output Voltage Swing High State (IOH = –100 µA) Low State (IOL = 100 µA) VeOH VeOL VA–1.5 0 4.0 – 5.5 1.0 VA 4.6 5.0 5.4 90 115 140 REFERENCE SECTION Reference Voltage (TJ = 25°C) Total Variation (Line, Load and Temperature) ERROR AMPLIFIERS V BIAS VOLTAGE Voltage (VDD = 5.0 V to 12.5 V, IO = 0) V OSCILLATOR AND PWM SECTIONS Total Frequency Variation Over Line and Temperature VDD = 5.0 V to 10 V, TA = 0° to 70°C, RT = 169 k fOSC kHz Duty Cycle at Each Output Maximum Minimum DCmax DCmin 92 – 95 – – 0 % Sync Input Input Resistance (Vsync = 3.5 V) Minimum Sync Pulse Width Rsync Tp 25 – 50 1.0 100 – kΩ µs Output Voltage – “On”–State (Isink = 200 mA) VOL – 150 250 mV Output Current – “Off”–State (VOH = 40 V) IOH – 0.1 1.0 µA Rise and Fall Times tr, tf – 50 – ns Output Voltage – “On”–State (Isink = 100 µA) VOL – 30 100 mV Output Voltage – “On”–State (Isink = 50 mA) VOL – 2.0 2.5 V Output Voltage – “Off”–State (Isource = –100 µA) VOH VDD–0.5 5.9 – V Output Voltage – “Off”–State (Isource = – 50 mA) VOH VDD–3.5 3.3 – V Output Voltage – “Low”–State (Isink = 1.0 mA) VfeOL – 10 100 mV Output Current – “Off”–State (VOH = 12.5 V) IfeOH – 0.6 1.0 µA VswOH VswOL 5.5 0 5.9 0.1 6.0 0.2 Rds Ilkg V0 R0 0 0 29.5 20 2.0 0.1 29.9 40 10 2.0 30 60 OUTPUT MOSFETs EL DISCHARGE OUTPUT (ELD) AND DRV1 FEEDBACK ENABLE SWITCHES (DS1, DS2) SWITCHED VDD OUTPUT (SW1) Output Voltage Switch “On” (EN1 = 1, Isource = 100 µA) Switch “Off” (EN1 = 0, Isink = 100 µA) V AUXILIARY VOLTAGE OUTPUTS V0 Enable Switch “On”–Resistance: VB to V0 “Off”–State Leakage Current (VB = 10 V) V0 Voltage (VB = 30 V, Isource = 0 mA) V0 Resistance (Isource = 4.0 mA) Ω µA V Ω NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible. MOTOROLA ANALOG IC DEVICE DATA 3 MC34270 MC34271 ELECTRICAL CHARACTERISTICS (continued) (VDD = 6.0 V, for typical values TA = Low to High [Note 1], for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Ro Iss 0.0565 0.0500 0.1135 0.1010 0.1135 0.1010 0.0565 0.0500 20 5.0 0.0580 0.0520 0.1160 0.1035 0.1160 0.1035 0.0580 0.0520 40 10 0.0595 0.0535 0.1185 0.1065 0.1185 0.1065 0.0595 0.0535 60 20 Ω mA Input Low State VIL 0 – 0.8 V Input High State VIH 2.0 – 6.0 V Input Impedance Rin 25 50 100 kΩ Ichg 0.5 1.0 2.5 µA Idschg 250 650 – µA ICC – – 2.0 3.0 5.0 15 µA VDD Current Backlight “On” (EN1 = 1; EN2 = 0) ICC – 0.7 3.0 mA VDD Current LCD “On” (No Inductor) (EN1 = 0; EN2 = 1) ICC – 0.9 2.0 mA IO – 1.2 3.0 mA AUXILIARY VOLTAGE OUTPUTS V1, V2, V3, V4 Outputs 1–V1/V0 Ratio: MC34270 MC34271 1–V2/V0 Ratio: MC34270 MC34271 V3/V0 Ratio: MC34270 MC34271 V4/V0 Ratio: MC34270 MC34271 Output Resistance (Isource = 4.0 mA) Output Short Circuit Current LOGIC INPUTS (EN1, EN2, MODE) SOFT START CONTROL (SS1,SS2) Charge Current (Capacitor Voltage = 1.0 V to 4.0 V) Discharge Current (Capacitor Voltage = 1.0 V) TOTAL SUPPLY CURRENT VDD Current Standby Mode (EN1 = EN2 = 0) VDD = 6.0 V VDD = 16 V VB Current (V0 = 35 V) NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Figure 2. Error Amp Open Loop Gain and Phase versus Frequency VDD = 6.0 V TA = 25°C 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 VComp, COMPENSATION VOLTAGE (V) 4 0 100 AVOL, OPEN LOOP VOLTAGE GAIN (dB) DC, SWITCH OUTPUT DUTY CYCLE 1.0 4.5 VDD = 6.0 V VComp = 2.5 V RL = Open TA = 25°C 80 Gain 60 Phase 40 30 60 90 20 120 0 150 – 20 10 100 1.0 k 10 k 100 k θ, EXCESS PHASE (° ) Figure 1. Switch Output Duty Cycle versus Compensation Voltage 180 1000 k f, FREQUENCY (Hz) MOTOROLA ANALOG IC DEVICE DATA MC34270 MC34271 Figure 3. Reference Voltage Change versus Reference Current Figure 4. Quiescent Current versus Supply Voltage QUIESCENT CURRENT (mA) – 5.0 –10 VA –15 – 20 VDD = 6.0 V TA = 25°C – 25 – 30 1.0 0 2.0 3.0 4.0 FET DRAIN VOLTAGE (V) 1.5 1.0 1.0 Standby Current EN1 and EN2 = 0 0.5 4.0 6.0 8.0 RT = 169 k No Loading TA = 25°C 10 12 0.2 18 16 14 0.6 Figure 5. FET Drain Voltage versus Sink Current Figure 6. ELD and DRV1 Switch Output Source and Sink Saturation versus Current 0.08 0.04 VDD = 6.0 V TA = 25°C 50 0 100 150 200 0 2.0 VDD Sink Saturation –1.0 1.0 Source Saturation – 3.0 – 4.0 0 15 OSCILLATOR FREQUENCY CHANGE (kHz) VDD = 6.0 V VA 0.15 0.10 Vref 0.05 0 – 0.05 0 10 20 30 40 50 TA, AMBIENT TEMPERATURE (°C) MOTOROLA ANALOG IC DEVICE DATA 30 0 60 45 Figure 8. Oscillator Frequency Variation versus Temperature 0.30 0.20 0.5 ISource, SWITCH OUTPUT CURRENT (mA) Figure 7. Vref and VA Variation versus Temperature 0.25 VDD = 6.0 V 1.5 TA = 25°C – 2.0 ID, DRAIN CURRENT (mA) VOLTAGE VARIATION (V) 1.4 EN1 = 1 and EN2 = 0 VDD, SUPPLY VOLTAGE (V) 0.12 – 0.10 1.8 I, CURRENT DRAW (mA) 0.16 0 EN1 and EN2 = 1 2.0 0 2.0 5.0 Vsat, SWITCH OUTPUT SOURCE SATURATION (V) OUTPUT VOLTAGE DROP (mV) Vref STANDBY SUPPLY CURRENT (µ A) 2.2 2.5 Vsat , SWITCH OUTPUT SINK SATURATION (V) 0 60 70 8.0 VDD = 6.0 V RT = 169 k 6.0 4.0 2.0 0 – 2.0 – 4.0 – 6.0 – 8.0 0 10 20 30 40 50 60 70 TA, AMBIENT TEMPERATURE (°C) 5 MC34270 MC34271 Figure 10. VA, Vref versus VDD Figure 9. Frequency versus Timing 5.0 REFERENCE VOLTAGE (V) FREQUENCY (kHz) 1000 VDD = 6.0 V TA = 25°C 100 10 0 100 1000 RT = 169 k TA = 25°C 4.0 VA 3.0 2.0 1.0 0 Vref 0 TIMING RESISTANCE (kΩ, s) 1.0 2.0 3.0 4.0 5.0 6.0 VDD LEVEL (V) OPERATING DESCRIPTION The MC34270 and MC34271 series are monolithic, fixed frequency power switching regulators specifically designed for dc to dc converter and battery powered applications. These devices operate as fixed frequency, voltage mode regulators containing all the active functions required to directly implement step–up, step–down and voltage inverting converters with a minimum number of external components. Potential markets include battery powered, handheld, automotive, computer, industrial and cost sensitive consumer products. A description of each section is given below with the representative block diagram shown in Figure 9. Oscillator The oscillator frequency is programmed by resistor RT. The charge to discharge ratio is controlled to yield a 95% maximum duty cycle at the switch outputs. During the fall time of the internal sawtooth waveform, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gates high, disabling the output switching MOSFETs. The internal sawtooth waveform has a nominal peak voltage of 3.3 V and a valley voltage of 1.7 V. Pulse Width Modulators Both pulse width modulators consist of a comparator with the oscillator ramp voltage applied to the noninverting input, while the error amplifier output is applied to the inverting input. A third input to the comparator has a 0.5 mA typical current source that can be used to implement soft start. Output switch conduction is initiated when the ramp waveform is discharged to the valley voltage. As the ramp voltage increases to a voltage that exceeds the error amplifier output, the latch resets, terminating output MOSFET conduction for the duration of the oscillator ramp. This PWM/latch combination prevents multiple output pulses during a given oscillator cycle. Each PWM circuit is enabled by a logic input. When disabled, the entire block is turned off, drawing only leakage current from the power source. Shared circuits, like the 6 reference and oscillator, can be activated by either EN1 or EN2. Circuit #1 has an ELD output which may be used to drive an LCD or backlight. Its output frequency is the oscillator frequency divided by 1024. Error Amplifiers and Reference Each error amplifier is provided with access to both inverting and noninverting inputs, and the output. The Error Amplifiers’ Common Mode Input Range is 0 to 2.5 V. The amplifiers have a minimum dc voltage gain of 60 dB. The 1.25 V reference has an accuracy of ± 4.0% at room temperature. External loop compensation is required for converter stability. A simple low–pass filter is formed by connecting a resistive divider from the output to the error amplifier inverting input, and a series resistor–capacitor from the error amplifier output also to the to the inverting input. The step down converter is easiest to compensate for stability. The step–up and voltage inverting configurations, when operated as continuous conduction boost or flyback converters, are more difficult to compensate, and may require a lower loop design bandwidth. MOSFET Switch Outputs The output MOSFETs are designed to switch a maximum of 60 V, with a peak drain current capability of 500 mA. In circuit #1 an additional DRV1 output is provided for interfacing with an external MOSFET.The gates of the MOSFETs are held low when the circuit is disabled. Auxiliary Output Voltages Output voltages V0 through V4 are provided for use as references or bias voltages. V0 is the circuit #2 output voltage, when an internal FET switch is activated. The other auxiliary output voltages are proportional to VB. The amplifiers for V1 and V2 are powered from V0, while the amplifiers for V3 and V4 are powered from VDD. MOTOROLA ANALOG IC DEVICE DATA MC34270 MC34271 Figure 11. Representative Block Diagram Electroluminescent Backlight Configuration SW1 Circuit #1 Bias Supply 32 EL Panel 1 Î Î EN1 26 D1 En DS1 VDD 8 Drv1 7 S Q ÷N ELD 9 VDD ÷2 OSC 31 Sync Mode 10 D2 Vref 1.25 V 27 Q R En 2 3 FB1 DAC S2 19 ÎÎ ÎÎ VDD 4 Comp1 SS1 5 VB 18 S Ref1 Brightness VDD 11 30 RT 169 k “On/Off” S1 6 R VDD2 Circuit #2 Bias Supply Ref2 23 22 FB2 Comp2 21 SS2 20 VB VB 6.0 V to 30 V 17 V0 V0 16 DS2 V1 V1 24 15 V2 V2 25 EN2 14 VA 28 Gnd 29 MOTOROLA ANALOG IC DEVICE DATA BIAS VDD2 V3 V3 13 VDD2 V4 LCD Display V4 12 7 MC34270 MC34271 Figure 12. Auxiliary Supply Configuration 12 V SW1 Circuit #1 Bias Supply 32 D1 En DS1 1 Î Î EN1 26 VDD 8 Drv1 2 3 LCD Contrast DAC ELD 9 VDD 5.0 V to 16 V 11 Mode 10 D2 Vref 1.25 V 18 S Ref1 R En FB1 S2 19 Q Î ÎÎ Î VDD 4 Comp1 SS1 5 VB ÷N 30 RT 27 12 V S1 6 OSC 31 Sync 169 k Q R VDD ÷2 – 27 V 7 S VDD2 Circuit #2 Bias Supply Ref2 23 22 FB2 Comp2 21 SS2 20 VB VB 6.0 V to 30 V 17 V0 V0 16 DS2 V1 V1 24 15 25 EN2 V2 V2 14 VA 28 Gnd 29 8 BIAS VDD2 V3 V3 13 VDD2 V4 LCD Display V4 12 MOTOROLA ANALOG IC DEVICE DATA MC34270 MC34271 Figure 13. MC34270 Incandescent Backlight Configuration Vin 5.0 V to 16 V MC34270 SW1 Circuit #1 Bias Supply 32 D1 En DS1 1 Î Î EN1 26 VDD 8 Drv1 ÷2 7 S Q S1 6 R ÷N ELD 9 VDD OSC 31 Sync 11 Mode 10 30 RT 169 k Vref 2 3 D2 Vref 1.25 V 27 Ref1 R En FB1 S2 19 Q Î Î ÎÎ VDD 4 Comp1 SS1 5 LCD Contrast DAC 18 S VDD2 Circuit #2 Bias Supply DS1 1 Ref2 23 22 FB2 Comp2 21 SS2 20 6.0 V to 30 V VB 17 V0 V0 16 DS2 V1 V1 24 15 25 EN2 V2 V2 14 VA 0.1 µF 28 BIAS Gnd 29 MOTOROLA ANALOG IC DEVICE DATA VDD2 V3 V3 13 VDD2 V4 LCD Display V4 12 9 MC34270 MC34271 Figure 14. EL PANEL Drive Circuit Vin 6.0 V + MC34270 or MC34271 10 µF 0.22 µF 200 V MR856 8 2.2 M SW1 Circuit #1 Bias Supply 32 D1 En EN1 26 Î Î ÎÎ Î Î VDD 8 Drv1 9.1 k 4.3 M 15 pF 1.0 k ÷N 4 4T #36 5 9 120T 1 #36 15 k EL PANEL 7 MPSA44 120T #36 2 400 Hz ELD 0.1 µF MR856 1.0 k 11 Mode 10 MTP3055EL 10 D2 18 S R 2.2 k S2 19 Q Î VDD 3 FB1 MMBT2907 4T #36 6 S1 6 R 4 Comp1 SS1 0.1 µF 5 22 k 10 k Q 30 RT Vref Vref 1.25 V 0.1 27 µF 2 Ref1 8.25 k S OSC 31 Sync 160 k 7 VDD ÷2 3 VDD2 Circuit #2 Bias Supply DS1 1 DAC 1.0 k VB 8.2 k Ref2 23 22 FB2 Comp2 21 SS2 20 VB VB 17 V0 V0 16 DS2 V1 V1 24 15 25 EN2 V2 V2 14 VA 28 BIAS Gnd 29 VDD2 V3 V3 13 VDD2 V4 LCD Display V4 12 NOTES::1. Transformer information TDK Core # PC40EEM12.7/13.7–Z Bobbin # BEPC–10–118G 2 mil gap. LP = 1.6 µhy. 2. EL PANEL: DUREL 3/SL ORANGE 10 MOTOROLA ANALOG IC DEVICE DATA MC34270 MC34271 OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 873–01 L 24 17 B DETAIL A 32 D S H A–B V M L 0.20 (0.008) –B– –A– 0.20 (0.008) M C A–B 0.05 (0.002) A–B S D S 16 S 25 B 1 P B 9 8 –D– –A–,–B–,–D– A 0.20 (0.008) M C A–B 0.05 (0.002) A–B S D S S D S DETAIL A S 0.20 (0.008) H A–B M F BASE METAL DETAIL C M J C E –H– –C– SEATING PLANE H M G N DATUM PLANE 0.01 (0.004) D 0.20 (0.008) M C A–B S D S SECTION B–B VIEW ROTATED 90° CLOCKWISE U T R –H– DATUM PLANE K X DETAIL C MOTOROLA ANALOG IC DEVICE DATA Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V X MILLIMETERS MIN MAX 7.10 6.95 7.10 6.95 1.60 1.40 0.273 0.373 1.50 1.30 – 0.273 0.80 BSC 0.20 – 0.119 0.197 0.57 0.33 5.6 REF 8° 6° 0.119 0.135 0.40 BSC 5° 10° 0.15 0.25 8.85 9.15 0.15 0.25 5° 11° 8.85 9.15 1.0 REF INCHES MIN MAX 0.274 0.280 0.274 0.280 0.055 0.063 0.010 0.015 0.051 0.059 – 0.010 0.031 BSC 0.008 – 0.005 0.008 0.013 0.022 0.220 REF 8° 6° 0.005 0.005 0.016 BSC 5° 10° 0.006 0.010 0.348 0.360 0.006 0.010 5° 11° 0.348 0.360 0.039 REF 11 MC34270 MC34271 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 12 ◊ *MC34270/D* MOTOROLA ANALOG IC DEVICE DATA MC34270/D