Features • • • • • • • • • • • • AM/FM Tuner Front End with Integrated PLL AM Up-conversion System (AM-IF: 10.7 MHz) FM Down-conversion System (FM-IF: 10.7 MHz) IF Frequencies up to 25 MHz Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz Fast Fractional PLL (Lock Time < 1 ms) Inclusive Spurious Compensation Fast RF-AGC, Programmable in 1-dB Steps Fast IF-AGC, Programmable in 2-dB Steps Fast Frequency Change by 2 Programmable N-divider Two DACs for Automatic Tuner Alignment High S/N Ratio 3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers-compatible) AM/FM Front End IC Description The T4260 is an advanced AM/FM receiver with integrated fast PLL as a single-chip solution based on Atmel’s high-performance BICMOS II technology. The low-impedance driver at the IF output is designed for the A/D of a digital IF. The fast tuning concept realized in this part is based on patents held by Atmel and allows lock times less than 1 ms for a jump over the FM band with a step width of 12.5 kHz. The AM up-conversion and the FM down-conversion allows an economic filter concept. An automatic tuner alignment is provided by built-in DACs for gain and offset compensation. The frequency range of the IC covers the FM broadcasting band as well as the AM band. The low current consumption helps the designers to achieve economic power consumption concepts and helps to keep the power dissipation in the tuner low. T4260 Pin Description EN 23 22 OSCBUF CLK 24 21 OSCB DATA 25 20 OSCE VRPLL 19 26 18 OSCGND GNDPLL REFFREQ 28 17 AMLF VTUNE 27 IFOUTB 29 16 FMLF IFOUTA 30 15 VSPLL IFAGCFM 14 VRVCO 31 13 SW1 IFAGCA1 RFAGCFM 33 32 IFREF 34 11 12 SW2/AGC RFAGCA2 IFINAM 35 10 IFAGCA2 IFINFM 36 9 AMAGCO VRT 37 8 MXAMIA GNDT 38 7 MXAMIB MXAMOA MXAMOB 40 39 6 5 GNDRF MXFMIB VST 41 4 MXFMIA RFAGCA1 42 3 FMAGCO MXFMOA 2 DAC2 43 1 DAC1 44 MXFMOB Figure 1. Pinning SSO44 Rev. 4528G–AUDR–12/03 Pin Description 2 Pin 1 Symbol DAC1 Function DAC1 output 2 3 DAC2 FMAGCO DAC2 output FM AGC current 4 5 MXFMIA MXFMIB FM mixer input A FM mixer input B 6 7 GNDRF MXAMIB RF ground AM mixer input B 8 9 MXAMIA AMAGCO AM mixer input A AM AGC current 10 11 IFAGCA2 SW2/AGC AM IF-AGC filter 2 Switch 2 / AM AGC voltage 12 13 RFAGCA2 SW1 RF AM-AGC filter 2 Switching output 1 14 15 VRVCO VSPLL 16 17 FMLF AMLF 18 19 VTUNE OSCGND Tuning voltage Oscillator ground 20 21 OSCE OSCB Oscillator emitter Oscillator base 22 23 OSCBUF EN 24 25 CLK DATA 26 27 VRPLL REFFREQ 28 29 GNDPLL IFOUTB PLL ground IF output B 30 31 IFOUTA IFAGCFM IF output A FM IF-AGC filter 32 33 IFAGCA1 RFAGCFM AM IF-AGC filter 1 RF FM-AGC filter 34 35 IFREF IFINAM IF amplifier reference input IF amplifier AM input 36 37 IFINFM VRT IF amplifier FM input Tuner reference voltage 38 39 GNDT MXAMOB Tuner ground AM mixer output B 40 41 MXAMOA VST AM mixer output A Tuner supply voltage 42 43 RFAGCA1 MXFMOA RF AM-AGC filter 1 FM mixer output A 44 MXFMOB FM mixer output B VCO reference voltage PLL supply voltage FM loop filter AM loop filter Oscillator buffer output/input 3-wire bus Enable 3-wire bus Clock 3-wire bus Data PLL reference voltage PLL reference frequency T4260 4528G–AUDR–12/03 T4260 Figure 2. Block Diagram MXFMOB MXAMOA MXFMOA MXAMOB 43 44 40 39 IFAGCFM IFAGCA2 IFOUTA IFOUTB IFAGCA1 IFINAM IFREF ININFM 34 35 29 30 36 31 10 32 41 37 RF/IF SUPPLY 38 14 MXFMIA 4 MXFMIB 5 GNDRF MXAMIB RFAGCA1 42 RFAGCFM 33 RFAGCA2 AMAGCO FMAGCO 15 PLL SUPPLY 7 MXAMIA 26 28 DIV 23 AGC BUS 12 AM VRT GNDT VRVCO AGC 6 8 VST FM N DIV PD 25 DATA 11 SW2/AGC 2 1 R DIV EN CLK 9 3 VRPLL GNDPLL 24 13 SW-AMLF VSPLL SW1 DAC2 DAC1 VCO 22 OSCBUF Functional Description 21 20 19 OSCE OSCB OSCGND 27 16 REFFREQ FMLF 17 AMLF 18 VTUNE The T4260 implements an AM up-conversion reception path from the RF input signal to the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the LO frequency to the AM mixer. The FM reception path generates the same LO frequency from the RF input signal by a down-conversion to the IF output. The IF A/D output is designed for digital signal processing. The IF can be chosen in the range of 10 MHz to 25 MHz. Automatic gain control (AGC) circuits are implemented to control the preamplifier stages in the AM and FM reception paths. For improved performance, the PLL has an integrated special 2-bit shift fractional logic with spurious suppression that enables fast frequency changes in AM and FM mode by a low step frequency (fPDF ). In addition, two programmable DACs (Digital to Analog Converter) support the alignment via a microcontroller. For a double-tuner concept, external voltage can be applied at the input of the DACs, the internal PLL can switched off and the OSC buffer (output) can also be used as input. Several register bits (Bit 0 to Bit 145) are used to control the circuit’s operation and to adapt certain circuit parameters to the specific application. The control bits are organized in four 8-bit, four 16-bit and three 24-bit registers that can be programmed by the 3-wire bus protocol. The bus protocol and the bit-to-register mapping is described in the section “3-wire Bus Description” on page 9. The meaning of the control bits is mentioned in the following sections. 3 4528G–AUDR–12/03 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referred to GND Parameters Analog supply voltage Pins 15 and 41 Symbol Value Unit VST, VSPLL 10 V Maximum power consumption Ptot 1.0 W Ambient temperature range Tamb -40 to +85 °C Storage temperature range Tstg -40 to +150 °C Tj 150 °C Symbol Value Unit RthJA 52 K/W Junction temperature Thermal Resistance Parameters Junction ambient, soldered to PCB Operating Range Parameters Supply voltage range (1) Pins 15 and 41 Symbol Min. Typ. Max. Unit VST, VSPLL 8 8.5 10 V Tamb -40 85 °C Rfi 60 175 MHz Ambient temperature Oscillator frequency Note: Pin 21 1. VST and VSPLL must have the same voltage. Electrical Characteristics Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters 1 Power Supply 1.1 Supply voltage 1.2 Supply current 2 Test Conditions AM and FM mode, VS = 10 V Pin Symbol Min. Typ. Max. Unit Type* 15, 41 VS 8 8.5 10 V C 15, 41 IS 70 85 110 mA A PLL Divider 2.1 Programmable R-divider 14-bit register 3 16383 A 2.2 Programmable (VCO) N-divider (1 kHz step frequency) 2- × 18-bit register switchable via Bit 5 3 262143 A 2.3 Reference oscillator input voltage f = 0.1 MHz to 3 MHz 2.4 Reference frequency FM AM 27 100 120 120 mVrms 150 2850 10000 10000 B kHz kHz *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40° C to +85° C) but are tested at +25° C 4 T4260 4528G–AUDR–12/03 T4260 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters Test Conditions 2.5 Settling time in FM mode (switching from 87.5 MHz to 108 MHz or vice versa) fPD = 50 kHz IPD = 2 mA 3 Pin Symbol Min. Typ. Max. 1 Unit Type* ms B AMLF/FMLF 3.1 Output current 1 FMLF, AMLF = 1.8 V 16, 17 40 50 60 µA A(1) 3.2 Output current 2 FMLF, AMLF = 1.8 V 16, 17 80 100 120 µA A(1) 3.3 Output current 3 FMLF, AMLF = 1.8 V 16, 17 850 1000 1250 µA A(1) 3.4 Output current 4 FMLF, AMLF = 1.8 V 16, 17 1650 2000 2450 µA A(1) 3.5 Leakage current FMLF, AMLF = 1.8 V 16, 17 10 nA A(1) 400 mV C 4 VTUNE 4.1 Saturation voltage LOW VSATH = (VA-VPDOFM) 18 VSATL 4.2 Saturation voltage HIGH VSATH = (VA-VPDOFM) 18 VSATH 500 mV C 1, 2 IDAC1,2 1 mA D 1, 2 VDAC1,2 5 DAC1, DAC2 5.1 Output current 100 200 5.2 Output voltage VS-0.6 V A 5.3 Maximum offset range Offset = 0, gain = 58 1, 2 0.9 0.98 1.1 V A(1) 5.4 Minimum offset range Offset = 127, gain = 58 1, 2 -0.9 -0.98 -1.1 V A(1) 5.5 Maximum gain range Gain = 255, offset = 64 1, 2 2.06 2.09 2.13 – A(1) 5.6 Minimum gain range Gain = 0, offset = 64 1, 2 0.63 0.67 0.73 – A(1) 21 60 170 MHz B 21 60 140 MHz A 22 150 mVrms C 150 mVrms A 6 Oscillator 6.1 Frequency range 6.2 Fractional frequency range 6.3 Buffer output 7 7.1 8 0.3 Fractional mode Oscillator Input Input voltage 21 VOSC FM Mixer 8.1 Frequency range MHz B 8.2 Input IP3 133 dBµV C 8.3 Input impedance 3.5 kΩ D 8.4 Input capacitance 8.5 Noise figure 8.6 Conversion transconductance 75 163 4 F 14 2.6 3.1 3.6 pF D dB C ms D(1) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40° C to +85° C) but are tested at +25° C 5 4528G–AUDR–12/03 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. 9 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 26 MHz B AM Mixer (Symmetrical Input) 9.1 Frequency range 0.075 9.2 Input IP3 133 dBµV C 9.3 Input impedance 2.5 kΩ D 9.4 Noise figure 10 dB C 9.5 Conversion transconductance mS D(1) 10 Isolation F 2.6 3.1 3.6 10.1 Isolation AM-FM 40 dB C 10.2 IF suppression 40 dB C MHz MHz A 11 RF-AGC 11.1 Frequency range FM AM 11.2 Output current FM AM 5 5 mA mA B 11.3 Output current time constant FM rising FM falling AM symmetrical 2 50 40 ms ms ms C 11.4 RF-AGC AM threshold (programmable with Bit 12 - Bit 15) 75 0.075 163 26 88 dBµV 42 87 88 90 dBµV A(1) 89 dBµV 42 88 89 91 dBµV A(1) 90 dBµV 42 89 90 92 dBµV A(1) 91 dBµV 42 90 91 93 dBµV A(1) 92 dBµV 42 91 92 94 dBµV A(1) 93 dBµV 42 92 93 95 dBµV A(1) 94 dBµV 42 93 94 96 dBµV A(1) 95 dBµV 42 94 95 97 dBµV A(1) 96 dBµV 42 95 96 98 dBµV A(1) 97 dBµV 42 96 97 99 dBµV A(1) 98 dBµV 42 97 98 100 dBµV A(1) 99 dBµV 42 98 99 101 dBµV A(1) 100 dBµV 42 99 100 102 dBµV A(1) 101 dBµV 42 100 101 103 dBµV A(1) 102 dBµV 42 101 102 104 dBµV A(1) 103 dBµV 42 102 103 107 dBµV A(1) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40° C to +85° C) but are tested at +25° C 6 T4260 4528G–AUDR–12/03 T4260 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. 11.5 12 Parameters RF-AGC FM threshold (programmable with Bit 12 - Bit 15) Test Conditions Pin Min. Typ. Max. Unit Type* 91 dBµV 33 90 91 93 dBµV A(1) 92 dBµV 33 91 92 95 dBµV A(1) 93 dBµV 33 92 93 96 dBµV A(1) 94 dBµV 33 93 94 96 dBµV A(1) 95 dBµV 33 94 95 98 dBµV A(1) 96 dBµV 33 95 96 99 dBµV A(1) 97 dBµV 33 96 97 102 dBµV A(1) 98 dBµV 33 97 98 101 dBµV A(1) 99 dBµV 33 98 99 102 dBµV A(1) 100 dBµV 33 99 100 104 dBµV A(1) 101 dBµV 33 100 101 104 dBµV A(1) 102 dBµV 33 101 102 105 dBµV A(1) 103 dBµV 33 102 103 106 dBµV A(1) 104 dBµV 33 103 104 107 dBµV A(1) 105 dBµV 33 104 105 108 dBµV A(1) 106 dBµV 33 105 106 109 dBµV A(1) 25 MHz A IF Amplifier 12.1 Frequency range 12.2 Output voltage 10 12.3 Distortion (2-tone IM3) f1 = 10.7 MHz f2 = 10.75 MHz RL = 2 × 300 Ω 12.4 Gain (programmable in 2-dB steps) Minimum gain Maximum gain 12.5 Input impedance FM AM 13 13.1 Symbol 36, 35 117 dBµV B 55 dB A 12 42 dB dB A 330 2500 Ω Ω D IF-AGC IF-AGC AM/FM threshold (programmable with Bit 0 - Bit 2) 13.2 AGC dynamic range 13.3 AGC time constant (external capacity ≤100 nF) 109 dBµV 29/30 108 109 112 dBµV A(1) 111 dBµV 29/30 110 111 114 dBµV A(1) 113 dBµV 29/30 111 113 115 dBµV A(1) 115 dBµV 29/30 113 115 117 dBµV A(1) 117 dBµV 29/30 116 117 121 dBµV A(1) 118 dBµV 29/30 117 118 122 dBµV A(1) 119 dBµV 29/30 118 119 123 dBµV A(1) 121 dBµV 29/30 120 121 126 dBµV A(1) 40 dB B 16 4 200 µs ms ms D FM rising FM falling AM symmetrical *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40° C to +85° C) but are tested at +25° C 7 4528G–AUDR–12/03 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters 14 IF Gain 14.1 15 IF gain (programmable with Bit 6 - Bit 9) Output voltageLOW 15.2 Output leakage current HIGH 16 Symbol Min. Typ. Max. Unit Type* 12 dB 9 12 14 dB A(1) 14 dB 12 14 16 dB A(1) 16 dB 14 16 18 dB A(1) 18 dB 17 18 20 dB C(1) 20 dB 17 20 22 dB A(1) 22 dB 19 22 24 dB C(1) 24 dB 21 24 26 dB C(1) 26 dB 23 26 28 dB C(1) 28 dB 25 28 30 dB A(1) 30 dB 27 30 32 dB C(1) 32 dB 29 32 34 dB C(1) 34 dB 31 34 36 dB C(1) 36 dB 33 36 38 dB C(1) 38 dB 35 38 40 dB C(1) 40 dB 37 40 42 dB C(1) 42 dB 39 42 44 dB A(1) 100 160 200 mV A 10 µA A V C 200 mV A 10 µA A V C 5.3 +0.8 V V A A 1.0 MHz B ns ns C C I = 1 mA, VSWO1 = 8.5 V Maximum output voltage 13 VSWOL 13 IOHL 13 8.5 SW2/AGC (Open Drain in Switch Mode) 16.1 Output voltage LOW 16.2 Output leakage current HIGH 16.3 Maximum output voltage 17 Pin SWO1 (Open Drain) 15.1 15.3 Test Conditions I = 1 mA, V11 = 6 V 11 VSWOL 11 IOHL 100 11 160 6 3-wire Bus, ENABLE, DATA, CLOCK 17.1 Input voltage 17.2 Clock frequency 17.3 Period of CLK High Low VBUS VBUS 2.7 -0.3 24 tH tL 250 250 23-25 24 17.4 Rise time EN, DA, CLK 23-25 tR 400 ns C 17.5 Fall time EN, DA, CLK 23-25 tF 100 ns C 17.6 Set-up time 23-25 tS 100 ns C 17.7 Hold time EN 23 tHEN 250 ns C 17.8 Hold time DA 25 tHDA 0 ns C *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40° C to +85° C) but are tested at +25° C 8 T4260 4528G–AUDR–12/03 T4260 3-wire Bus Description The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all bits of one register. The different registers available (see chapter “3-wire Bus Data Transfer” on page 11) are addressed by the length of the command (number of transmitted bits) and by two address bits that are unique to each register of a given length. 8-bit registers are programmed by 8-bit commands, 16bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a falling edge on the enable line (EN) and ends with a rising edge on EN. EN has to be kept LOW during the bus command. The sequence of transmitted bits during one command starts with the MSB of the first byte and ends with the LSB of the last byte of the register addressed. To transmit one bit (0/1), DATA has to be set to the appropriate value (LOW/HIGH) and a LOW-to-HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW-to-HIGH transitions on CLK during the LOW period of EN is used to determine the length of the command. Figure 3. 3-wire Pulse Diagram 8-bit command EN DATA MSB BYTE 1 LSB BYTE 1 LSB MSB CLK 16-bit command EN DATA MSB BYTE 2 LSB CLK 24-bit command EN DATA MSB LSB MSB BYTE 1 LSB MSB BYTE 2 BYTE 3 LSB CLK e.g. R-Divider 27 26 25 24 23 2 2 21 20 X R-Divider X 2 13 2 12 2 11 2 10 29 28 1 0 Addr. PDFM PDAM Fract. 2 3 2 2 2 1 2 0 VCO-Divider 9 4528G–AUDR–12/03 Figure 4. 3-wire Bus Timing Diagram tF tR VHigh Enable tHEN tS tR VLow tF VHigh Data VLow tHDA tS tF tR VHigh Clock VLow tH 10 tL T4260 4528G–AUDR–12/03 T4260 3-wire Bus Data Transfer Table 1. Control Registers A24_10 MSB BYTE 1 LSB MSB BYTE 2 R-Divider LSB MSB R-Divider BYTE 3 ADDR. PDAM/ PDFM Fractional LSB Divider VCO 27 26 25 24 23 22 21 20 x x 213 212 211 210 29 28 1 0 1/0 0/1 23 22 21 20 131 130 129 128 127 126 125 124 139 138 137 136 135 134 133 132 x x 145 144 143 142 141 140 LSB MSB x x A24_01 MSB BYTE 1 BYTE 2 N2-Divider LSB MSB N2-Divider ADDR. BYTE 3 x x LSB N2-Divider 27 26 25 24 23 22 21 20 215 214 213 212 211 210 29 28 0 1 01) 01) 01) 01) 217 216 109 108 107 106 105 104 103 102 117 116 115 114 113 112 111 110 x x 123 122 121 120 119 118 LSB MSB x x x x Note: 1. Value has to be 0. A24_00 MSB BYTE 1 BYTE 2 N1-Divider 27 26 87 86 Note: 1. LSB MSB N1-Divider ADDR. BYTE 3 LSB N1-Divider 25 24 23 22 21 20 215 214 213 212 211 210 29 28 0 0 01) 01) 01) 01) 217 216 85 84 83 82 81 80 95 94 93 92 91 90 89 88 x x 101 100 99 98 97 96 Value has to be 0. A16_11 MSB BYTE 1 LSB DAC2-Gain MSB BYTE 2 LSB ADDR. 27 26 25 24 23 22 21 20 1 1 x x x x x x 73 72 71 70 69 68 67 66 x x 79 78 77 76 75 74 A16_10 MSB BYTE 1 LSB DAC2-Offset MSB ADDR. BYTE 2 LSB SWAMLF Osc.Buffer Low c. CP High c.CP SWimpulse SWwire x 26 25 24 23 22 21 20 1 0 1= standard ON/ OFF HI/ LO HI/ LO ON/ OFF ON/ OFF 59 58 57 56 55 54 53 52 x x 65 64 63 62 61 60 A16_01 MSB BYTE 1 LSB DAC1-Gain MSB BYTE 2 LSB ADDR. 1=SW2 0=AGC SW2 1=low SW1 1=low 27 26 25 24 23 22 21 20 0 1 x x x 1/0 1/0 1/0 45 44 43 42 41 40 39 38 x x 51 50 49 48 47 46 11 4528G–AUDR–12/03 A16_00 MSB BYTE 1 LSB DAC1-Offset MSB ADDR. BYTE 2 x x LSB x x x SHIFT x 26 25 24 23 22 21 20 0 0 0 0 0 0 01) 1/0 31 30 29 28 27 26 25 24 x x 37 36 35 34 33 32 Note: 1. Value has to be 0. A8_11 MSB BYTE 1 LSB ADDR. Delay time high cur. CP2 x HCDEL 1 1 ON/ OFF HI/ LO ON/ OFF HI/ LO 01) 1/0 x x 23 22 21 20 19 18 Note: 1. Delay time high cur. CP1 Value has to be 0. A8_10 MSB BYTE 1 LSB ADDR. AM/ FM IFAGC 1 0 1/0 1/0 23 22 21 20 x x 17 16 15 14 13 12 ADDR. IF-IN VCO 0 1 AM/ FM HI/LO 23 22 21 20 x x 11 10 9 8 7 6 N2/N1 PLL ON/ OFF PD TE/ PD RF-AGC A8_01 MSB BYTE 1 LSB IF-Gain A8_00 MSB ADDR. BYTE 1 LSB IF-AGC 0 0 1/0 1/0 01) 22 21 20 x x 5 4 3 2 1 0 Note: 12 1. Value has to be 0. T4260 4528G–AUDR–12/03 T4260 Bus Control IF-AGC The IF-AGC controls the level of the IF signal that is passed to the external ceramic filter and the IF input (AM Pin 35 or FM Pin 36 and Pin 34). In AM mode the time constant can be selected by the external capacitors at Pin 32 (IFAGCA1) and Pin 10 (IFAGCA2) and in FM mode by an external capacitor at Pin 31 (IFAGCFM). In AM mode, the double pole (by the capacitors at Pin 32 and Pin 10) allows a better harmonic distortion by a lower time constant. The IF-AGC threshold can be controlled by setting Bits 0 to 2 as given in Table 2. Table 2. IF-AGC Threshold IF-AGC B2 B1 B0 109 dBµV 0 0 0 111 dBµV 0 0 1 113 dBµV 0 1 0 115 dBµV 0 1 1 117 dBµV 1 0 0 118 dBµV 1 0 1 119 dBµV 1 1 0 121 dBµV 1 1 1 The IF-AGC ON/OFF can be controlled by Bit 16 as given in Table 3. Table 3. IF-AGC PD Test IF-AGC ON/OFF B16 IF-AGC ON 0 IF-AGC OFF 1 A special test mode for PD is implemented for final production test only. This mode is activated by setting Bit 3 = 1. This mode is not intended to be used by customer application. For normal operation Bit 3 has to be set to 0. Table 4. PD-Test Mode N1/N2 PD TE/PD B3 Pin 17 = AMLF output (standard) 0 Pin 17 = PD Testmode 1 The N2/N1 Bit controls the active N-divider. Only one of the two N-Divider can be active. The N1-Divider is activated by setting Bit 5 = 0, the N2-Divider by setting Bit 5 = 1. Table 5. N-Divider N2/N1 B5 N1-divider active 0 N2-divider active 1 13 4528G–AUDR–12/03 IF Amplifier The IF gain amplifier can be used in AM and FM mode to compensate the loss of the external ceramic bandfilters. The IF gain can be controlled in 2-dB steps by setting Bit 6 to Bit 9 as given in Table 6. Table 6. IF Gain IF Gain B9 B8 B7 B6 12 dB 0 0 0 0 14 dB 0 0 0 1 16 dB 0 0 1 0 18 dB 0 0 1 1 20 dB 0 1 0 0 ... ... ... ... ... 40 dB 1 1 1 0 42 dB 1 1 1 1 The selection of the IF amplifier input can be controlled by Bit 11 as given in Table 7. Table 7. IF-IN Operating Mode IF-IN AM/FM B11 IF-IN FM 0 IF-IN AM 1 REMARK: The AM input (Pin 35) has an input impedance of 2.5 kΩ for matching with a crystal filter. The FM input (Pin 36) has an input impedance of 330 Ω for matching with a ceramic filter. VCO The VCO HI/LO function is controlled by means of Bit 10. Table 8. VCO Operating Mode RF-AGC VCO HI/LO B10 VCO high current 0 VCO low current 1 The AM and FM RF-AGC controls the current into the AM and FM pin diodes (FM Pin 3 and AM Pin 9) to limit the level at the AM or FM mixer input. If the level at the AM or FM mixer input exceeds the selected threshold, then the current into the AM or FM pin diodes increases. If this step is not sufficient in AM mode, the source drain voltage of the MOSFET (Pin 11) can be decreased. In AM mode, the time constants can be selected by the external capacitors at Pin 42 (RFAGCA1) and at Pin 12 (RFAGCAM2) and in FM mode by an external capacitor at Pin 33 (RFAGCFM). In AM mode, the double pole (by the capacitors at Pin 42 and Pin 12) allows a better harmonic distortion by a lower time constant. The RF-AGC can be controlled in 1-dB steps by setting the Bits 12 to 15. The values for FM and AM are controlled by Bit 17. 14 T4260 4528G–AUDR–12/03 T4260 Table 9. RF-AGC Reception Mode RF-AGC AM RF-AGC FM B15 B14 B13 B12 88 dB 91 dB 0 0 0 0 89 dB 92 dB 0 0 0 1 90 dB 93 dB 0 0 1 0 91 dB 94 dB 0 0 1 1 92 dB 95 dB 0 1 0 0 ... ... ... ... ... ... 102 dB 105 dB 1 1 1 0 103 dB 106 dB 1 1 1 1 There are two different operation modes, AM and FM, which are selected by means of Bit 17 and Bit 145 according to Table 1 and Table 2. In AM mode (Bit 17 = 1), the AM mixer, the AM RF-AGC, the AM divider (prescaler) and the IF AM amplifier (input at Pin 35) are activated. In FM mode (Bit 17 = 0), the FM mixer, the FM RF-AGC and the IF FM amplifier (input at Pin 36) are activated. In AM or FM reception mode, Bit 145 has to be set to the corresponding mode. The buffer amplifier input can be connected to Pin 16 (with the external FM loop filter) by Bit 145 = 0 and to Pin 17 (with the external AM loopfilter) by Bit 145 = 1. The AM/FM function for the tuner part is controlled by Bit 17 as given in Table 10. Table 10. Tuner Operating Modes PLL AM/FM B17 FM 0 AM 1 The PLL can switch off by Bit 4 = 0. In this case, the N-Divider input signal is internally connected to ground. Table 11. PLL Mode HCDEL PLL ON/OFF B4 PLL OFF 0 PLL ON 1 There are two registers, HCDEL 1 (Bits 20 and 21) and HCDEL 2 (Bits 22 and 23), to control the delay time of the high-current charge pump and to deactivate them. Bit 18 (HCDEL) determines whether register HCDEL 1 or 2 is used. Table 12. High-current Charge Pump Delay Time Register HCDEL 1/2 Select Mode HCDEL (B18) HCDEL 1 0 HCDEL 2 1 15 4528G–AUDR–12/03 If Bits 20 and 21 (HCDEL 1) or Bits 22 and 23 (HDCEL 2) are both set to 0, then the high-current charge pump is deactivated. Otherwise, the delay time can be selected as described in Table 13. Table 13. Delay Time of HCDEL Register 2-bit Shift High-current Charge Pump B21/B23 B20/B22 OFF 0 0 Delay time 5 ns 0 1 Delay time 10 ns 1 0 Delay time 15 ns 1 1 A divider 2-bit shift (Bit 32 = 0) allows faster frequeny changes by using a four times higher step frequeny (e.g., fPDF = 50 kHz instead of fPDF = 12.5 kHz). If the PLL is locked (after the frequency change), the normal step frequency (e.g., fPDF = 12.5 kHz) will be active again. If no 2-bit shift is used (Bit 32 = 1), the frequeny changes will be done with the normal step frequency (12.5 kHz). In 2-bit shift mode the N- and R-divider are shifted by two bits to the right (this corresponds by a R- and N-divider division by 4). An important condition for this mode is that the R-divider has to be a multiple of 4. Table 14. Manual and Lock Detect Shift Mode 2-bit Shift SW1 (Pin 13) B32 Dividers 2-bit shift 0 No shift 1 The switching output SW1 (Pin 13) is controlled by Bit 46 as given in Table 15. Table 15. Switching Output REMARK: SW1 B46 High 0 Low 1 SW1 is an open-drain output. Figure 5. Internal Components at SW1 SW1 16 T4260 4528G–AUDR–12/03 T4260 SW2/AGC (Pin 11) The Pin SW2/AGC works as a switching output (open drain, Pin 11) or as an AM AGCcontrol pin to control the cascade stage of an external AM-preamplifier. The SW2/AGC is controlled by Bits 47 and 48 as given in Table 16. Table 16. Switching Output 2 / AGC Mode REMARK: SW2/AGC B48 B47 AGC function 0 X High 1 0 Low 1 1 In AGC mode, the output voltage is 6 V down to 1 V. Figure 6. Internal Components at SW2/AGC VS AGC SWO/AGC SW2 Test Mode A special test mode is implemented for final production test only. This mode is activated by setting Bit 123 = 1. This mode is not intended to be used by customer application. For normal operation Bit 123 has to be set to 0. Table 17. Test Mode AM Mixer Test Mode B123 ON 1 OFF 0 The AM mixer is used for up-conversion of the AM reception frequency to the IF frequency. Therefore, an AM prescaler is implemented to generate the necessary LO frequency from the VCO frequency. The VCO divider can be controlled by the Bits 140 to 143 as given in Table 18. (The VCO divider is only active in AM mode) 17 4528G–AUDR–12/03 Table 18. Divider Factor of the AM Prescaler Divider AM Prescaler B143 B142 B141 B140 Divide by 2 0 0 0 0 Divide by 3 0 0 0 1 Divide by 4 0 0 1 0 Divide by 5 0 0 1 1 Divide by 6 0 1 0 0 Divide by 7 0 1 0 1 Divide by 8 0 1 1 0 Divide by 9 0 1 1 1 Divide by 10 1 x x x FM Mixer In the FM mixer stage, the FM reception frequency is down-converted to the IF frequency. The VCO frequency is used as LO frequency for the mixer. PLL Loop Filter The PLL loop filter selection for AM and FM mode can be controlled by Bit 145 as given in Table 19. Table 19. Loop Filter Operating Mode Fractional Mode PDAM/PDFM B145 PDFM active 0 PDAM active 1 The activated fractional mode (Bit 144 = 0) in connection with the direct shift (Bit 32 = 0) allows fast frequency changes (with the help of the 2-bit shift) with a four times higher step frequency. After the frequency change, the normal step frequency is active again. If the fractional mode is deactivated (Bit 144 = 1) and direct shift mode is active, (Bit 32 = 0) the VCO frequency is set to the next lower frequency which is many times the amount frequency of 4 times step frequency. This means that the 2 shifted bits of the active N-Divider are not used in this mode. The shift bits are interpreted as logic 0. The fractional mode with direct shift mode deactivated (Bit 32 = 1) allows normal frequency changes with a step frequency of 12.5 kHz. Table 20. Fractional Mode Spurious Suppression Fractional B144 ON 0 OFF 1 In fractional and direct shift mode the spurious suppression is able by SW wire and SW impulse. Table 21. Spurious Suppression by SW Wire 18 SW Wire B60 OFF 0 ON 1 T4260 4528G–AUDR–12/03 T4260 Table 22. Spurious Suppression by Correction Current Charge Pump Charge Pump (AMLF/FMLF) SW Impulse B61 OFF 0 ON 1 AMLF/FMLF is the current charge pump output of the PLL. The current can be controlled by setting the Bits 62 and 63. The loop filter has to be designed correspondingly to the chosen pump current and the internal reference frequency. During the frequency change, the high-current charge pump (Bit 62) is active to enable fast frequency changes. After the frequency change, the current will be reduced to guarantee a high S/N ratio. The low-current charge pump (Bit 63) is then active. The high current charge pump can also be switched off by setting the bits of the active HCDEL register to 0 (Bit 20 and Bit 21 [HCDEL 1] or Bit 22 and Bit 23 [HCDEL 2]). The current of the high-current charge pump is controlled by Bit 62 as given in Table 23. Table 23. High-current Charge Pump High-current Charge Pump B62 1 mA 0 2 mA 1 The current of the low-current charge pump is controlled by Bit 63 as given in Table 24. Table 24. Low-current Charge Pump Low Current Charge Pump B63 50 µA 0 100 µA 1 External Voltage at AMLF The oscillator (Pin 22) can be switched on/off by Bit 65. It is possible to use the oscillator buffer as an input or as an output. At the AMLF (Pin 17), an external tuning voltage can (Oscillator) be applied (Bit 65 = 0). If this is not done, the IC operates in standard mode (Bit 65 = 1). The oscillator, oscillator buffer and the AMLF are controlled by the Bits 65 and 64 as given in Table 25. Table 25. Oscillator Operating Modes Oscillator Oscillator Buffer AMLF (Pin 17) B65 B64 OFF INPUT INPUT f. DAC’s 0 X ON OFF AMLF (standard) 1 0 ON OUTPUT AMLF (standard) 1 1 19 4528G–AUDR–12/03 DAC1, 2 (Pins 1, 2) For automatic tuner alignment, the DAC1 and DAC2 of the IC can be controlled by setting gain and offset values. The principle of the operation is shown in Figure 7. The gain is in the range of 0.67 × VTune to 2.09 × VTune. The offset range is +0.98 V to -0.98 V. For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filter and the IF filter. For alignment, offset and gain are set for having the best tuner tracking. Figure 7. Block Diagram of DAC1, 2 VTUNE DAC1, 2 Gain +/- Offset The gain of DAC1 and DAC2 has a range of approximately 0.67 × V(VTUNE) to 2.09 × V(TUNE). This range is divided into 255 steps. One step is approximately (2.090.67)/255 = 0.00557 × V(TUNE). The gain of DAC1 can be controlled by the Bits 38 to 45 (20 to 27) and the gain of DAC2 can be controlled by the Bits 66 to Bit 73 (20 to 27) as given in Table 26. Table 26. Gain of DAC1, 2 Gain DAC1 Approximately B45 B44 B43 B42 B41 B40 B39 B38 Decimal Gain Gain DAC2 Approximately B73 B72 B71 B70 B69 B68 B67 B66 Decimal Gain 0.6728 × V(TUNE) 0 0 0 0 0 0 0 0 0 0.6783 × V(TUNE) 0 0 0 0 0 0 0 1 1 0.6838 × V(TUNE) 0 0 0 0 0 0 1 0 2 0.6894 × V(TUNE) 0 0 0 0 0 0 1 1 3 ... ... ... ... ... ... ... ... ... ... 0.9959 × V(TUNE) 0 0 1 1 1 0 1 0 58 ... ... ... ... ... ... ... ... ... ... 2.0821 × V(TUNE) 1 1 1 1 1 1 0 1 253 2.0877 × V(TUNE) 1 1 1 1 1 1 1 0 254 2.0932 × V(TUNE) 1 1 1 1 1 1 1 1 255 Offset = 64 (intermediate position) The offset of DAC1 and DAC2 has a range of approximately +0.98 V to -0.99 V. This range is divided into 127 steps. One step is approximately 1.97 V/127 = 15.52 mV. The offset of DAC1 can be controlled by the Bits 24 to Bit 30 (20 to 26) and the offset gain of DAC2 can be controlled by the Bits 52 to Bit 58 (20 to 26) as given in Table 27. 20 T4260 4528G–AUDR–12/03 T4260 Table 27. Offset of DAC1, 2 Offset DAC1 Approximately B30 B29 B28 B26 B26 B25 B24 Decimal Offset Offset DAC2 Approximately B58 B57 B56 B55 B54 B53 B52 Decimal Offset 0.9815 V 0 0 0 0 0 0 0 0 0.9659 V 0 0 0 0 0 0 1 1 0.9512 V 0 0 0 0 0 1 0 2 0.9353 V 0 0 0 0 0 1 1 3 ... ... ... ... ... ... ... 0 0 0 0 0 0 64 ... -0.0120 V 1 ... ... ... ... ... ... ... -0.9576 V ... 1 1 1 1 1 0 1 125 -0.9733 V 1 1 1 1 1 1 0 126 -0.9890 V 1 1 1 1 1 1 1 127 Gain = 58 (intermediate position) 21 4528G–AUDR–12/03 Permitted DAC Conditons The internal operation amplifier of the DACs should not operate with a too high internal difference voltage at their inputs. This means that a voltage difference higher than 0.5 V at the internal OP input should be avoided in operation mode. The respective output OP in the DAC is necessary for the addition and amplification of the tuning voltage (at pin 18) with the desired voltage gain and offset value. If the tuning voltage reaches a high value e.g. 9 V, with a gain setting of 2 times VTune and an offset of +1 V, then the output OP of the DAC should reach the (calculated) voltage of 19 V. The supply voltage of e.g. 10 V, however, limits the output voltage (of the DAC) to 10 V maximum. Due to the (limiting) supply voltage and the internal gain resistance ratio of 6 , the missing 9 V (calculated voltage - Vs) cause a voltage of 1.5 V at the OP input. This condition may not remain for a longer period of time. As long as the calculated DAC output voltage value does not exceed the supply voltage value by more than 3 V, no damages should occur during the product’s lifetime as the input voltage of the internal OP input voltage does not exceed 0.5 V. VTune x DAC gain factor + DAC offset < Vs + 3 V (9 V x 2 + 1 V) < 10 V + 3 V (condition not allowed) This means when having a gain factor of 2 and an offset value of 1 V, the tuning voltage should not exceed 6 V. Maximum tuning voltage < (VS + 3 V - DAC offset) / DAC gain factor e.g.: maximum tuing voltage = (10 V + 3 V - 1 V) / 2 = 6 V It is also possible to reduce the gain or the offset value instead of (or along with) the tuning voltage. Figure 8. Internal Components of DAC1, 2 VS DAC1, 2 22 T4260 4528G–AUDR–12/03 T4260 Input/Output Interface Circuits VTUNE, AMLF and FMLF (Pins 16-18) VTUNE is the loop amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. Figure 9. Internal Components at VTune, AMLF and FMLF VS VS V5 VTUNE AMLF/FMLF EN, DATA, CLK (Pins 23-25) All functions can be controlled via a 3-wire bus consisting of Enable, Data and Clock. The bus is designed for microcontrollers which can operate with 3-V supply voltage. Details of the data transfer protocol can be found in the chapter “3-Wire Bus Description”. Figure 10. Internal Components at Enable, Data and Clock V5 EN DATA CLK 23 4528G–AUDR–12/03 Figure 11. Block Diagram of the PLL Core 14 - BIT LATCH R - DIV. HCDEL 1 HCDEL 2 SHIFT 2 BIT Fref BIT 18 BIT 32 SWITCH DELAYTIME high cur. CP R - DIVIDER PHASE DETECTOR N / N+1 DIVIDER CHARGE PUMP B145 AM / FM AM/FM FILTER PREAMP AM - LOOP FILTER FM - LOOP FILTER VCO B62,63 B61 SWITCH N+1, N SHIFT 2 BIT ACCU 2 - BIT MUX N1 N2 2-BIT (LSB) B5 LATCH N - DIV 1 18 - BIT PLL Core Block Diagram Description LATCH N - DIV 2 B60, B144 18 - BIT The two N-dividers are stored in two 18-bit memory register (LATCH N-DIV) and the R-divider in a 14-bit memory register (LATCH R-DIV). One of the the two N-dividers (N1 or N2) can be activated by Bit 5 as active N-divider (with the 18-bit multiplexer MUX). The (divider) 2-bit shift mode can be activated with Bit 32 = 0. The N- and R-divider are shifted two bits to the right in this shift mode. Because the two lowest R-divider bits (Bit 124 and Bit 125) are 0 they do not have to be evaluated. In opposite to the R-divider the lowest two N-divider bits (Bit 102 and Bit 103 or Bit 80 and Bit 81, depends on the active N-divider) are special evaluated in the ACCU block if fractional mode is active (Bit 144 = 0). The two lowest N- and R-divider bits are also called shift bits. The SWITCH N+1, N block is steering the division through N or N+1 in the N-divider if fractional and 2-bit shift mode are active. There is only a division by N if the fractional mode is deactivated in 2-bit shift mode. The output signals of the 18-bit N-divider and 14-bit R-divider will be compared in the PHASEDETECTOR which one activates the sink and source currents of the charge pumps (CP). 24 T4260 4528G–AUDR–12/03 T4260 There are also two HCDEL registers (for the high current CP delay time) but only one of them is active. One of the HCDEL registers can be activated by Bit 18. The delay time of the HCDEL register can be selected with Bit 20 and Bit 21 or Bit 22 and Bit 23). The current for the high CP (HCCP) can be set by Bit 62 and the current for the low current CP (LCCP) by Bit 63. With Bit 145 the AM- or FM-Loopfilter (pin) can be activated. It is also possible to use the AM-Loopfilter in FM mode (instead of the FM-Loopfilter) or the FM-Loopfilter in AM mode. High-speed Tuning The fractional mode (Bit 144 = 0) in connection with the direct shift mode (Bit 32 = 0) allows very fast frequency changes with four times the step frequency (50 kHz = 4 × fPDF) at low frequency steps (e.g., fPDF = 12.5 kHz). In direct shift mode, the R- and the N-divider are shifted by 2 bits to the right (this corresponds to a R- and N-divider division by 4 or a step frequency multiplication by 4). Due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of 34 ms for a tune over the whole FM band from 87.5 MHz to 108 MHz is possible with fPDF = 12.5 kHz. If the FM receiving frequency is 103.2125 MHz (with e.g. f PDF = 12.5 kHz and fIF = 10.7 MHz), an N-divider of 9113 and an R-divider of 12 are necessary when using a reference-frequency (fref) of 150 kHz. fVCO = fIF + frec = 10.7 MHz + 103.2125 MHz = 113.9125 MHz fPDF = fVCO / N = fref / R = 113.9125 MHz / 9113 = 150 kHz /12 = 12.5 kHz An important condition for the use of the fractional mode is an R-divider with an integer value after the division by 4 (R-dividers have to be a multiple of 4). After a 2-bit shift (divider division by 4), the R-divider is now 3 (instead of 12) and the N-divider is 2278.25 (instead of 9113). The new N-divider of 2278.25 is also called ¼ fractional step because the modulo value of the N-divider is 0.25 = ¼. In total, there are 4 different fractional 2-bit shift steps: full, ¼, ½ and ¾ step. If the fractional mode is switched off (Bit 144 = 1) during direct shift mode (Bit 32 = 0), the modulo value of the N-divider will be ignored (the new N-divider is then 2278 instead of 2278.25). This means that the PLL locks on the next lower multiple frequency of 4 × fPDF (in our case fPDF = 12.5 kHz). The new VCO frequency (fVCO) is then 113.9 MHz (instead of 113.9125 MHz in fractional mode). Also the PLL has additionally a special fractional logic which allows a good spurious suppression in the fractional and direct shift mode. Activating the wire switch (Bit 60 = 1) and the correction charge pump (Bit 60 = 1) the spurious suppression is active. 25 4528G–AUDR–12/03 Charge Pump Current Settings Bit 62 (0 = 1 mA; 1 = 2 mA) allows to adjust the high current, which is active during a frequency change (if the delay time of the active HCDEL register is not switched off). A high charge pump current allows faster frequeny changes. After a frequency change, the current reduction is reduced (in locked mode) to the low current which is set by bit 63 (0 = 50 µA; 1 = 100 µA). A lower charge pump current guarantees a higher S/N ratio. The high current charge pump can be switched off by the active HCDEL register bits. In this case, when HCDEL 1 is active and the bits 20 and 21 are 0 (HCDEL 1 delay time = off) or HCDEL 2 is active and the bits 22 and 23 are 0 (HCDEL 2 delay time = off), only the low current charge pump (current) is active in locked and in the frequency change mode. AM Prescaler (Divider) Settings The AM mixer is used for up-conversion of the AM reception frequency to the IF frequency. Therefore, an AM prescaler is implemented to generate the necessary LO from the VCO frequency. For the reception of the AM band, different prescaler (divider) settings are possible. Table 28 lists the AM prescaler (divider) settings and the reception frequencies. fVCO = 98.2 MHz to 124 MHz fIF = 10.7 MHz frec = fVCO - fIF fVCO = AM prescaler x (frec + fIF) The following formula can also be useful by AM frequencies higher than 20 MHz: fVCO = AM prescaler x (frec - fIF) Table 28. AM Prescaler (Divider) Settings and the Reception Frequencies Divider (AM Prescaler) Note: 26 Minimum Reception Frequency [MHz] Maximum Reception Frequency [MHz] no divider 87.5 113.3 Divide by 2 38.4 51.3 Divide by 3 22.033 30.633 Divide by 4 13.85 20.3 Divide by 5 8.94 14.1 Divide by 6 5.667 9.967 Divide by 7 3.329 7.014 Divide by 8 1.575 4.8 Divide by 9 0.211 3.078 Divide by 10 0 1.7 The AM Prescaler Divider Settings with fVCO from 98.2 MHz to 124 MHz is only an example. The tuning range depends on the tuning diode and the inductor in the VCO circuit. The tank of the VCO should be designed for a maximum range at pin 18 (VTUNE) of 1.5 V to VSPLL - 1 V for a good S/N performance. T4260 4528G–AUDR–12/03 T4260 The N- and R- divider can be calculated as following: N = AM Prescaler × (frec + fIF)/fstep N = (frec + fIF)/fstep R = fref/fstep fVCO = N × fstep fref = reference oscillator frequency (pin 27) (AM mode) (FM mode) (For all modes) Example of AM settings: If the receiving frequency is 0.84 MHz (AM) and the following conditions are: fref = 4 MHz; fstep = 10 kHz; fIF = 10.7 MHz and an AM-Prescaler of 10 a N-Divider of 11540 and a R-Divider of 400 is necessary. R = fref/fstep = 4 MHz/10 KHz = 400 N = AM Prescaler × (frec + fIF)/fstep = 10 × (0.84 MHz + 10.7 MHz)/10 KHz = 11540 External Voltage at AMLF By using two ICs, for example, it is possible to operate the AMLF (Pin 17) of the second IC either with the tuning voltage (Vtune [Pin 18]), the DAC 1 voltage [Pin 1] or the DAC 2 (Pin 17) voltage [Pin 2] from the first T4260. For voltage reduction at the AMLF [Pin 17], a voltage factor ratio of 100/16 (R1/R2) is required. This means that an applied voltage from 0.5 V at Pin 17 (AMLF) corresponds to a tuning voltage of 3.625 V. It is recommended to use R1 with 100 kΩ and R2 with 16 kΩ. The allowed range of R1 is 10 kΩ to 1 MΩ and 1.6 kΩ to 160 kΩ for R2. Figure 12. External Voltage at AMLF (Pin 17) T4260Gain Vtune or DAC R1 R2 AMLF T4260 The maximum input voltage at the AMLF input (Pin 17) depends on the applied supply voltage as well as on the gain and offset settings. To avoid any damages during the product’s lifetime, the following formulas regarding SWAMLF voltage, gain and offset settings have to be observed (see chapter “Permitted DAC Conditons” on page 22). VSWAMLF x ([R1 + R2] / R2) x DAC gain factor + DAC offset < VS + 3 V (R1 + R2) / R2 = 7.25 This means when having a gain factor of 2 and an offset value of 1 V, the applied SWAMLF voltage should be limited to a voltage lower than 0.83 V. SWAMLF voltage < (VS + 3 V - DAC offset) / (DAC gain factor × 7.25) e.g.: maximum SWAMLF voltage = (10 V + 3 V - 1 V) / (2 × 7.25) = 0.83 V It is also possible to reduce the gain or offset instead (or along with) the SWAMLF voltage. 27 4528G–AUDR–12/03 Figure 13. Test Circuit Test Point 1 DAC1 MXFMOB 44 2 DAC2 MXFMOA 43 10n 330 100n 10n 3 FMAGCO 10n 3k 10n RFAGCA1 42 4 MXFMIA VST 41 5 MXFMIB MXAMOA 40 6 GNDRF MXAMOB 39 7 MXAMIB GNDT 38 8 MXAMIA VRT 37 VST 100n 9 AMAGCO IFINFM 36 330 10 IFAGCA2 IFINAM 35 2k4 11 SW2/AGC RFAGCA 12 2 13 SW1 IFREF 34 100n RFAGCFM 33 100k IFAGCA1 32 100k 14 VRVCO IFAGCFM 31 100n VSPLL 15 VSPLL IFOUTA 30 100 16 FMLF IFOUTB 29 17 AMLF GNDPLL 28 10n 100n 1n 5k1 18 VTUNE REFFREQ 27 10k 5k6 15p 19 OSCGND 10n 22p 20 OSCE 47p 21 OSCB 22 OSCBUF 10n 28 VRPLL 26 1n DATA 25 CLK 24 BUS EN 23 10n T4260 4528G–AUDR–12/03 T4260 Figure 14. Application Circuit P2 P3 GNDT GNDPLL C13 R2 IFoutA Bu2 10uF 180 100n C15 KF1 R6 300 F1 F2 100n 220n100n C17 10n C31 12p L2 100uH C23 C24 R14 68k F3 R11 1n 6p8 CD1 C22 68k C32 6p8 C25 L3 4n7 2m2 20 21 R9 470 R10 47k C40 C41 15n 100n 10p C19 L1 T1 C18 2u2 BFR93A 10n C27 C45 10u 47 F4 CD2 D1 C26 C34 1n C49 6p8 F5 1n CD3 BB804 R27 5k6 R23 5R6 220n VSPLL P10 T2 BC848B P16 470k R19 470k R15 1k AMPREIN C36 Bu1 22p 47p R18 3p9 S391D 10n Ant C44 100n J109 R17 22 OSCBUF Bu5 R26 100 BB804 R13 1k C42 1n C46 R12 68k 23 C50 OSCB Bu4 C43 R25 2n2 5k1 100n T4 C21 C20 10n 27p REFFREQ C47 C48 18p BB804 DATA 19 VRPLL 18 R24 6k2 C38 R16 2k7 16 17 P11 P12 P13 FM AM VT P15 SW1 BC 848 T3 OSCB 2u2 100n OSCE 4u7 OSCGND 100n 24 VTUNE 100n 25 GNDPLL C16 10n DAC2 P8 26 AMLF 15 27 IFOUTB IFINFM AMAGCO 12 13 14 C37 C39 10 11 C28 29 28 FMLF VRT MXAMIA 6 7 C29 VSPLL GNDT MXAMIB 5 8 9 C30 DAC1 P7 30 IFAGCFM MXAMOB GNDRF 4 31 VRVCO MXAMOA MXFMIB 3 33 32 IFAGCA1 VST MXFMIA 2 34 IFREF RFAGCA1 FMAGCO 1 35 SW2/AGC MXFMOA 37 36 DAC2 38 IFOUTA 100n 47p 40 39 MXFMOB 41 C10 C11 C12 IFINAM 220n 42 C8 DAC1 100p 44 43 DATA P4 CLK P5 EN P6 100n C6 C5 IFAGCA2 C3 REFFREQ Bu4 100n C14 C9 100n SW1 R3 300 RFAGCA2 RFAGCFM C2 100n C1 10u IFoutB Bu3 2k2 VST R1 P1 5R6 KF2 R8 EN 1u OSCBUF C7 CLK R5 5R6 C4 L4 10n P14 D2 S391D P9 AMAGCO 4u7 C35 10p C33 D3 S391D 100n R28 3k9 R22 470k 29 4528G–AUDR–12/03 Ordering Information Extended Type Number Package Remarks T4260IL SSO44 Tube T4260ILQ SSO44 Taped and reeled Package Information 9.15 8.65 Package SSO44 Dimensions in mm 18.05 17.80 7.50 7.30 2.35 0.3 0.25 0.10 0.8 16.8 44 0.25 10.50 10.20 23 technical drawings according to DIN specifications 1 30 22 T4260 4528G–AUDR–12/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4528G–AUDR–12/03