Features • On-chip Control Functions are Available for System Gain Adjust (dB Linear versus DC Current) • Low Noise LO Design • ESD Protected Benefits • All Front-end Functions of a High-performance FM Receiver Except the RF FM Receiver IC Preamplifier are Integrated • Improved Dynamic Range by High Current Double-balanced Mixer Design and a New AGC Conception with 3 Loops On-chip • Improved Blocking and Intermod Behavior Due to a Unique “Interference” Sensor U4065B Controlling the AGC • Easy Cascading of 3 IF Filters (Ceramic) Enabled by Two On-chip IF Preamplifiers Description The IC U4065B is a bipolar integrated FM front-end circuit. It contains a mixer, an oscillator, two IF preamplifiers and an unique interference sensor. The device is designed for high-performance car radio and home receiver applications. Rev. 4807A–AUDR–05/04 Figure 1. Block Diagram VS ANT VS IF gain adjust IF tank IF BPF IF BPF IF output IF BPF 19 RF tank 18 20 5 21 4 7 3 16 2 14 PIN ATT Mixer IF 1 RF AGC wide band and IF Interference mixer RF tank NC LO tank IF 2 13 AGC adjust (wide band) 12 24 VREF = 4 V IF and detector 23 22 1 9 11 17 Voltage regulator Local oscillator 8 6 10 + LO output VS Interference IF BPF VTUNE VS AGC level 2 U4065B 4807A–AUDR–05/04 U4065B Pin Configuration Figure 2. Pinning SO24 LOBUFF 1 24 LOB GND1 2 23 LOE IF2OUT 3 22 GND5 GAINIF1 4 21 IF1IN IF2IN 5 20 GND4 VS 6 19 MIXOUT2 IF1OUT 7 18 MIXOUT1 GND2 8 17 VREF IMIFIN 9 16 MIXIN2 AGCOUT 10 15 MIXIN1 IMMIXOUT 11 14 GND3 NC 12 13 AGCWB 3 4807A–AUDR–05/04 Pin Description 4 Pin Symbol Function 1 LOBUFF Buffered local oscillator output 2 GND1 Ground of the second IF amplifier 3 IF2OUT Output of the second IF amplifier 4 GAINIF1 Gain control of the first IF amplifier 5 IF2IN 6 VS 7 IF1OUT 8 GND2 Ground 9 IMIFIN Input of the amplifier for the IM sensor 10 AGCOUT Output of the automatic gain control 11 IMMIXOUT Output of the intermodulation mixer 12 NC 13 AGCWB 14 GND3 Mixer ground 15 MIXIN1 Input 1 of the double-balanced mixer 16 MIXIN2 Input 2 of the double-balanced mixer 17 VREF 18 MIXOUT1 19 MIXOUT2 20 GND4 Ground of the first IF amplifier 21 IF1IN Input of the first IF amplifier 22 GND5 Oscillator ground 23 LOE Local oscillator (emitter) 24 LOB Local oscillator (base) Input of the second IF amplifier Supply voltage Output of the first IF amplifier Not connected Threshold adjustment of the wideband AGC Reference voltage output Mixer output 1 Mixer output 2 U4065B 4807A–AUDR–05/04 U4065B LOBUFF Figure 3. Buffered Local Oscillator Output + 23 50 1 ESD 1V The buffered local oscillator used for output, drives the FM input of the PLL circuit (for example, U428xBM family). The typical parallel output resistance at 100 MHz is 70 Ω, the parallel output capacitance is about 10 pF. When using an external load of 500 Ω/10 pF, the oscillator swing is about 100 mV. The second harmonic of the oscillator frequency is less than -15 dBc. GND1 Figure 4. Ground of the Second IF Amplifier 8 2 ESD There is no internal connection to the other ground pins. IF2OUT Figure 5. Output of the Second IF Amplifier 3 ESD VS VREF The parallel output capacitance to ground is about 7 pF. The external load resistance must be connected to VS. The DC current into the pin is typically 3 mA. Note: The supply voltage VS has to be protected against IF distortion. 5 4807A–AUDR–05/04 GAINIF1 Figure 6. Gain Control of the First IF Amplifier 17 VREF 2 kΩ ESD 4 The gain of the first IF amplifier can be adjusted by a resistor to ground. This is useful, for example, to compensate for the insertion loss tolerances of the ceramic BPFs. It must be ensured that the output current of the pin does not exceed 150 µA in any case. Linear increasing in the current out of GAINIF1 results in a linear dB increase of the gain (0.15 dB/µA). I4 = 0, thus, G = Gmin = 2 dB I4 = 140 µA, thus, G = Gmax = 22 dB IF2IN Figure 7. Input of the Second IF Amplifier VREF 5 ESD The parallel input resistance is 330 Ω. The parallel input capacitance is about 12 pF. No DC current is allowed. To avoid overload of this stage, an internal detector watches the input level and causes current at the AGCOUT pin. 6 U4065B 4807A–AUDR–05/04 U4065B IF1OUT Figure 8. Output of the First IF Amplifier VS ESD 330 7 The parallel output resistance is 330 Ω which allows the use of standard ceramic BPF. The parallel output capacitance is about 7 pF. The DC voltage at the pin is 0.5 V less than VS. IMIFIN Figure 9. Input of the IF Amplifier for the IM Sensor 9 ESD The parallel input resistance is 330 Ω. The amplifier is extremely sensitive to AC signals. An IF signal with a few hundred µV at this pin will cause current at the AGC output. Therefore, attention needs to be paid when connecting the standard ceramic filter between IMOUT and this pin. The reference point of the filter has to be free of any AC signal, no DC current shall appear at this pin. 7 4807A–AUDR–05/04 AGCOUT Figure 10. Output of the Automatic Gain Control 10 1k ESD 1V The AGC output is an open collector output. The current of the pin diode is this current multiplied by the current gain of the external PNP transistor. The DC voltage at the pin may vary from 2 V to VS, therefore, this pin can easily be used as an indicator of the AGC regulation state. IMMIXOUT Figure 11. Output of the Intermodulation Mixer VS ESD 300 11 1V The parallel output resistance is 330 Ω which allows the use of standard ceramic BPF without any further matching network. It must be ensured that the ground pin of the filter is free of AC signals. AGCWB Figure 12. Threshold Adjustment of the Wideband AGC VREF 35k 32k ESD 13 The threshold of the wideband AGC can be adjusted by an external resistor to ground. The setting range is 10 dB. For minimum blocking, this pin is connected to ground. To set the threshold to lower levels, the resistance should have a value of up to a few hundred kΩ. 8 U4065B 4807A–AUDR–05/04 U4065B MIXIN1 Figure 13. Input 1 of the Double-balanced Mixer VREF 2.5k 15 ESD The parallel input resistance is 1.2 kΩ. The parallel input capacitance is about 9 pF. When using the mixer in an unbalanced way, this pin needs to be grounded for RF signals by an external capacitance of a few nF. DC current is not allowed. MIXIN2 Figure 14. Input 2 of the Double-balanced Mixer VREF 2.5k 16 ESD The parallel input resistance is 1.6 kΩ. The parallel input capacitance is about 7 pF. The double sideband noise figure of the unbalanced mixer is about 7 dB. If using the mixer in balanced mode, the noise figure will be reduced by about 0.8 dB. VREF Figure 15. Reference Voltage Output VS 200 4.6 V 17 ESD The internal temperature-compensated reference voltage is 3.9 V and it is used as bias voltage for most blocks. Therefore, the electrical characteristics of the U4065B are mainly independent of the supply voltage. The internal output resistance of the reference voltage is less than 10 Ω. To avoid internal coupling across this pin, external capacitors are required. The maximum output current is IREF = 5 mA. 9 4807A–AUDR–05/04 MIXOUT1, MIXOUT2 Figure 16. Mixer Output 1, 2 18 19 ESD The mixer output is an open collector of a bipolar transistor. The minimum voltage at these pins is 5 V (VS - voltage swing). The DC current into these pins is typically 9 mA. Good LO and RF suppression at the mixer output can be achieved by symmetrical load conditions at the pins MIXOUT1 and MIXOUT2. IF1IN Figure 17. Input of the First IF Amplifier 21 VREF 330 ESD The typical input resistance is 330 Ω. The DC voltage is almost identical to the reference voltage. DC current must be avoided at this pin. 10 U4065B 4807A–AUDR–05/04 U4065B LOE Figure 18. Emitter of the Local Oscillator 23 ESD An external capacitor is connected between LOE and ground. The ground pin of this capacitor must be connected to pin GND5, the chip-internal ground of the local oscillator. LOB Figure 19. Base of the Local Oscillator 24 ESD The tank of the local oscillator is connected at pin LOB. The ground pin of this tank needs to be connected to pin GND5, the chip-internal ground of the local oscillator’s pin 24. The resonant resistance of the tank should be about 250 Ω. Minimum Q of the unloaded tank is 50. 11 4807A–AUDR–05/04 Functional Description The U4065B FM-frontend IC is the dedicated solution for high-end car radios. A new design philosophy enables to build up tuners with superior behavior. This philosophy is based on the fact that the sensitivity of state of the art designs is at the physical border and cannot be enhanced any more. On the other hand, the spectral power density in the FM-band increases. An improvement of reception can only be achieved by increasing the dynamic range of the receiver. This description is to give the designer an introduction to get familiar with this new product and its philosophy. The Signal Path The U4065B offers the complete signal path of an FM-frontend IC including a highly linear mixer and two IF preamplifiers. The mixer is a double-balanced, high-current Gilbert Cell. A high transit frequency of the internal transistors enables the use of the emitter grounded circuit with its favorable noise behavior. The full balanced output offers LO carrier reduction. The first IF preamplifier has a dB-linear gain adjustment by DC means. Thus, different ceramic filter losses can be compensated and the overall tuner gain can be adapted to the individual requirements. The low noise design suppresses post stage noise in the signal path. Input and output resistance is 330 Ω to support standard ceramic filters. This is achieved without feedback, which would cause different input impedances when varying the output impedance. The second IF preamplifier enables the use of three ceramic filters with real 330 Ω inputand output termination. Feedthrough of signals is kept low. The high level of output compression is necessary to keep up a high dynamic range. Beneath the signal path the local oscillator part and the AGC signal generation can be found on chip. The local oscillator uses the collector grounded colpitts type. A low phase noise is achieved with this access. A mutual coupling in the oscillator coil is not necessary. The AGC Concept Special care was taken to design a unique AGC concept. It offers 3 AGC loops for different kinds of reception conditions. The most important loop is the interference sensor part. In today’s high-end car radios, the FM AGC is state of the art. It is necessary to reduce the influence of 3rd and higher order intermodulation to sustain reception in the presence of strong signals in the band. On one hand, it makes sense to reduce the desired signal level by AGC as few as possible to keep up stereo reception, on the other hand two or more strong out-of-channel signals may interfere and generate an intermodulation signal on the desired frequency. By introducing input attenuation, the level of the intermod signal decreases by a higher order, whereas the level of the desired signal shows only a linear dependency on the input attenuation. Therefore, input attenuation by pin diodes may keep up reception in the presence of strong signals. The standard solution to generate the pin diode current is to pick up the RF-signal in front of the mixer. Because the bandwidth at that point is about 1.5 MHz, this is called wideband AGC. The threshold of AGC start is a critical parameter. A low threshold does not allow any intermodulation but has the disadvantage of blocking if there is only one strong station on the band or if the intermod signals do not cover the desired channel. A higher AGC threshold may tolerate a certain ground floor of intermodulation. This avoids blocking, but it has the disadvantage, that no reception is possible, if the interfering signals generate an intermod signal inside the desired channel. This contradiction could not be overcome in the past. 12 U4065B 4807A–AUDR–05/04 U4065B With the new U4065B IC, there is a unique access to this problem. This product has an interference sensor on chip. Thus, an input signal attenuation is only performed if the interfering signals do generate an intermod signal inside the desired channel. If they do not, the existing wideband AGC is active but up to 20 dB higher levels. The optimum AGC state is always generated. The Figure 20 to Figure 23 on page 14 illustrate the situation. In Figure 20 the AGC threshold of a standard tuner is high to avoid blocking. But then the intermod signal suppresses the desired signal. The interference sensor of the U4065B ensures that the AGC threshold is kept low as illustrated in Figure 21 on page 14. In Figure 22 on page 14 the situation is reversed. The AGC threshold of a standard tuner is kept low to avoid intermod problems. But then blocking makes the desired signal level drop below the necessary stereo level. In this case, the higher wideband AGC level of the U4065B enables perfect stereo reception. By principle, this interference sensor is an element with a third order characteristic. For input levels of zero, the output level is zero, too. With increasing input level, the output level is increased with the power of three, thus preferring intermod signals compared to linear signals. At the same time, a down conversion to the IF level of 10.7 MHz is performed. If a corresponding 10.7 MHz IF filter selects the intermod signals, only an output is generated, if an intermod signal inside the 10.7 MHz channel is present. The circuit blocks interference sensor and IF, and detector build up a second IF chain. In an FM system, the maximum deviation of a 3rd order intermod signal is the triple max deviation of the desired signal. Therefore, the ceramic IF BPF between pin 11 and pin 9 may be a large bandwidth type. This is all that is needed for this unique feature. A further narrow band AGC avoids overriding the second IF amplifier. The amplitude information of the channel is not compressed in order to maintain multipath detection in the IF part of the receiver. Figure 20. A High AGC Threshold Causes the Intermod Signal to Suppress the Desired Signal Level Interfering signals Intermod signal Intermod signal Desired signal Stereo-level Noise floor Desired frequency Frequency 13 4807A–AUDR–05/04 Figure 21. AGC Threshold Settings Level Interfering signals Desired signal Stereo-level Intermod signal Intermod signal Noise floor Frequency Desired frequency Figure 22. A Low AGC Threshold Causes the Blocking Signal to Suppress the Desired Signal Level Strong signal Stereo-level Desired signal Noise floor Frequency Desired frequency Figure 23. The Correct AGC Threshold Enables Optimum Reception Level Strong signal Desired signal Stereo-level Noise floor Desired frequency 14 Frequency U4065B 4807A–AUDR–05/04 U4065B Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Reference point is ground (pins 2, 8, 14, 20 and 22) Parameters Symbol Value Unit Supply voltage VS 10 V Power dissipation at Tamb = 85°C Ptot 470 mW Tj 125 °C Ambient temperature range Tamb -30 to +85 °C Storage temperature range Tstg -50 to +125 °C ± VESD 2000 V Symbol Value Unit RthJA 90 K/W Junction temperature Electrostatic handling: Human body model (HBM), all I/O pins tested against the supply pins Thermal Resistance Parameters Thermal resistance Electrical Characteristics VS = 8.0 V, fRF = 98 MHz, fOSC ≅ 108.7 MHz, fIF = fOSC - fRF = 10.7 MHz Reference point is ground (pins 2, 8, 14, 20, and 22),Tamb = 25°C, unless otherwise specified. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Supply voltage 3, 6, 10, 18, 19 VS 7 8 10 V Supply current 3, 6, 10, 18, 19 Itot 37 47 mA VLOB VLOE 160 100 90 220 Oscillator (GND5 Has to be Connected to External Oscillator Components) Oscillator voltage 24 23 1 RG24 = 220 Ω, unloaded Q of LOSC = 70, RL1 = 520 Ω Harmonics 1 Output resistance 1 Voltage gain VLOBUFF 70 mV -15 Between 1 and 23 dBc Ω 70 RLO 0.9 Mixer (GND3 Has to be Separated from GND1, GND2 and GND4) Conversion power gain 3rd-order input intercept Conversion transconductance Noise figure Source impedance: RG15,16 = 200 Ω Load impedance: RL18,19 = 200 Ω GC 5 7 10 dB IP3 4 6 14 dBm 8 mA/V NFDSB 7 dB kΩ gC Input resistance to ground f = 100 MHz 15 Rignd15 1.2 Input capacitance to ground f = 100 MHz 15 Cignd15 9 pF Input resistance to ground f = 100 MHz 16 Rignd16 1.6 kΩ Input capacitance to ground f = 100 MHz 16 Cignd16 7 pF kΩ Input-input resistance Between 15 and 16 Rii15,16 1.6 Input-input capacitance Between 15 and 16 Cii15,16 5 pF 18 and 19 Cignd18,19 9 pF Output capacitance to GND 15 4807A–AUDR–05/04 Electrical Characteristics (Continued) VS = 8.0 V, fRF = 98 MHz, fOSC ≅ 108.7 MHz, fIF = fOSC - fRF = 10.7 MHz Reference point is ground (pins 2, 8, 14, 20, and 22),Tamb = 25°C, unless otherwise specified. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit 17 20 24 dB First IF Preamplifier (IF 1) Gain control deviation by I4 4 Gain control slope 4 External control current to ground At Gmin At Gnom At Gmax Power gain At I4min At I4nom At I4max Noise figure At Gmax At Gnom At Gmin Source impedance: RG21 = 200 Ω, Load impedance: RL7 = 200 Ω Between 21 and 7 Between 21 and 7 Temperature coefficient of the gain at Gnom dGIF1/dI4 0.15 dB/µA I4min I4nom I4max 0 70 140 µA Gmin Gnom Gmax -2.5 11 19 2 12 22 2.5 16 28 dB NFmin NFnom NFmax 7 9 15 dB TKnom +0.045 dB/K 1 dB compression at Gnom 7 Vcnom 70 mV -3 dB cut-off frequency at Gnom 7 fcnom 50 MHz Input resistance f = 10 MHz 21 RiIF1 Input capacitance f = 10 MHz 21 CiIF1 Output resistance f = 10 MHz 7 RoIF1 Output capacitance f = 10 MHz 7 CoIF1 Between 5 and 3 GIF2 270 330 270 330 400 5 Ω pF 400 7 Ω pF Second IF Preamplifier (IF 2) Power gain Source impedance: RG5 = 200 Ω Load impedance: RL3 = 200 Ω Noise figure 15 18 19 dB NFIF2 7 dB mV MHz 1 dB compression 3 Vcomp 500 -3 dB cutoff frequency 3 fc 50 270 330 400 Ω Parallel input resistance f = 10 MHz 5 RiIF2 Parallel input capacitance f = 10 MHz 5 CiIF2 12 pF kΩ pF Parallel output resistance f = 10 MHz 3 RoIF2 50 Parallel output capacitance f = 10 MHz 3 CoIF2 7 17 Vref 3.7 5 Voltage Regulator Regulated voltage Maximum output current 17 Iref Internal differential resistance, dc17/di17 when I17 = 0 17 rd17 17 psrr Power supply suppression 16 f = 50 Hz 3.9 V mA 7 36 4.9 50 50 Ω dB U4065B 4807A–AUDR–05/04 U4065B Electrical Characteristics (Continued) VS = 8.0 V, fRF = 98 MHz, fOSC ≅ 108.7 MHz, fIF = fOSC - fRF = 10.7 MHz Reference point is ground (pins 2, 8, 14, 20, and 22),Tamb = 25°C, unless otherwise specified. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit AGC Input Voltage Thresholds (AGC Threshold Current is 10 µA at Pin 10) IF2 input 5 VthIF2 85 86 92 dBµV IF and detector 9 VthIFD 42 43 48 dBµV Between 15 and 16 VthWB1 VthWB2 95 85 98 87 100 90 dBµV dBµV fiRF = 100 MHz V at pin 13 = 0 V I through pin 13 = 0 A Mixer input level of wideband sensor Figure 24. Test Circuit VO IF 4.7n 4.7n Gain IF 1 0 to 140 µA 50 VI IF 1 6 6 5 2 2 5 50 1 I4 RL7 VI IF 7 20 4 RG5 50 2 5 50 1 5 6 2 21 VO IF 4.7n VS 1 2 6 I3 IF 1 RL3 IF 2 18 2 5 RL18,19 1 5 50 6 4.7n 1 block 13 15 R13 I13 AGC adjust (wide band) Mixer Voltage RG15,16 VS AGC 19 14 2 VS I10 10 50 VO IF 3 RG21 I18,19 5 16 6 VS regulator I6 6 4.7n VI RF Interference mixer RG24 8p fOSC COSC 47p VREF = 4 V 24 23 1µ 17 Local Interference oscillator amplifier 9 RG9 LOSC 2 6 5 1 4.7n 33p 22 12 11 1 50 8 VI IF RLOBUFF RG11 470p 2 VO IF 1 1 VLOBUFF fLOBUFF RL1 6 4.7n 5 50 RF Transformers MCL Type TMO 4 - 1 IL = 0.7 dB 5 Z/Ω 50 200 2 4 0 0 6 17 4807A–AUDR–05/04 Local Oscillator Figure 25. LO Principle Application RG24 VOSC24 47p fOSC 24 Local oscillator 23 33p VOSC1, fOSC 1 Oscillator output buffer 520 Tamb Free running oscillator frequency fOSC ≈ 110 MHz, VOSC24 = 160 mV, RG24 = 220 Ω, QL = 70 Figure 26. Oscillator Swing versus Temperature 180 160 VOSC1 (mV) 140 120 100 80 60 40 20 0 -30 -10 10 30 50 70 90 Tamb (°C) 18 U4065B 4807A–AUDR–05/04 U4065B fOSC = 110.7 MHz, VOSC24 ≅ 160 mV, fIF = 10.7 MHz Mixer Figure 27. Mixer Principle Application 50 2 VIRF1 fRF1 1 2 2 VIRF2 fRF2 5 6 Mixer 19 15 RG24 VOIF IL2 18 14 IL1 2 1 6 5 50 24 Local oscillator 23 47p VS 22p fOSC Tamb Conversion power gain GC = 20 log (VOIF/VIRF) + IL1 (dB) + IL2 (dB) IL1, IL2 insertion loss of the RF transformers Figure 28. Mixer Characteristic 120 Conversion characteristic VOIF (dBµV) 100 80 60 40 3rd order IM-characteristic 20 0 0 20 40 60 80 100 120 VIRF1, VIRF2 (dBµV) 19 4807A–AUDR–05/04 Figure 29. Conversion Power Gain of the Mixer Stage versus Temperature 8 7 GC (dB) 6 5 4 3 2 1 0 -30 -10 10 30 50 70 90 Tamb (°C) Figure 30. Current of the Mixer Stage versus Temperature 11.0 10.7 I18, I19 (mA) 10.4 10.1 9.8 9.5 9.2 8.9 8.6 8.3 8.0 -30 -10 10 30 50 70 90 Tamb (°C) 20 U4065B 4807A–AUDR–05/04 U4065B First IF Preamplifier Figure 31. First IF Preamplifier Principle Application VIIF21 1:2 IL1 50 1 fIF 2VIIF 5 21 7 IF VOIF7 RL7 = 200 RG21 = 200 2 Tamb 4 6 VOIF 2:1 IL2 2 1 6 5 50 V (pin 4) I4 Power gain GIF = 20 log (VOIF/VIIF) + IL1 (dB) + IL2 (dB) IL1, IL2 = insertion loss of the RF transformers Figure 32. Power Gain of the First IF Amplifier versus I4 25 T = 90°C 20 GIF (dB) 15 T = -30°C 10 5 0 T = 30 °C -5 0 20 40 60 80 100 120 140 I4 (µA) 21 4807A–AUDR–05/04 Figure 33. Power Gain of the First IF Amplifier versus Frequency 25 20 Gmax GIF1 (dB) 15 Gnom 10 5 Gmin 0 -5 -10 10 20 30 40 50 60 70 80 90 100 f (MHz) Figure 34. V (Pin 4) versus I4 3.8 3.6 T = 90°C 3.4 V4 (V) 3.2 3.0 2.8 T = 30°C T = -30°C 2.6 2.4 2.2 2.0 0 20 40 60 80 100 120 140 I4 (µA) 22 U4065B 4807A–AUDR–05/04 U4065B Second IF Preamplifier Figure 35. Second IF Preamplifier Principle Application VS 330 VIIF5 1:2 IL1 50 fIF VOIF3 3 5 RL3 = 200 RG5 = 200 1 2 5 6 VOIF 2:1 IF Tamb IL2 2 1 6 5 50 2 VIIF Power gain GIF = 20 log (VOIF/VIIF) + IL1 (dB) + IL2 (dB) IL1; IL2 = insertion loss of the RF transformers Figure 36. Power Gain of the Second IF Amplifier versus Temperature 18.5 18.0 GIF2 (dB) 17.5 17.0 16.5 16.0 15.5 15.0 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Tamb (°C) 23 4807A–AUDR–05/04 Figure 37. Power Gain of the Second IF Amplifier versus Frequency 20 18 16 GIF2 (dB) 14 12 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 100 f (MHz) Figure 38. AGC Threshold (110 = 1 µA) of the Second IF Amplifier versus Temperature Threshold (dBµV) 87.0 86.8 86.6 86.4 86.2 86.0 -30 -10 10 30 50 70 90 Tamb (°C) Figure 39. AGC Characteristic of the Second IF Amplifier Input 10000.00 1000.00 I10 (µA) 100.00 110 (90°C)/µA 110 (-30°C)/µA 10.00 1.00 0.10 110 (30°C)/µA 0.01 80 85 90 95 100 105 VIIF (dBµA) 24 U4065B 4807A–AUDR–05/04 U4065B Interference Sensor (Mixer) Figure 40. Interference Sensor Principle Application 50 2 VIRF1 fIRF1 2 VIRF2 fIRF2 15 IL1 1 2 5 6 RG15/16 = 200 RL11 = 200 Interference mixer 11 IL2 16 2 1 6 5 VOIF fIF 50 fLO Local oscillator VS IL1 = IL2 = 0.7 dB Test conditions for characteristic VOIF versus VIRF1: fLO = 100 MHz, fRF1 = 89.3 MHz, VIRF2 = 0, fIF = fLO - fRF1 = 10.7 MHz Test conditions for 3rd order IM-characteristic VOIF versus VIRF1, VIRF2: fLO = 100 MHz, fRF1 = 89.4 MHz, fRF2 = 89.5 MHz, fIF = fLO - (2 fRF1 - 1 fRF2) = 10.7 MHz IL1, IL2 = insertion loss of the RF transformer Figure 41. Characteristics of the Interference Sensor (Mixer) 90 80 VOIF(dBµV) 70 Conversion characteristic 60 50 40 3rd order IM-characteristic 30 20 10 0 60 65 70 75 80 85 90 95 100 VIRF (dBµV) 25 4807A–AUDR–05/04 Figure 42. Conversion Characteristic of the Interference Sensor (Mixer) 100 90 -30°C VOIF (dBµV) 80 70 60 30°C 50 40 90°C 30 20 10 0 70 75 80 85 90 95 100 105 110 115 VIRF (dBµV) Figure 43. Third-order Interference Characteristic of the Interference Sensor (Mixer) 80 VOIF (dBµV) 70 60 -30°C 50 40 30°C 30 90°C 20 70 75 80 85 90 95 100 105 110 115 VIRF (dBµV) 26 U4065B 4807A–AUDR–05/04 U4065B Interference Sensor (Amplifier) Figure 44. Interference Sensor Principle Application 50 fIF 2 VIIF AGC Thresholds 1:2 VIIF9 IL1 RG9 = 200 10 9 VS IF 1 2 5 6 I10 Tamb IL1 = 0.7 dB Figure 45. AGC Threshold of the Interference IF Amplifier versus Temperature Threshold (dBµV 45.0 44.5 44.0 43.5 43.0 42.5 42.0 41.5 41.0 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Tamb (°C) Figure 46. Wideband AGC Threshold (I10 = 1 µA) versus I13 105 VIRF (dBµV) 108 MHz 100 88 MHz 95 90 98 MHz 85 0 5 10 15 20 25 30 35 40 45 50 55 I13 (µA) 27 4807A–AUDR–05/04 Figure 47. Wideband AGC Threshold (I10 = 1 µA) versus Temperature 100 U13 = 0 V 98 VIRF 15/16 96 94 I13 = 30 µA 92 90 88 86 I13 = 0 A 84 82 80 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Tamb (°C) AGC Characteristics Figure 48. AGC Characteristic of the Interference IF and Detector Block 10000.00 -30°C 1000.00 90°C I10 (µA) 100.00 30°C 10.00 1.00 0.10 0.01 35 45 55 65 75 85 95 VIIF (dBµV) Figure 49. Characteristic of the Wideband AGC (I13 = 0 V) 10000.00 1000.00 -30°C I10 (µA) 100.00 10.00 30°C 1.00 90°C 0.10 0.01 80 85 90 95 100 105 110 115 120 VIIF (dBµV) 28 U4065B 4807A–AUDR–05/04 U4065B Figure 50. Characteristic of the Wideband AGC (V13 = 0 V) 10000.00 1000.00 -30°C I10 (µA) 100.00 10.00 30°C 1.00 0.10 90°C 0.01 90 95 100 105 110 115 120 9.5 10.0 VIRF (dBµV) DC Characteristics Figure 51. Supply Current versus Supply Voltage 18 16 I6 14 I (mA) 12 10 I18, I19 8 6 I3 4 2 0 6.0 6.5 7.0 7.5 8.0 8.5 9.0 VS (V) Figure 52. Reference Voltage versus Temperature 3.88 3.87 VREF (V) 3.86 3.85 3.84 3.83 3.82 3.81 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Tamb (°C) 29 4807A–AUDR–05/04 Figure 53. Supply Current versus Temperature 40 35 I3 + I6 + I18 + I19 30 I (mA) 25 20 I6 15 I18, I19 10 I3 5 0 -30 -10 10 30 50 70 90 Tamb (°C) Figure 54. Reference Voltage versus I17 4.00 VREF (V) 3.95 3.90 3.85 3.80 3.75 -10 -8 -6 -4 -2 0 2 4 I17 (mA) 30 U4065B 4807A–AUDR–05/04 4807A–AUDR–05/04 ANT 75 Ω VAGC 27p C25 1n C4 R2 100 22 VTUN 1n C6 10n C5 1.7 - 6.5 V S391D R1 2p7 220nH L1 10n D1 S392D C3 1n C2 D2 C1 56k R3 D3 1 3 1p5 C10 10p C8 R6 47k VS = 8.5 V C9 10n C11 BFR93A 22 R5 L3 470n 6 4 Q1 2.2 µH L2 C7 1n appr. 8 mA R4 470 R9 220 Q2 BC858 L4 D4 12 330k 100n C15 CF1 1n 6.8p C14 C 16 C13 R14 160k 120k R13 100p CF2 L5 22 R15 330 D5 L6 CF4 1n C24 1 24 22p 47p C20 C23 IF OUT CF3 820 R17 470 R19 10k R18 C19 22n C26 4 6 4.7p 15 R16 1 IF 2 C18 3 U4065B 150n C17 (Tracking adj.) 1n 56k R11 R12 18p C12 13 R7 56k 1.5k R10 R20 22k LO OUT Gain adj. 100k R21 6.8p C22 OSC 1n C21 U4065B Figure 55. Application Diagram 31 Part List Item Q1 32 Description BFR93AR (BFR93A) Q2 BC858 D1 S392D D2 S391D D3, D4, D5 BB804 L1 11 turns, 0.35 mm wire, 3 mm diameter (approximately 220 nH) L2 2.2 mH (high Q type) L3 TOKO® 7KL-type, # 600ENF-7251x L4 TOKO 7KL-type, # 291ENS 2341IB L5 TOKO 7KL-type, # M600BCS-1397N L6 TOKO 7KL-type, # 291ENS 2054IB CF1 TOKO type SKM 2 (230 KHZ) CF2, CF3, CF4 TOKO type SKM 3 (180 KHZ) U4065B 4807A–AUDR–05/04 U4065B Ordering Information Extended Type Number Package Remarks U4065B-AFL SO24 plastic – U4065B-AFL3 SO24 plastic Taping according to ICE-286-3 Package Information Package SO24 Dimensions in mm 9.15 8.65 15.55 15.30 7.5 7.3 2.35 0.25 0.10 0.4 1.27 24 13.97 0.25 10.50 10.20 13 technical drawings according to DIN specifications 1 12 33 4807A–AUDR–05/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2004. All rights reserved. Atmel ® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. TOKO ® is a registered trademark of TOKO KABUSHIKI KAISHA TA Toko, Inc. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4807A–AUDR–05/04