SPEAR-09-H042 SPEAr™ Head200 ARM 926, 200 K customizable eASIC™ gates, large IP portfolio SoC Data Brief Features ■ ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates (16K LUT equivalent) with 8 channels internal DMA high speed accelerator function and 87 dedicated general purpose I/Os ■ Multilayer AMBA 2.0 compliant bus with fMAX 133 MHz ■ Programmable internal clock generator with enhanced PLL function, specially optimized for E.M.I. reduction LFBGA289 ■ 16 KB single port SRAM embedded ■ Dynamic RAM interface: 8/16 bit DDR, 8/16 bit SDRAM ■ SPI interface connecting serial ROM and Flash devices ■ 2 USB 2.0 Host independent ports with integrated PHYs ■ USB 2.0 device with integrated PHY ■ Ethernet MAC 10/100 with MII management interface ■ Real time clock ■ WatchDog ■ 4 general purpose timers ■ Operating temperature: - 40 to 85 °C ■ Package: LFBGA289 (15x15x1.7mm pitch 0.8mm) Description SPEAr Head200 is a powerful digital engine belonging to SPEAr family, the innovative customizable system-on-chip. ■ 1 independent UART up to 115 Kbps (software flow control mode) ■ I2C master mode, fast and slow speed The device integrates an ARM core with a large set of proven IPs (Intellectual Properties) and a configurable logic block that allows very fast customization of unique and/or proprietary solutions, with low effort and low investment. ■ 6 general purpose I/Os Optimized for embedded applications. Table 1. Device summary Order code Package Packing SPEAR-09-H042 LFBGA289 (15x15x1.7mm) Tray January 2008 Rev 1 For further information contact your local STMicroelectronics sales office. 1/16 www.st.com 16 Contents SPEAR-09-H042 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Features modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 eASIC GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 External FPGA emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Dynamic RAM data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Ballout top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Package outline assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/16 SPEAR-09-H042 1 Introduction Introduction This data brief describes the differences between SPEAr Head200 (SPEAR-09-H022) and the one packaged in LFBGA289 balls 0.8mm pitch (SPEAR-09-H042). In this document the main package characteristics are described as well as the chip features modifications. The reference specifications, for the SPEAR-09-H022 are available on the web at: www.st.com. 3/16 Features modification 2 SPEAR-09-H042 Features modification To fit the new small package a number of features has been reduced or limited: 2.1 ● Analog to digital converter (ADC) ● eASIC GPIOs ● External FPGA emulation mode ● Dynamic RAM data path ● UARTs Analog to digital converter (ADC) ADC feature has been completely deleted so the 16 analog channels, the related test output, the power balls and the reference voltages have been removed. 2.2 eASIC GPIOs SPEAR-09-H022 features 112 GPIOs in the eASIC customizable part, some of these I/Os have been removed, but 87 are still available on SPEAR-09-H042. Unusable hidden eASIC GPIOs (74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100-111) must be configured as inputs. 2.3 External FPGA emulation mode SPEAR-09-H022 has the capability to emulate the internal eASIC behavior with an external FPGA through the component GPIOs. This feature has been completely removed on SPEAR-09-H042 hence the developement boards must use the 420 PBGA components. 2.4 Dynamic RAM data path The SPEAr component features a multi purpose memory controller to interface SDRAM or DDR memories able to work with different data path widths. While SPEAR-09-H022 handles 8 and 16-bit DDRs or 8, 16 and 32-bit SDRAMs, on SPEAR-09-H042 to save 16 data balls and the related "data mask" balls, the SDRAM data path has been limited to 16-bit like the DDR one. 2.5 UARTs Two of the original UART interfaces have been removed, SPEAR-09-H042 features just the UART1 interface. 4/16 SPEAR-09-H042 3 Pin description Pin description Table 2 shows the component signals, grouped by function, and the relative ballout diagram. 3.1 Interface signals Table 2. Group Debug eASIC Interface signals Signal Name Ball Direction Function TEST0 A14 TEST1 H14 TEST2 H13 Input Test configuration port. For the functional mode they have to be set to 0 TEST3 H12 PLL_BYPASS G1 Input Enable / disable PLL bypass eASICGP_IO[00] G4 I/O eASIC general purpose I/O eASICGP_IO[01] H7 eASICGP_IO[02] H6 eASICGP_IO[03] H5 eASICGP_IO[04] F3 eASICGP_IO[05] E4 eASICGP_IO[06] F5 eASICGP_IO[07] D2 eASICGP_IO[08] E3 eASICGP_IO[09] D3 eASICGP_IO[10] D1 eASICGP_IO[11] G6 eASICGP_IO[12] G7 eASICGP_IO[13] D4 eASICGP_IO[14] C1 eASICGP_IO[15] E5 eASICGP_IO[16] F6 eASICGP_IO[17] B1 eASICGP_IO[18] E6 eASICGP_IO[19] B4 eASICGP_IO[20] F7 eASICGP_IO[21] A1 5/16 Pin description Table 2. Group 6/16 SPEAR-09-H042 Interface signals (continued) Signal Name Ball eASICGP_IO[22] A3 eASICGP_IO[23] A4 eASICGP_IO[24] C2 eASICGP_IO[25] F4 eASICGP_IO[26] C3 eASICGP_IO[27] C5 eASICGP_IO[28] B5 eASICGP_IO[29] H8 eASICGP_IO[30] B2 eASICGP_IO[31] G5 eASICGP_IO[32] B3 eASICGP_IO[33] A2 eASICGP_IO[34] C4 eASICGP_IO[35] A5 eASICGP_IO[36] H9 eASICGP_IO[37] C6 eASICGP_IO[38] G9 eASICGP_IO[39] C7 eASICGP_IO[40] D5 eASICGP_IO[41] B6 eASICGP_IO[42] A6 eASICGP_IO[43] G8 eASICGP_IO[44] E8 eASICGP_IO[45] E9 eASICGP_IO[46] D8 eASICGP_IO[47] B7 eASICGP_IO[48] E7 eASICGP_IO[49] F8 eASICGP_IO[50] A7 eASICGP_IO[51] B8 eASICGP_IO[52] A8 eASICGP_IO[53] D9 eASICGP_IO[54] D6 eASICGP_IO[55] F9 eASICGP_IO[56] D7 Direction Function SPEAR-09-H042 Table 2. Group Ethernet Pin description Interface signals (continued) Signal Name Ball Direction Function eASICGP_IO[57] F10 eASICGP_IO[58] C9 eASICGP_IO[59] B9 eASICGP_IO[60] A9 eASICGP_IO[61] G10 eASICGP_IO[62] C8 eASICGP_IO[63] E10 eASICGP_IO[64] D10 eASICGP_IO[65] C10 eASICGP_IO[66] B10 eASICGP_IO[67] A10 eASICGP_IO[68] G11 eASICGP_IO[69] F11 eASICGP_IO[70] E11 eASICGP_IO[71] D11 eASICGP_IO[72] C11 eASICGP_IO[73-74] B11 eASICGP_IO[75-76] A11 eASICGP_IO[77-78] A12 eASICGP_IO[79-80] B12 eASICGP_IO[81-82] C12 eASICGP_IO[83-84] D12 eASICGP_IO[85-86] E12 eASICGP_IO[87-88] A13 eASICGP_IO[89-90] B13 eASICGP_IO[91-92] C13 eASICGP_IO[93-94] D13 eASICGP_IO[95-96] E13 eASICGP_IO[97-98] C14 eASICGP_IO[99] D14 eASIC_EXT_CLOCK E14 eASIC_PI_CLOCK K15 TX_CLK C15 TXD[0] C16 Ethernet TX output data TXD[1] C17 Ethernet TX output data eASIC program interface out clock Input Ethernet input TX clock 7/16 Pin description SPEAR-09-H042 Table 2. Group GPI/Os Interface signals (continued) Signal Name Ball Direction TXD[2] D15 Output TXD[3] D16 Ethernet TX output data TX_EN D17 Ethernet TX enable CRS E15 COL E16 RX_CLK E17 RXD[0] F15 RXD[1] F16 RXD[2] F17 RXD[3] G15 RX_DV Input Function Ethernet TX output data Carrier sense input Collision detection input Input Ethernet input RX clock Input Ethernet RX input data G16 Input Data valid on RX RX_ER G17 Input Data error detected MDC H15 Output MDIO H16 I/O I/O data to PHY GP_IO[0] M15 GP_IO[1] L17 GP_IO[2] L16 I/O General purpose I/O GP_IO[3] L15 GP_IO[4] K17 GP_IO[5] K16 SDA H17 I/O I2C serial data SCL J15 Output I2C clock TDO F12 Output JTAG TDO TDI F13 Input JTAG TDI TMS F14 Input JTAG TMS RTCK G12 Output TCK G13 Input JTAG clock nTRST G14 Output JTAG reset Output timing reference for MDIO I2C JTAG 8/16 Master clock MCLK_in N1 Input MCLK_out N2 Output Master reset MRESET G3 Input MPMC MPMCDATA[00] T12 MPMCDATA[01] R12 MPMCDATA[02] T13 MPMCDATA[03] R13 JTAG output clock 12MHz input crystal 12MHz output crystal Master reset SPEAR-09-H042 Table 2. Group Pin description Interface signals (continued) Signal Name Ball MPMCDATA[04] T14 MPMCDATA[05] R14 MPMCDATA[06] T15 MPMCDATA[07] R15 MPMCDATA[08] T17 MPMCDATA[09] P16 MPMCDATA[10] P17 MPMCDATA[11] N15 MPMCDATA[12] N16 MPMCDATA[13] N17 MPMCDATA[14] M16 MPMCDATA[15] M17 MPMCADDROUT[00] R6 MPMCADDROUT[01] U7 MPMCADDROUT[02] T7 MPMCADDROUT[03] R7 MPMCADDROUT[04] U8 MPMCADDROUT[05] T8 MPMCADDROUT[06] R8 MPMCADDROUT[07] U9 MPMCADDROUT[08] T9 MPMCADDROUT[09] R9 MPMCADDROUT[10] U10 MPMCADDROUT[11] T10 MPMCADDROUT[12] R10 MPMCADDROUT[13] T11 MPMCADDROUT[14] R11 nMPMCDYCSOUT[0] U4 nMPMCDYCSOUT[1] T4 nMPMCDYCSOUT[2] T5 nMPMCDYCSOUT[3] R5 MPMCCKEOUT[0] U11 MPMCCKEOUT[1] U12 MPMCCLKOUT[0] U16 nMPMCCLKOUT[0] U15 Direction I/O Function DDR / SDRAM data Output DDR / SDRAM address Output DDR / SDRAM chip select Output DDR / SDRAM clock enable DDR / SDRAM clock 1 Output DDR / SDRAM clock 1 neg. 9/16 Pin description SPEAR-09-H042 Table 2. Group RTC SMI Interface signals (continued) Signal Name Ball Direction Function MPMCCLKOUT[1] U14 DDR / SDRAM clock 2 nMPMCCLKOUT[1] U13 DDR / SDRAM clock 2 neg. MPMCDQMOUT[0] T16 MPMCDQMOUT[1] U17 MPMCDQS[0] R16 MPMCDQS[1] R17 nMPMCCASOUT T6 nMPMCRASOUT U6 nMPMCWEOUT Output DDR / SDRAM data mask Output DDR data strobe Output DDR / SDRAM strobes U5 Output DDR / SDRAM write enable RTCXO U2 Output 32.768KHx output crystal RTCXI U1 Input 32.768KHz input crystal SMINCS[0] B15 SMINCS[1] A17 SMINCS[2] A16 SMINCS[3] A15 SMICLK Output Serial flash chip select B16 Output Serial flash output clock SMIDATAIN B17 Input SMIDATAOUT B14 Output UART1_RXD J17 Input UART1 RX data UART1_TXD J16 Output UART1 TX data DMNS R2 I/O D- port of USB device DPLS R1 I/O D+ port of USB device HOST1_DP L1 I/O D+ port of USB host1 HOST1_DM L2 I/O D- port of USB host1 HOST2_DP J1 I/O D+ port of USB host2 HOST2_DM J2 I/O D- port of USB host2 HOST1_VBUS F1 Output USB host1 VBUS signal HOST2_VBUS F2 Output USB host2 VBUS signal OVERCURH1 E1 I/O USB host1overcurrent OVERCURH2 E2 I/O USB host2 overcurrent VBUS G2 I/O USB device VBUS signal RREF J6 Input Serial flash data in Serial flash data out UART USBs 10/16 USB reference resistor SPEAR-09-H042 3.2 Pin description Power connections Table 3. Group Power Power connections Signal Name Ball vdd3v3 (1) Function Digital 3.3V power vdd (2) Digital 1.2V power gnd (3) Digital ground vdd_dith P6 DDR / SDR dedicated digital PLL 3.3V power vss_dith P7 DDR / SDR dedicated digital PLL ground SSTL_VREF P15 Voltage reference SSTL / CMOS mode. This pin is used both as logic state and as power supply vdd2v5_DDR (4) DDR / SDR digital 2.5V / 3.3V power vdd1v2_date_osci T1 1.2V dedicated power for RTC vdd_date_osci U3 1.2V dedicated power for RTC gnd_date_osci T3 Dedicated digital ground for RTC gnde_date_osci T2 Dedicated digital ground for RTC anavdd_3v3_pll1600 M3 Dedicated USB PLL analog 3.3V power anagnd_3v3_pll1600 M4 Dedicated USB PLL analog ground digvdd_1v2_pll1600 N3 Dedicated USB PLL analog 1.2V power diggnd_1v2_pll1600 N4 Dedicated USB PLL analog ground vddl_1v2_d P5 Dedicated USB 1.2V power vddb_1v2_d P2 Dedicated USB 1.2V power vddc_1v2_d P1 Dedicated USB 1.2V power vdd_usb M5 Dedicated USB 1.2V power vddc_1v2_h1 L4 Dedicated USB 1.2V power vddb_1v2_h1 L3 Dedicated USB 1.2V power vddl_1v2_h1 K3 Dedicated USB 1.2V power vddc_1v2_h0 J5 Dedicated USB 1.2V power vddb_1v2_h0 J4 Dedicated USB 1.2V power vddl_1v2_h0 H3 Dedicated USB 1.2V power vdd3_3v3_d R3 Dedicated USB 3.3V power vdde3v3_usb M2 Dedicated USB 3.3V power vdd3_3v3_h1 K2 Dedicated USB 3.3V power vdd3_3v3_h0 H2 Dedicated USB 3.3V power vssl_3v3_d R4 Dedicated USB ground vssb_1v2_d P4 Dedicated USB ground vssc_1v2_d P3 Dedicated USB ground 11/16 Pin description Table 3. Group SPEAR-09-H042 Power connections (continued) Signal Name Ball Function gnde_usb M1 Dedicated USB ground gnd_usb L5 Dedicated USB ground vssc_1v2_h1 K5 Dedicated USB ground vssb_1v2_h1 K4 Dedicated USB ground vssb_1v2_h0 H4 Dedicated USB ground vssc_1v2_h0 J3 Dedicated USB ground vssl_3v3_h0 H1 Dedicated USB ground vssl_3v3_h1 K1 Dedicated USB ground 1. Signal spread on the following balls: H11, J08, J09, J13, J14, K14, M14, N14, P14. 2. Signal spread on the following balls: H10, J07, J12, L14, N05, P09, P13. 3. Signal spread on the following balls: J10, J11, K06 to K13, L06 to L13, M06 to M13, N08 to N13. 4. Signal spread on the following balls: N06, N07, P08, P10 to P12. 12/16 SPEAR-09-H042 Pin description 3.3 Ballout top view Figure 1. Ballout top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G P _IO[ 21 P _IO[ 33 P _IO[ 22 P _IO[ 23 P _IO[ 35 P _IO[ 42 P _IO[ 50 P _IO[ 52 P _IO[ 60 P _IO[ 67 P _IO[ 75 P _IO[ 77 P _IO[ 87 TEST0 ] ] ] ] ] ] ] ] ] ] ] ] ] SM IN C SM IN C SM IN C S[ 3] S[ 2] S[ 1] A B eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G SM ID A SM IN C SM IC L SM ID A P _IO[ 17 P _IO[ 30 P _IO[ 32 P _IO[ 19 P _IO[ 28 P _IO[ 41 P _IO[ 47 P _IO[ 51 P _IO[ 59 P _IO[ 66 P _IO[ 73 P _IO[ 79 P _IO[ 89 TA OUT S[ 0] K TA IN ] ] ] ] ] ] ] ] ] ] ] ] ] B C eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G TX_C L P _IO[ 14 P _IO[ 24 P _IO[ 26 P _IO[ 34 P _IO[ 27 P _IO[ 37 P _IO[ 39 P _IO[ 62 P _IO[ 58 P _IO[ 65 P _IO[ 72 P _IO[ 81 P _IO[ 91 P _IO[ 97 TXD [ 0] TXD [ 1] K ] ] ] ] ] ] ] ] ] ] ] ] ] ] C D eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G P _IO[ 10 P _IO[ 13 P _IO[ 40 P _IO[ 54 P _IO[ 56 P _IO[ 46 P _IO[ 53 P _IO[ 64 P _IO[ 71 P _IO[ 83 P _IO[ 93 P _IO[ 99 TXD [ 2] TXD [ 3] TX_EN P _IO[ 7] P _IO[ 9] ] ] ] ] ] ] ] ] ] ] ] ] D E eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC _ OVER C OVER C eA SIC G eA SIC G P _IO[ 15 P _IO[ 18 P _IO[ 48 P _IO[ 44 P _IO[ 45 P _IO[ 63 P _IO[ 70 P _IO[ 85 P _IO[ 95 EXT_C UR H 1 UR H 2 P _IO[ 8] P _IO[ 5] ] ] ] ] ] ] ] ] ] LOC K R X_C L K E F eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G H OST1_ H OST2 eA SIC G eA SIC G P _IO[ 25 P _IO[ 16 P _IO[ 20 P _IO[ 49 P _IO[ 55 P _IO[ 57 P _IO[ 69 VB US _VB US P _IO[ 4] P _IO[ 6] ] ] ] ] ] ] ] R XD [ 0] R XD [ 1] R XD [ 2] F G P LL_B YP A SS nTR ST R XD [ 3] R X_D V R X_ER G H eA SIC G eA SIC G vssl_3v vdd3_3 vddl_1v vssb_1v eA SIC G eA SIC G eA SIC G P _IO[ 29 P _IO[ 36 3_h0 v3_h0 2_h0 2_h0 P _IO[ 3] P _IO[ 2] P _IO[ 1] ] ] vdd TEST1 M DC H J H OST2 H OST2 vssc_1v vddb_1v vddc_1v R R EF _D P _D M 2_h0 2_h0 2_h0 vdd gnd gnd vdd vdd3v3 vdd3v3 SC L K vssl_3v vdd3_3 vddl_1v vssb_1v vssc_1v 3_h1 v3_h1 2_h1 2_h1 2_h1 gnd gnd gnd gnd gnd gnd gnd gnd L H OST1_ H OST1_ vddb_1v vddc_1v gnd_us DP DM 2_h1 2_h1 b gnd gnd gnd gnd gnd gnd gnd gnd vdd GP _IO[ GP _IO[ GP _IO[ 1 3] 2] ] L M anavdd anagnd gnde_u vdde3v vdd_us _3v3_pll _3v3_pll sb 3_usb b 1600 1600 gnd gnd gnd gnd gnd gnd gnd gnd vdd3v3 M PM C M PM C GP _IO[ D A TA [ 1 D A TA [ 1 0] 4] 5] M N digvdd_ diggnd_ M C LK_i M C LK_ 1v2_pll1 1v2_pll1 n o ut 600 600 gnd gnd gnd gnd gnd gnd M PM C M PM C M PM C vdd3v3 D A TA [ 1 D A TA [ 1 D A TA [ 1 1] 2] 3] N P vddc_1v vddb_1v vssc_1v vssb_1v vddl_1v vdd_dit vss_dit vdd2v5 2_d 2_d 2_d 2_d 2_d h h vdd vdd3v3 M PM C M PM C SSTL_V D A TA [ D A TA [ 1 R EF 9] 0] P nM P M M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C vdd3_3 vssl_3v M PM C M PM C C D YC S A D D R A D D R A D D R A D D R A D D R A D D R D A TA [ 1 D A TA [ D A TA [ D A TA [ v3_d 3_d D QS[ 0] D QS[ 1] OUT[ 3] OUT[ 0] OUT[ 3] OUT[ 6] OUT[ 9] OUT[ 12] OUT[ 14] ] 3] 5] 7] R vdd1v2_ gnde_d nM P M nM P M nM P M M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C M P M C gnd_dat dat e_o s at e_o sc C D YC S C D YC S C C A SO A D D R A D D R A D D R A D D R A D D R D A TA [ D A TA [ D A TA [ D A TA [ D QM O D A TA [ e_o sci ci i OUT[ 1] OUT[ 2] UT OUT[ 2] OUT[ 5] OUT[ 8] OUT[ 11 OUT[ 13] 0] 2] 4] 6] UT[ 0] 8] T nM P M nM P M nM P M M P M C M P M C M P M C M P M C M P M C M P M C nM P M M P M C nM P M M P M C M P M C vdd_dat C D YC S C WEOU C R A SO A D D R A D D R A D D R A D D R C KEOU C KEOU C C LKO C LKOU C C LKO C LKOU D QM O e_o sci OUT[ 0] T UT OUT[ 1] OUT[ 4] OUT[ 7] OUT[ 10] T[ 0] T[ 1] UT[ 1] T[ 1] UT[ 0] T[ 0] UT[ 1] U R T U D P LS VB US DM NS R TC XI R TC XO 1 2 TD O eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G eA SIC G M R ESE eA SIC G eA SIC G P _IO[ 31 P _IO[ 12 P _IO[ 43 P _IO[ 38 P _IO[ 61 P _IO[ 68 R TC K T P _IO[ 0] P _IO[ 11 ] ] ] ] ] ] 3 4 vdd 5 vdd2v5 vdd2v5 6 7 vdd3v3 vdd3v3 8 vdd 9 vdd3v3 TEST3 vdd2v5 vdd2v5 vdd2v5 10 11 12 TD I TC K TEST2 13 TM S CRS C OL M D IO SD A UA R T1_ UA R T1_ TXD R XD eA SIC _ GP _IO[ GP _IO[ vdd3v3 P I_C LO 5] 4] CK 14 15 16 J K 17 13/16 Package information 4 SPEAR-09-H042 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. LFBGA289 mechanical data and package dimensions mm inch DIM. MIN. TYP. A A1 MAX. MIN. TYP. 1.700 0.270 MAX. 0.0669 0.0106 A2 0.985 A3 0.200 A4 0.0387 0.0078 0.800 b 0.350 14.850 15.000 15.150 0.5846 0.5906 0.5965 E 0.400 0.0315 D D1 OUTLINE AND MECHANICAL DATA 0.450 0.0137 0.0157 0.0177 12.800 0.5039 14.850 15.000 15.150 0.5846 0.5906 0.5965 E1 12.800 0.5039 e 0.800 0.0315 F 1.100 Body: 15 x 15 x 1.7mm 0.0433 ddd 0.120 0.0047 eee 0.150 0.0059 fff 0.080 0.0031 LFBGA289 Low profile Fine Pitch Ball Grid Array 8077927 B 14/16 SPEAR-09-H042 5 Revision history Revision history Table 4. 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