AN200291 Migrating from I2C nvSRAM to I2C F-RAM™ Author: Harsha Medu Associated Part Family: I 2 C F-RAM Associated Code Examples: None Related Application Notes: AN96578 To get the latest version of this application note, please visit http://www.cypress.com/go/AN200291. AN200291 provides guidelines for migrating from I2C nvSRAM to I2C F-RAM™. It recommends equivalent F-RAM devices, describes package and feature differences, and discusses the hardware and firmware modifications that need to be made for a successful migration. Contents 1 2 Introduction ............................................................... 1 Overview .................................................................. 2 2.1 Package Compatibility ..................................... 2 2.2 Pin Compatibility .............................................. 2 2.3 Instruction/Feature Set..................................... 3 2.4 Parameters ...................................................... 4 3 Critical Considerations .............................................. 8 3.1 Pin Difference .................................................. 8 3.2 I2C Speed ........................................................ 9 3.3 nvSRAM Special Features ............................... 9 3.4 Sleep Mode...................................................... 9 3.5 Device ID ....................................................... 10 3.6 Serial Number ................................................ 10 1 3.7 Status Register and Block Protect ................. 11 3.8 Timing Parameters ........................................ 11 3.9 Vcc Ramp Rate ............................................... 11 3.10 Firmware Changes ........................................ 11 4 Summary ................................................................ 11 Document History............................................................ 12 Worldwide Sales and Design Support ............................. 13 Products .......................................................................... 13 PSoC® Solutions ............................................................. 13 Cypress Developer Community....................................... 13 Technical Support ........................................................... 13 Introduction F-RAM (ferroelectric random access memory) is a nonvolatile memory that uses a ferroelectric capacitor to store data. The data written in F-RAM is nonvolatile instantaneously. Unlike EEPROM and flash, F-RAM writes data to nonvolatile memory at bus speed. nvSRAM is a SRAM memory with a nonvolatile element embedded in each memory cell. The embedded nonvolatile elements incorporate SONOS Quantum Trap technology. The SRAM provides infinite read and write cycles, while the Quantum Trap cells offer highly reliable nonvolatile storage of data. Data transfers from the SRAM to the nonvolatile elements (STORE operation) take place automatically at power down. On power up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). Cypress has made three nvSRAM devices that are not recommended for new design (NRND): CY14MB064J2A, CY14ME064J2A, and CY14B101J2. Cypress provides replacement options for these devices through its F-RAM products. This application note provides details on migrating from I2C nvSRAM to I2C F-RAM. It discusses the differences in package, features, and timing, and the modifications required in hardware and firmware to make the migration successful. For the nvSRAM devices that are NRND, Table 1 lists the suggested F-RAM replacement parts. www.cypress.com Document No. 002-00291 Rev. ** 1 Migrating from I2C nvSRAM to I2C F-RAM Table 1. Migration Options SI No. nvSRAM (or Original) Part Number F-RAM (or Replacement) Part Number Description 2 1 CY14MB064J2A FM24CL64B 64-Kb, 3.0-V I C Device 2 CY14ME064J2A FM24C64B 64-Kb, 5.0-V I C Device 3 CY14B101J2 FM24V10 / FM24VN10 1-Mb, 3.0-V I C Device 2 2 These suggested F-RAM parts are similar to the nvSRAM parts in read/write protocol (I2C) and density, but they are not identical. You need to be aware of the differences when replacing the nvSRAM parts. The following sections discuss the similarities and differences. 2 Overview 2.1 Package Compatibility All nvSRAM package options are supported in F-RAM, as shown in Table 2. In addition, the 3.0-V, 64-Kb F-RAM device is also offered in an 8-pin DFN package. Table 2. Package Comparison Migration Options 1 Package 2.2 2 CY14MB064J2A FM24CL64B CY14ME064J2A 8-pin SOIC Available Available Available 8-pin DFN Not Available Available Not Available 3 CY14B101J2 FM24V10/ FM24VN10 Available Available Available Not Available Not Available Not Available FM24C64B Pin Compatibility Between nvSRAM and F-RAM, all the I/O pins except pin 1 match, as described in Table 3. Pin 1 is device select pin A0 in F-RAM. Since A0 has an internal pull-down in F-RAM, it can be left floating when migrating to F-RAM. Table 3. Pin Differences SI No. Part Numbers Pin Description CY14MB064J2A All the pins are compatible except pin 1. Pin 1 is VCAP in CY14MB064J2A, while it is A0 in FM24CL64B. Since FM24CL64B does not need the VCAP pin, it provides an extra device select pin, A0, through which a maximum of eight F-RAM devices can be hooked into the 2 same I C bus. 1 versus FM24CL64B CY14ME064J2A 2 versus FM24C64B www.cypress.com Using the A0 pin will require a firmware change in existing applications. Bit 1 in the memory slave ID was “don’t care” in nvSRAM, but it should be 0 in F-RAM (assuming the A0 pin will be left unconnected or connected to VSS in F-RAM). All the pins are compatible except pin 1. Pin 1 is VCAP in CY14ME064J2A, while it is A0 in FM24C64B. Since FM24C64B does not need the VCAP pin, it provides an extra device select 2 pin, A0, through which a maximum of eight F-RAM devices can be hooked onto the same I C bus. Using the A0 pin will require a firmware change in existing applications. Bit 1 in the memory slave ID was “don’t care” in nvSRAM, but it should be 0 in F-RAM (assuming the A0 pin will be left unconnected or connected to VSS in F-RAM). Document No. 002-00291 Rev ** 2 Migrating from I2C nvSRAM to I2C F-RAM SI No. Part Numbers Pin Description CY14B101J2 3 versus All the pins are compatible. Since F-RAM does not require VCAP, pin 1 is NC (no connect). FM24V10 / FM24VN10 2.3 Instruction/Feature Set Table 4 compares all the features of nvSRAM with F-RAM. The highlighted cells show that the feature is inferior in F-RAM compared to nvSRAM. Table 4. Feature Set Comparison Migration Options 1 Feature Set 2 CY14MB064J2A FM24CL64 B Single-Byte Write Available Available Multi-Byte Write Available Hs-mode Single-Byte Write 3 Comments FM24C64B CY14B101J2 FM24V10/ FM24VN10 Available Available Available Available Available Available Available Available Available Available Not Available Available Not Available Available Available I C Hs-mode is not supported in 64-Kb F-RAM. Hs-mode Multi-Byte Write Available Not Available Available Not Available Available Available I C Hs-mode is not supported in 64-Kb F-RAM. Current Address Single-Byte Read Available Available Available Available Available Available Current Address Multi-Byte Read Available Available Available Available Available Available Hs-mode Current Address Single-Byte Read Available Not Available Available Not Available Available Available I C Hs-mode is not supported in 64-Kb F-RAM. Hs-mode Current Address Multi-Byte Read Available Not Available Available Not Available Available Available I C Hs-mode is not supported in 64-Kb F-RAM. Selective (Random) Single-Byte Read Available Available Available Available Available Available Selective (Random) Multi-Byte Read Available Available Available Available Available Available Sleep Mode Available Not Available Available Not Available Available Available 64-Kb F-RAM consumes very low standby current; hence, sleep mode is not supported. Device ID Available Not Available Available Not Available Available Available Device ID is not supported in 64-Kb F-RAM. Serial Number Available Not Available Available Not Available Available Available in FM24VN10 Serial number is not supported in 64-Kb F-RAM. – AutoStore is not applicable to F-RAM, since nonvolatile write is instantaneous. CY14ME064J2A 2 2 AutoStore 2 2 Available www.cypress.com – Available – Document No. 002-00291 Rev ** Available 3 Migrating from I2C nvSRAM to I2C F-RAM Migration Options 1 Feature Set CY14MB064J2A 2 FM24CL64 B 3 CY14ME064J2A FM24C64B CY14B101J2 Comments FM24V10/ FM24VN10 Software STORE Available – Available – Available – Software STORE is not applicable to F-RAM, since nonvolatile write is instantaneous. AutoStore Enable and Disable Available – Available – Available – AutoStore is not applicable to F-RAM. Software RECALL Available – Available – Available – Software RECALL is not applicable to F-RAM, since there are no separate NV memory cells. Status Register/ Block Protect Available Not Available Available Not Available Available Not Available Status register or block protect is not available in F-RAM. Speed 3.4 MHz, 1 MHz, 400 kHz 1 MHz, 400 kHz 3.4 MHz, 1 MHz, 400 kHz 1 MHz, 400 kHz 3.4 MHz, 1 MHz, 400 kHz 3.4 MHz, 1 MHz, 400 kHz High-speed mode is not supported in 64-Kb F-RAM. Endurance is virtually unlimited for all practical purposes for both nvSRAM and F-RAM. 6 6 10 Nonvolatile Cycles Endurance Data Retention o (at 85 C) 2.4 20 Years 10 Nonvolatile Cycles 6 10 10 Nonvolatile Cycles 14 10 Years 10 20 Years 14 10 Years 20 Years 10 14 10 Years F-RAM data retention is lower than that of nvSRAM. Parameters Table 5 provides the DC and AC parameter comparisons between 64-Kb nvSRAM and F-RAM. Except for highspeed mode, the parameters are compatible. The highlighted cells show that the feature is inferior in F-RAM compared to nvSRAM. Table 5. Parameter Comparison of 64-Kb nvSRAM and F-RAM Parameter CY14MB064J2A/ CY14ME064J2A Description Min FM24CL64B / FM24C64B Unit Max Min Max DC Parameters VCC/VDD ICC1 3 V Typical 2.7 3.6 2.7 3.65 5 V Typical 4.5 5.5 4.5 5.5 fSCL = 3.4 MHz – 1 Not Supported V Power supply Average Vcc current – fSCL = 1 MHz 400 – mA 300 (FM24CL64B) µA 400 (FM24C64B) ICC2 www.cypress.com Average Vcc current during STORE – 3 Document No. 002-00291 Rev ** N/A mA 4 Migrating from I2C nvSRAM to I2C F-RAM Parameter CY14MB064J2A/ CY14ME064J2A Description Min ICC4 Average VVCAP current during AutoStore cycle – FM24CL64B / FM24C64B Unit Max 3 Min N/A – Vcc standby current mA 6 120 (CY14MB064J2A) ISB Max (FM24CL64B) - 150 µA 10 (FM24C64B) (CY14ME064J2A) IZZ Sleep mode current – 8 Not Supported IIX Input current on I/O pin –1 +1 –1 +1 µA IOZ Output leakage current –1 +1 –1 +1 µA Ci / CO Output pin capacitance – 7 – 8 pF Ci / CI Input pin capacitance – 7 – 6 pF VIH Input HIGH voltage 0.7 x VCC VCC + 0.5 0.7 x VCC VCC + 0.3 V VIL Input LOW voltage –0.5 0.3 x VCC –0.3 0.3 x VCC V Output LOW voltage IOL = 3 mA – 0.4 – 0.4 V VOL IOL = 6 mA – 0.6 Not Supported VIN = VIL(Max) 50 – 40 – kΩ VIN = VIH(Min) 1 – 1 – MΩ 0.05 x VCC – 0.05 x VCC – V Rin Vhys Hysteresis of Schmitt trigger inputs µA V VCAP Storage capacitor 42 180 N/A µF VVCAP Maximum voltage driven on VCAP pin by the device – VCC N/A V – 3.4 Not Supported MHz – 1 – 1 MHz – 400 – 400 kHz 250 – 250 – ns Clock Frequency fSCL Clock frequency, SCL AC Switching Parameters at fSCL = 1 MHz tSU; STA Setup time for repeated START condition tHD;STA Hold time for START condition 250 – 250 – ns tLOW LOW period of the SCL 500 – 600 – ns tHIGH HIGH period of the SCL 260 – 400 – ns tSU;DATA Data in setup time 100 – 100 – ns tHD;DATA Data hold time (in/out) 0 – 0 – ns tDH Data out hold time 0 – 0 – ns tr Rise time of SDA and SCL – 120 – 300 ns tf Fall time of SDA and SCL – 120 – 100 ns tSU;STO Setup time for STOP condition 250 – 250 – ns www.cypress.com Document No. 002-00291 Rev ** 5 Migrating from I2C nvSRAM to I2C F-RAM Parameter CY14MB064J2A/ CY14ME064J2A Description Min FM24CL64B / FM24C64B Unit Max Min Max tVD;DATA Data output valid time – 400 – tVD;ACK ACK output valid time – 400 Not Specified ns – 120 Not Specified ns 500 – 500 – ns – 50 – 50 ns – ms 30 – µs/V 30 – µs/V Output fall time from VIH(min) to tOF VIL(max) Bus free time between STOP and tBUF next START condition Pulse width of spikes that must be tSP suppressed by input filter 550 ns Timing 1 (FM24CL64B) tFA (tPU) Power up to first access – 20 10 (FM24C64B) – tVCCRISE (tVR) VCC power-up ramp rate 50 tVF VCC power-down ramp rate Not Specified tSLEEP Time to enter low-power mode after issuing SLEEP instruction – 8 Not Applicable ms tWAKE (tREC) Time for wakeup from sleep mode – 20 Not Applicable ms tSB Time to enter standby mode after issuing STOP condition – 100 Not Specified µs Table 6 provides the DC and AC parameter comparisons between 1-Mb nvSRAM and F-RAM. All the parameters are compatible. The highlighted cells show that the feature is inferior in F-RAM compared to nvSRAM. Table 6. Parameter Comparison of 1-Mb nvSRAM and F-RAM CY14B101J2 Parameter FM24V10 / FM24VN10 Description Unit Min Max Min Max DC Parameters VCC/VDD Power supply ICC1 Average Vcc current 2.7 3.6 2.0 fSCL = 3.4 MHz – 1 1 fSCL = 1 MHz – 400 – 3.6 V mA 400 µA ICC2 Average Vcc current during STORE – 3 Not Applicable mA ICC4 Average VVCAP current during AutoStore cycle – 3 Not Applicable mA ISB Vcc standby current – 150 – 150 µA IZZ Sleep mode current – 8 – 8 µA IIX Input current on I/O pin –1 +1 –1 +1 µA IOZ Output leakage current –1 +1 –1 +1 µA Ci Capacitance for each I/O pin – 7 – – pF CO Output pin capacitance (SDA) – – – 8 pF www.cypress.com Document No. 002-00291 Rev ** 6 Migrating from I2C nvSRAM to I2C F-RAM CY14B101J2 Parameter FM24V10 / FM24VN10 Description Unit Min Max Min Max CI Input pin capacitance – – – 6 pF VIH Input HIGH voltage 0.7 x VCC VCC + 0.5 0.7 x VCC VCC + 0.3 V VIL Input LOW voltage –0.5 0.3 x VCC –0.3 0.3 x VCC V Output LOW voltage IOL = 3 mA – 0.4 – 0.4 V VOL IOL = 6 mA – 0.6 Not Specified VIN = VIL(Max) 50 – 50 – kΩ VIN = VIH(Min) 1 – 1 – MΩ 0.05 x VCC – 0.05 x VCC – V Rin Vhys Hysteresis of Schmitt trigger inputs V VCAP Storage capacitor 42 180 Not Applicable µF VVCAP Maximum voltage driven on VCAP pin by the device – VCC Not Applicable V – 3.4 – 3.4 MHz – 1 – 1 MHz – 400 – 400 kHz 250 – 260 – ns Clock Frequency fSCL Clock frequency, SCL AC Switching Parameters at fSCL = 1 MHz tSU;STA Setup time for repeated START condition tHD;STA Hold time for START condition 250 – 260 – ns tLOW LOW period of the SCL 500 – 500 – ns tHIGH HIGH period of the SCL 260 – 260 – ns tSU;DATA Data in setup time 100 – 50 – ns tHD;DATA Data hold time (in/out) 0 – 0 – ns tDH Data out hold time 0 – 0 – ns tr Rise time of SDA and SCL – 120 – 120 ns tf Fall time of SDA and SCL – 120 – 120 ns tSU;STO Setup time for STOP condition 250 – 260 – ns tVD;DATA Data output valid time – 400 – 450 ns tVD;ACK ACK output valid time – 400 Not Specified ns tOF Output fall time from VIH(min) to VIL(max) – 120 Not Specified ns 500 – 500 – ns – 50 – 50 ns tBUF tSP Bus free time between STOP and next START condition Pulse width of spikes that must be suppressed by input filter Timing tFA (tPU) Power up to first access 20 – 0.25 – ms tVCCRISE (tVR) VCC power-up ramp rate 50 – 50 – µs/V www.cypress.com Document No. 002-00291 Rev ** 7 Migrating from I2C nvSRAM to I2C F-RAM CY14B101J2 Parameter FM24V10 / FM24VN10 Description Unit Min Max Min tVF VCC power-down ramp rate No Restriction tSLEEP Time to enter low-power mode after issuing SLEEP instruction – 8 Not Specified tWAKE (tREC) Time for wakeup from sleep mode – 20 – tSB Time to enter standby mode after issuing STOP condition – 100 Not Specified 3 100 Max – µs/V ms 0.4 ms µs Critical Considerations Table 7 summarizes the critical considerations for each option that need to be accommodated when migrating from nvSRAM to F-RAM. Table 7. Summary of Critical Considerations SI No. Part Numbers Key Differences Pin: Pin 1 is VCAP in nvSRAM and A0 in F-RAM. CY14MB064J2A 1 versus FM24CL64B Speed: 3.4 MHz is not supported in F-RAM. F-RAM supports 1 MHz, 400 kHz, and 100 kHz. Features not required: AutoStore, software STORE, software RECALL, AutoStore Enable, and AutoStore Disable are not applicable to F-RAM. Features not supported: Sleep mode, device ID, serial number, block protect, and status register are not supported in F-RAM. Pin: Pin 1 is VCAP in nvSRAM and A0 in F-RAM. CY14ME064J2A 2 versus FM24C64B Speed: 3.4 MHz is not supported in F-RAM. F-RAM supports 1 MHz, 400 kHz, and 100 kHz. Features not required: AutoStore, software STORE, software RECALL, AutoStore Enable, and Autostore Disable are not applicable to F-RAM. Features not supported: Sleep mode, device ID, serial number, block protect, and status register are not supported in F-RAM. Pin: Pin 1 is VCAP in nvSRAM and A0 in F-RAM. CY14B101J2 3 versus FM24V10/ FM24VN10 3.1 Features not required: AutoStore, software STORE, software RECALL, AutoStore Enable, and AutoStore Disable are not applicable to F-RAM. Features not supported: Block protect and status register are not supported in F-RAM. Features with different implementation: Sleep mode, Device ID and serial number are supported, but instructions are different between nvSRAM and F-RAM. Pin Difference Pin 1 in nvSRAM is VCAP. In 64-Kb F-RAM, it is A0 and in 1-Mb F-RAM, it is NC, as shown in Figure 1 and Figure 2. Hence when migrating from nvSRAM to F-RAM, leave pin 1 floating. F-RAM has an internal pull-down to keep pin A0 LOW. Figure 1. Package Comparison of 64-Kb nvSRAM and F-RAM FM24CL64B / FM24C64 Top View not to scale www.cypress.com Document No. 002-00291 Rev ** 8 Migrating from I2C nvSRAM to I2C F-RAM Figure 2. Package Comparison of 1-Mb nvSRAM and F-RAM FM24V10 / FM24VN10 Top View not to scale 3.2 I2C Speed I2C Hs-mode is supported only in higher density (128 Kb or higher) F-RAM. Therefore, I2C speed is not an issue when migrating from 1-Mb nvSRAM to 1-Mb F-RAM. I2C speed is also not an issue when migrating from 64-Kb nvSRAM (CY14MB064J2A) to 64-Kb F-RAM (FM24CL64B) for a 1-MHz or lower I2C access. However, if Hs-mode access is a necessity, then CY14MB064J2A can migrate to a higher density F-RAM (128 Kb, FM24V01) that supports Hs-mode in the same footprint. CY14ME064J2A (5-V nvSRAM) has no replacement for Hs-mode in F-RAM. 3.3 nvSRAM Special Features The nvSRAM special features such as AutoStore, AutoStore Enable, AutoStore Disable, software STORE, and software RECALL are not applicable to F-RAM. In nvSRAM, data is first written to SRAM and then transferred to nonvolatile cells during AutoStore or software STORE. In F-RAM, data is nonvolatile instantaneously; hence, these features are not relevant. 3.4 Sleep Mode On lower density F-RAM devices (FM24CL64B and FM24C64B), the standby current is equivalent to the sleep mode currents of the nvSRAM. Hence, sleep mode is not required in low-density F-RAM. In the 1-Mb F-RAM FM24V10/FM24VN10, sleep mode is supported similar to the nvSRAM CY14B101J2. However, the sleep mode entry instructions are different, as shown in Figure 3 and Figure 4. Figure 3. Sleep Mode in nvSRAM (CY14B101J2) www.cypress.com Document No. 002-00291 Rev ** 9 Migrating from I2C nvSRAM to I2C F-RAM Figure 4. Sleep Mode in F-RAM (FM24V10) 3.5 Device ID Unlike nvSRAM, a device ID is not available in all F-RAM devices. FM24V10/FM24VN10 has a device ID similar to that in the nvSRAM counterpart, CY14B101J2. However, the instructions to read the device ID are different, as shown in Figure 5 and Figure 6. On lower density F-RAM devices (FM24CL64B and FM24C64B), a device ID is not available. However, FM24CL64B can migrate to a higher density F-RAM (128-Kb FM24V01) if a device ID is a necessity. Figure 5. Device ID Read in nvSRAM (CY14B101J2) Figure 6. Device ID Read in F-RAM (FM24V10) 3.6 Serial Number Unlike nvSRAM, a serial number is available only in the 1-Mb F-RAM device. While the standard 1-Mb FM24V10 does not have a serial number, another F-RAM part, FM24VN10, has a serial number. The serial number in nvSRAM is user configurable, but in F-RAM, it is a factory-programmed read-only number. Also, the instructions to read the serial number are different between the two, as shown in Figure 7 and Figure 8. On lower density F-RAM devices (FM24CL64B and FM24C64B), a serial number is not available. Figure 7. Serial Number Read in nvSRAM (CY14B101J2) www.cypress.com Document No. 002-00291 Rev ** 10 Migrating from I2C nvSRAM to I2C F-RAM Figure 8. Serial Number Read in F-RAM (FM24VN10) 3.7 Status Register and Block Protect Unlike nvSRAM, F-RAM does not have a status register. Hence, the block protect feature is also not supported. If you are using the block protect feature in nvSRAM, it is not available when migrating to F-RAM. However, the Write Protect (WP) pin functionality, which protects the entire memory, is the same for both nvSRAM and F-RAM. 3.8 Timing Parameters The AC parameters, tLOW and tHIGH, represent the SCL clock LOW and HIGH timing. They are the same for 1-Mb CY14B101J2 and FM24V10. For 64-Kb nvSRAM and F-RAM, they are the same except at 1 MHz. If your application is running at 1 MHz, ensure that tLOW is minimum, 600 ns, and tHIGH is minimum, 400 ns, when migrating to F-RAM. The fall time of the SDA and SCL line, tf, is 120 ns (max) for 64-Kb nvSRAM, while is it 100 ns (max) for 64-Kb F-RAM. The setup timing for repeat START (tSU;STA) and STOP (tSU;STO) and hold timing (tHD;STA) for START is slightly different. It is 260 ns for 1-Mb FM24V10 and 250 ns for CY14B101J2. The rest of the F-RAM specifications are either better than or the same as those of nvSRAM. Refer to Table 5 and Table 6 for a comparison. 3.9 Vcc Ramp Rate F-RAM has the same or a better Vcc power-up ramp rate specification than the nvSRAM. However, the power-down ramp rate specification is added in F-RAM. Ensure that the power-down ramp rates are slower than 30 µs/V in your system. 3.10 Firmware Changes The firmware for nvSRAM may contain extra logic due to nvSRAM-specific features such as AutoStore, software STORE, software RECALL, AutoStore Enable, and AutoStore Disable. This logic can be removed for F-RAM. The sleep mode, device ID, and serial number instructions are different in F-RAM; hence, the firmware needs to be modified. The power up to first access time, sleep mode entry time, and wakeup time are less in F-RAM. Hence, the firmware can be updated to reduce the wait time. Refer to Table 5 and Table 6 for more details. 4 Summary This application note discussed the options for migrating from I2C nvSRAM to I2C F-RAM devices. There are a few differences between them that need to be considered in terms of package, features, and parameters. The majority of designs that use the specified nvSRAM devices can migrate to F-RAM with minimal changes. www.cypress.com Document No. 002-00291 Rev ** 11 Migrating from I2C nvSRAM to I2C F-RAM Document History Document Title: AN200291 - Migrating from I2C nvSRAM to I2C F-RAM™ Document Number: 002-00291 Revision ** ECN 5009385 www.cypress.com Orig. of Change MEDU Submission Date 11/10/2015 Description of Change New application note. Document No. 002-00291 Rev ** 12 Migrating from I2C nvSRAM to I2C F-RAM Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb Wireless/RF cypress.com/go/wireless Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support PSoC is a registered trademark and F-RAM is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone Fax Website : 408-943-2600 : 408-943-4730 : www.cypress.com © Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 002-00291 Rev ** 13