Converting STK10C48 to STK12C68 Introduction r u ST si K1 ng 2 C C6 Y1 8 4E is 25 in N 6L R A ND in st St ea at d us of . ST K1 2C 68 . This document provides guidance on converting a design that is currently using the STK10C48 to the Simtek recommended part STK12C68. Feature set and limitations of the STK10C48 Function Category STK10C48 Autostore Software store Software recall Hardware store HSB based Hardware store NE based Package Comparison STK12C68 No No No No Yes, but can be disabled Yes Yes Yes Yes No The 300 mil dip package is available in the STK12C68 and the STK10C48 . Other packages that take less PCB area also exist such as the 350 mil SOIC. Package PKG Code N P W C si C on 300 mil SOIC – 28pin 300 mil SOIC – 28 pin 600 mil pdip -- 28 pin 300 mil cdip -- 28 pin S de 350 mil SOIC – 28 pin STK10C48 Available STK12C68 Available Available Available Not Available Not Available Not Available Available Available Available Notes Surface mount – smallest PCB area Surface mount Surface mount Through hole Through hole Issues to consider during the conversion The key difference is that the STK10C48 has a different hardware store mechanism than the STK12C68. STK12C68 will normally autostore so powering via VCAP and having VCCx open will prevent autostore. Logic explained here creates a signal to activate /HSB(hardware store) by combining the /G, /NE, /E, and /W signals used with the STK10C48. This will activate the same feature as in the STK10C48 (NE based hardware store) by instead activating /HSB. It is essential that the logic output be glitch free. In many implementations, /NE and /E signal is usually a logic decode of uppermost addresses and any decode from multiple address lines can glitch. /W signal is usually falling later in the cycle glitch-free strobe from the MPU. Please check that there is sufficient time from address change to /W falling to gate-out /E and /NE glitches. This will ensure glitch free leading edge. Also, be sure that /W rises before the address changes. (Delay in the /W signal can cause problems for the rising edge.) This is the normal situation for most MPUs (check your MPU datasheet). The /HSB signal should go low only when /G Application Note Number MA0015 0.0 is high and /E, /NE, and /W are all low. This low going pulse will activate the /HSB input which initiates a hardware store when low just like the STK10C48 does in response to /G being high, /NE, /E, and /W being low. Hardware recall is not supported in this conversion. There is no external pin on the STK12C68 to support hardware recall. Recall is automatic on power up so is in most cases not needed or used. If needed, contact Simtek applications engineering for recommendations. Improper Timing example The following timing diagram shows an unwanted situation just before the low going write pulse. /HSB output from the OR gate should not glitch by having /WRITE extend into the next cycle. This can occur if there are too much delay in the /WRITE signal. Normally, /WRITE output from an MPU will terminate well before any address change. Be sure to check the timing of address changes to /WRITE rising. This time should always be negative and any positive values risk activating /HSB inadvertently. decoding glitches /NVCE /HSB Error: /WRITE delayed letting glitches through r u ST si K1 ng 2 C C6 Y1 8 4E is 25 in N 6L R A ND in st St ea at d us of . ST K1 2C 68 . ( /NVCE: logical decode of high addresses ) /WRITE Schematic changes for conversion: The larger memory is used with identical function but with two high order address bits tied inactive. The choice of package is open with the “S” package being the most area efficient surface mount choice. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 10 9 8 7 6 5 4 3 25 24 21 /READ /CE /WRITE 22 20 27 U1 NE VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 G E W VSS 28 from power plane +5v 11 12 13 15 16 17 18 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 14 STK10C48 C1-bypass 0.1 uF de 1 must use gnd plane C on Before Conversion schematic si /NVCE Application Note Number MA0015 0.0 Here, A11 and A12 are tied low and only 2k x 8 of the available memory is used. The power is applied to VCAP (pin 1) and VCCx (pin 28) is left open which prevents autostore. The bypass capacitor, C1, is best if tightly connected to pin 1. Logic as shown creates the /HSB signal. Adjust the timing of inputs to ensure a glitch free output as needed with additional logic or delays (explained above in detail). A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 U3 2 /WRITE 1 2 3 4 5 U2 1 /READ /CE /WRITE OR4 10 9 8 7 6 5 4 3 25 24 21 23 2 26 22 20 27 U1 VCAP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 HSB G E W VCCx DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 28 11 12 13 15 16 17 18 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS 14 STK12C68-W45I r u ST si K1 ng 2 C C6 Y1 8 4E is 25 in N 6L R A ND in st St ea at d us of . ST K1 2C NOT must use gnd plane on si de After Conversion schematic C /READ /NVCE /CE 1 . from power plane +5v 68 closest to pin Moved from VCC C1-bypass 0.1uF Application Note Number MA0015 0.0 Corresponding pin Connection Pin for pin comparison of the two parts is given in the table below: W# VCC W# VCCX 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 . A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E# A10 G# A11 A9 A8 HSB Hook VCAP to system VCC Unhook /NE and connect to OR gate input (see schematic) Ground pin A12 “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ Also, connect to OR gate input (See schematic) “ Also, connect to OR gate input (See schematic) Ground A11 pin No change “ Also, connect to OR gate output (see schematic above) Also connect to OR gate input 12C68 VCCx should be open C on si de r u ST si K1 ng 2 C C6 Y1 8 4E is 25 in N 6L R A ND in st St ea at d us of . ST K1 2C N/C A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E# A10 G# NC A9 A8 N/C Comments 68 STK10C48 STK12C68 Pin NAME NAME /NE VCAP 1 27 28 Application Note Number MA0015 0.0