SIMTEK STK10C48

STK10C48
2K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
DESCRIPTION
• 25ns, 35ns and 45ns Access Times
• STORE to Nonvolatile Elements Initiated by
Hardware
• RECALL to SRAM Initiated by Hardware or
Power Restore
• Automatic STORE Timing
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Elements
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 28-Pin 300 mil PDIP, 300 mil SOIC and
350 mil SOIC Packages
The Simtek STK10C48 is a fast static RAM with a nonvolatile element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in the Nonvolatile Elements. Data may easily
be transferred from the SRAM to the Nonvolatile Elements (the STORE operation), or from the Nonvolatile
Elements to the SRAM (the RECALL operation), using
the NE pin. Transfers from the Nonvolatile Elements to
the SRAM (the RECALL operation) also take place automatically on restoration of power. The STK10C48
combines the high performance and ease of use of a
fast SRAM with nonvolatile data integrity.
The STK10C48 features industry-standard pinout for
nonvolatile RAMs.
PIN CONFIGURATIONS
BLOCK DIAGRAM
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
A6
A7
A8
A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
INPUT BUFFERS
A5
ROW DECODER
Quantum Trap
32 x 512
STORE
STATIC RAM
ARRAY
32 x 512
RECALL
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
NC
A8
A9
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
28 - 300 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
COLUMN I/O
STORE/
RECALL
CONTROL
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
NE
E
W
March 2006
1
1
A0 - A10
Address Inputs
W
Write Enable
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
NE
Nonvolatile Enable
VCC
Power (+ 5V)
VSS
Ground
Document Control # ML0002 rev 0.2
STK10C48
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
(VCC = 5.0V ± 10%)
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
INDUSTRIAL
PARAMETER
UNITS
MIN
MAX
MIN
NOTES
MAX
ICC1b
Average VCC Current
85
75
65
90
75
65
mA
mA
mA
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
ICC2c
Average VCC Current during STORE
3
3
mA
All Inputs Don’t Care, VCC = max
Average VCC Current at tAVAV = 200ns
5V, 25°C, Typical
10
10
mA
W ≥ (V CC – 0.2V)
All Others Cycling, CMOS Levels
25
21
18
26
22
19
mA
mA
mA
tAVAV = 25ns, E ≥ VIH
tAVAV = 35ns, E ≥ VIH
tAVAV = 45ns, E ≥ VIH
750
750
μA
E ≥ (V CC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
ICC3
b
ISB1d
Average VCC Current
(Standby, Cycling TTL Input Levels)
ISB2d
VCC Standby Current
(Standby, Stable CMOS Input Levels)
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off-State Output Leakage Current
±5
±5
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.2
VCC + .5
2.2
VCC + .5
V
All Inputs
VIL
Input Logic “0” Voltage
VSS – .5
0.8
VSS – .5
0.8
V
All Inputs
VOH
Output Logic “1” Voltage
V
IOUT = – 4mA
VOL
Output Logic “0” Voltage
0.4
V
IOUT = 8mA
TA
Operating Temperature
85
°C
2.4
2.4
0.4
0
70
–40
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE ) .
Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEe
SYMBOL
5.0V
(TA = 25°C, f = 1.0MHz)
PARAMETER
MAX
UNITS
CONDITIONS
CIN
Input Capacitance
8
pF
ΔV = 0 to 3V
COUT
Output Capacitance
7
pF
ΔV = 0 to 3V
480 Ohms
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
March 2006
2
Document Control # ML0002 rev 0.2
STK10C48
(VCC = 5.0V ± 10%)
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
STK10C48-25
STK10C48-35
STK10C48-45
PARAMETER
#1, #2
1
tELQV
2
f
tAVAV
g
3
tAVQV
4
tGLQV
5
tAXQX
6
tELQX
UNITS
Alt.
g
h
MIN
25
tAA
Address Access Time
25
35
45
ns
tOE
Output Enable to Data Valid
10
15
20
ns
tOH
Output Hold after Address Change
5
5
5
ns
tLZ
Chip Enable to Output Active
5
5
5
ns
25
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZh
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
tEHICCLd, e
35
MAX
Read Cycle Time
Chip Disable to Output Inactive
tELICCH
MIN
tRC
tHZ
11
MAX
Chip Enable Access Time
tEHQZ
10
MIN
tACS
7
e
MAX
45
35
45
10
0
13
0
ns
15
0
0
10
13
0
35
ns
ns
15
0
25
ns
ns
ns
45
ns
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledf
2
tAVAV
ADDRESS
1
11
tELQV
E
tEHICCL
6
tELQX
7
tEHQZ
G
9
tGHQZ
4
8
tGLQV
tGLQX
DQ (DATA OUT)
DATA VALID
10
tELICCH
ICC
March 2006
ACTIVE
STANDBY
3
Document Control # ML0002 rev 0.2
STK10C48
(VCC = 5.0V ± 10%)
SRAM WRITE CYCLES #1 & #2
SYMBOLS
STK10C48-25
NO.
STK10C48-35
STK10C48-45
PARAMETER
UNITS
#1
#2
Alt.
12
tAVAV
tAVAV
tWC
Write Cycle Time
25
35
45
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
25
30
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
25
30
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
12
15
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
25
30
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
0
ns
20
tWLQZh, i
tWZ
Write Enable to Output Disable
21
tWHQX
tOW
Output Active after End of Write
Note i:
Note j:
MIN
MAX
MIN
MAX
10
5
MIN
13
5
MAX
15
5
ns
ns
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ VIH during address transitions. NE ≥ VIH.
SRAM WRITE CYCLE #1: W Controlledj
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
tAVWL
13
tWLWH
W
16
tWHDX
15
tDVWH
DATA IN
DATA VALID
20
tWLQZ
DATA OUT
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
tAVAV
ADDRESS
18
19
14
tAVEL
tEHAX
tELEH
E
17
tAVEH
13
W
tWLEH
16
15
tEHDX
tDVEH
DATA IN
DATA OUT
March 2006
DATA VALID
HIGH IMPEDANCE
4
Document Control # ML0002 rev 0.2
STK10C48
MODE SELECTION
E
W
G
NE
MODE
POWER
H
X
X
X
Not Selected
Standby
L
H
L
H
Read SRAM
Active
L
L
X
H
Write SRAM
Active
k
L
H
L
L
Nonvolatile RECALL
Active
L
L
H
L
Nonvolatile STORE
ICC2
L
L
L
H
L
H
L
X
No Operation
Active
Note k: An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE.
(VCC = 5.0V ± 10%)
STORE CYCLES #1 & #2
SYMBOLS
NO.
PARAMETER
#1
#2
MIN
MAX
UNITS
10
ms
Alt.
22
tWLQXl
tELQX
tSTORE
STORE Cycle Time
23
tWLNHm
tELNH
tWC
STORE Initiation Cycle Time
20
ns
24
tGHNL
Output Disable Set-up to NE Fall
0
ns
tGHEL
Output Disable Set-up to E Fall
0
ns
tNLEL
NE Set-up
0
ns
Chip Enable Set-up
0
ns
Write Enable Set-up
0
ns
25
26
tNLWL
27
tELWL
28
tWLEL
Note l: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V.
Note m: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate
the STORE initiation cycle.
Note n: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated.
STORE CYCLE #1: W Controlledn
NE
G
24
tGHNL
26
tNLWL
23
tWLNH
W
E
DQ (DATA OUT)
27
tELWL
22
tWLQX
HIGH IMPEDANCE
STORE CYCLE #2: E Controlledn
26
tNLEL
NE
25
tGHEL
G
W
28
tWLEL
23
tELNH
E
DQ (DATA OUT)
March 2006
22
tELQX
HIGH IMPEDANCE
5
Document Control # ML0002 rev 0.2
STK10C48
STORE INHIBIT/POWER-UP RECALL
(VCC = 5.0V + 10%)
SYMBOLS
STK10C48
NO.
PARAMETER
UNITS NOTES
Standard
MIN
29
tRESTORE
Power-up RECALL Duration
30
tSTORE
STORE Cycle Duration
31
VSWITCH
Low Voltage Trigger Level
32
VRESET
Low Voltage Reset Level
4.0
MAX
550
μs
10
ms
4.5
V
3.6
V
o
Note o: tRESTORE starts from the time VCC rises above VSWITCH.
STORE INHIBIT/POWER-UP RECALL
VCC
5V
31
VSWITCH
32
VRESET
STORE INHIBIT
POWER-UP RECALL
29
tRESTORE
DQ (DATA OUT)
POWER-UP
RECALL
March 2006
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
6
Document Control # ML0002 rev 0.2
STK10C48
(VCC = 5.0V ± 10%)
RECALL CYCLES #1, #2 & #3
SYMBOLS
NO.
PARAMETER
#1
#2
#3
MIN
MAX
UNITS
20
μs
33
tNLQXp
tELQX
tGLQX
RECALL Cycle Time
34
q
tELNH
tGLNH
RECALL Initiation Cycle Time
20
ns
tNLEL
tNLGL
NE Set-up
0
ns
Output Enable Set-up
0
ns
ns
tNLNH
35
36
tGLNL
tGLEL
37
tWHNL
tWHEL
tWHGL
Write Enable Set-up
0
38
tELNL
tGLEL
tELGL
Chip Enable Set-up
0
39
tNLQZ
NE Fall to Outputs Inactive
20
ns
40
tRESTORE
Power-up RECALL Duration
550
μs
ns
Note p: Measured with W and NE both high, and G and E low.
Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate
the RECALL initiation cycle.
Note r: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1: NE Controlledn
34
tNLNH
NE
36
tGLNL
G
W
37
tWHNL
E
38
tELNL
33
tNLQX
39
tNLQZ
HIGH IMPEDANCE
DQ (DATA OUT)
RECALL CYCLE #2: E Controlledn
35
tNLEL
NE
36
tGLEL
G
W
37
tWHEL
34
tELNH
E
DQ (DATA OUT)
33
tELQX
HIGH IMPEDANCE
RECALL CYCLE #3: G Controlledn, r
35
tNLGL
NE
G
W
34
tGLNH
37
tWHGL
38
tELGL
E
DQ (DATA OUT)
March 2006
33
tGLQX
HIGH IMPEDANCE
7
Document Control # ML0002 rev 0.2
STK10C48
DEVICE OPERATION
NONVOLATILE STORE
The STK10C48 has two modes of operation: SRAM
mode and nonvolatile mode, determined by the
state of the NE pin. When in SRAM mode, the memory operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to Nonvolatile Elements or from Nonvolatile
Elements to SRAM.
A STORE cycle is performed when NE, E and W and
low and G is high. While any sequence that
achieves this state will initiate a STORE, only W initiation (STORE cycle #1) and E initiation (STORE cycle
#2) are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
STORE cycle, previous nonvolatile data is erased
and the SRAM contents are then programmed into
nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled and the
DQ0-7 pins are tri-stated until the cycle is complete.
NOISE CONSIDERATIONS
Note that the STK10C48 is a high-speed memory
and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
If E and G are low and W and NE are high at the end
of the cycle, a READ will be performed and the outputs will go active, signaling the end of the STORE.
SRAM READ
NONVOLATILE RECALL
The STK10C48 performs a READ cycle whenever E
and G are low and NE and W are high. The address
specified on pins A0-10 determines which of the 2,048
data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be
valid after a delay of tAVQV (READ cycle #1). If the
READ is initiated by E or G, the outputs will be valid
at tELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the tAVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W or NE is brought low.
A RECALL cycle is performed when E, G and NE are
low and W is high. Like the STORE cycle, RECALL is
initiated when the last of the four clock signals goes
to the RECALL state. Once initiated, the RECALL
cycle will take tNLQX to complete, during which all
inputs are ignored. When the RECALL completes,
any READ or WRITE state on the input pins will take
effect.
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be
recalled an unlimited number of times.
SRAM WRITE
As with the STORE cycle, a transition must occur on
any one control pin to cause a RECALL, preventing
inadvertent multi-triggering. On power up, once VCC
exceeds 4.25V, a RECALL cycle is automatically initiated. Due to this automatic RECALL, SRAM operation
cannot commence until tRESTORE after VCC exceeds
4.25V.
A WRITE cycle is performed whenever E and W are
low and NE is high. The address inputs must be stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
POWER-UP RECALL
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
March 2006
During power up, or after any low-power condition
(VCC < 3.0V), an internal RECALL request will be
latched. When VCC once again exceeds 4.25V, a
RECALL cycle will automatically be initiated and will
take tRESTORE to complete.
8
Document Control # ML0002 rev 0.2
STK10C48
LOW AVERAGE ACTIVE POWER
If the STK10C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
The STK10C48 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK10C48 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the VCC level; and 7) I/O loading.
HARDWARE PROTECT
The STK10C48 offers two levels of protection to
suppress inadvertent STORE cycles. If the control
signals (E, G, W and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE
cycle will not be started. The STORE (or RECALL)
will be initiated only after a transition on any one of
these signals to the required state. In addition to
multi-trigger protection, STOREs are inhibited when
VCC is below 4.0V, protecting against inadvertent
STOREs.
100
Average Active Current (mA)
Average Active Current (mA)
100
80
60
40
TTL
20
80
60
TTL
40
CMOS
20
CMOS
0
0
50
100
150
Cycle Time (ns)
200
50
Figure 2: ICC (max) Reads
March 2006
100
150
Cycle Time (ns)
200
Figure 3: ICC (max) Writes
9
Document Control # ML0002 rev 0.2
STK10C48
ORDERING INFORMATION
STK10C48 - P F 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
P = Plastic 28-pin 300 mil DIP
N = Plastic 28-pin 300 mil SOIC
S = Plastic 28-pin 350 mil SOIC
March 2006
10
Document Control # ML0002 rev 0.2
STK10C48
Document Revision History
Revision
Date
Summary
0.0
December 2002
Removed 20 nsec device.
0.1
September 2003
Added lead-free lead finish
0.2
March 2006
Marked as Obsolete, Not recommended for new design.
March 2006
11
Document Control # ML0002 rev 0.2
STK10C48
March 2006
12
Document Control # ML0002 rev 0.2