STK22C48 2Kx8 AutoStore nvSRAM FEATURES DESCRIPTION • 25, 45 ns Read Access & R/W Cycle Times The Simtek STK22C48 is a 16Kb fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell. • Unlimited Read/Write Endurance • Automatic Non-Volatile STORE on Power Loss The SRAM provides the fast access & cycle times, ease of use, and unlimited read & write endurance of a normal SRAM. • Non-Volatile STORE Under Hardware Control • Automatic RECALL to SRAM on Power Up • Unlimited RECALL Cycles Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power-up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. • 1 Million STORE Cycles • 100-Year Non-volatile Data Retention • Single 5.0V +10% Operation • Commercial, Industrial, and Military Temperatures The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is the highest-performance, most reliable non-volatile memory available. • 28-Pin 300 mil SOIC or 330 mil SOIC (RoHSCompliant) BLOCK DIAGRAM VCCX A6 A7 A8 A9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 INPUT BUFFERS A5 ROW DECODER Quantum Trap 32 x 512 STORE STATIC RAM ARRAY 32 x 512 RECALL VCAP POWER CONTROL STORE/ RECALL CONTROL HSB COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 G E W This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status. 1 Document Control #ML0004 Rev 2.0 Feb, 2008 STK22C48 PIN CONFIGURATIONS VCAP NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 (TOP) 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCCX W HSB A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28-pin 300 mil SOIC 28-pin 330 mil SOIC PIN DESCRIPTIONS Pin Name I/O Description A10-A0 Input Address: The 11 address inputs select one of 2,048 bytes in the nvSRAM array DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM E Input Chip Enable: The active low E input selects the device W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. VCC Power Supply Power: 5.0V, ±10% VSS Power Supply Ground Document Control #ML0004 Rev 2.0 Feb, 2008 2 STK22C48 a ABSOLUTE MAXIMUM RATINGS Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Package Thermal Characteristics - See Website at http://www.simtek.com (VCC = 5.0V ± 10%)e DC CHARACTERISTICS SYMBOL COMMERCIAL PARAMETER MIN INDUSTRIAL MAX MIN MAX UNITS NOTES ICC1b Average VCC Current 85 65 90 65 mA mA tAVAV = 25ns tAVAV = 45ns ICC2c Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max ICC3b Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical 10 10 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels ICC4c Average VCAP Current during AutoStore Cycle 2 2 mA ISB1d Average VCC Current (Standby, Cycling TTL Input Levels) 25 18 26 19 mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH ISB2d VCC Standby Current (Standby, Stable CMOS Input Levels) 1.5 1.5 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) IILK Input Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±5 ±5 μA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage V IOUT = – 4mA except HSB VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 8mA except HSB VBL Logic “0” Voltage on HSB Output 0.4 0.4 V IOUT = 3mA TA Operating Temperature 0 70 –40 85 °C VCAP Storage Capacitance 61 220 61 220 μF Note b: Note c: Note d: Note e: 2.4 2.4 All Inputs Don’t Care 5 Volt rated, 68 μF+20%/-10% Nom. ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. AC TEST CONDITIONS 5.0V Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEf SYMBOL 480 Ohms OUTPUT (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 8 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V 255 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading Note f: These parameters are guaranteed but not tested. Document Control #ML0004 Rev 2.0 Feb, 2008 3 STK22C48 (VCC = 5.0V ± 10%)e SRAM READ CYCLES #1 & #2 SYMBOLS NO. STK22C48-25 STK22C48-45 MIN MIN PARAMETER #1, #2 UNITS Alt. MAX 1 tELQV tACS Chip Enable Access Time 2 tAVAVg, tELEHg tRC Read Cycle Time 3 tAVQVh tAA Address Access Time 25 45 ns 4 tGLQV tOE Output Enable to Data Valid 10 20 ns 5 tAXQXh tOH Output Hold after Address Change 5 6 tELQX tLZ Address Change or Chip Enable to Output Active 5 7 tEHQZi tHZ Address Change or Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZi tOHZ Output Disable to Output Inactive 10 tELICCHf tPA Chip Enable to Power Active 11 f tPS Chip Disable to Power Standby tEHICCL 25 MAX 45 25 45 0 0 10 0 0 25 3 tAVQV tAXQX DATA VALID SRAM READ CYCLE #2: E and G Controlledg ADDR ESS 2 E 27 29 6 t EHAX 11 t EHI CC L t ELQ X 7 t EHQ Z 3 t AV QV G 9 t GH Q Z 4 8 tG L Q X t G L QV DQ (D ATA OUT) DAT A VAL ID 10 t ELI CC H AC T IVE I CC ST AND BY Document Control #ML0004 Rev 2.0 Feb, 2008 4 ns ns 45 ADDRESS ns ns 15 2 tAVAV t E LE H 1 tEL Q V ns 15 SRAM READ CYCLE #1: Address Controlledg, h DQ (DATA OUT) ns 5 Note g: W and HSB must be high during SRAM READ cycles. Note h: Device is continuously selected with E and G both low. Note i: Measured ± 200mV from steady state output voltage. 5 ns 5 10 ns ns STK22C48 (VCC = 5.0V ± 10%)e SRAM WRITE CYCLES #1 & #2 SYMBOLS STK22C48-25 NO. STK22C48-45 PARAMETER UNITS #1 #2 Alt. MIN MAX MIN MAX 12 tAVAV tAVAV tWC Write Cycle Time 25 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 ns 20 tWLQZ i, j tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write 10 5 5 Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be ≥ VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles. SRAM WRITE CYCLE #1: W Controlledk, l 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ HIGH IMPEDANCE PREVIOUS DATA 21 tWHQX SRAM WRITE CYCLE #2: E Controlledk, l 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH 13 tWLEH W 15 tDVEH DATA IN DATA OUT Document Control #ML0004 Rev 2.0 Feb, 2008 16 tEHDX DATA VALID HIGH IMPEDANCE 5 15 ns ns STK22C48 HARDWARE MODE SELECTION E W HSB A12 - A0 (hex) MODE I/O POWER H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active X X L X Nonvolatile STORE Output High Z lCC2 NOTES n m Note m: HSB STORE operation occurs only if an SRAM write has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises. Note n: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. (VCC = 5.0V ± 10%)e HARDWARE STORE CYCLE SYMBOLS STK22C48 NO. PARAMETER Standard Alternate 22 tSTORE tHLHZ STORE Cycle Duration 23 tDELAY tHLQZ Time Allowed to Complete SRAM Cycle 24 tRECOVER tHHQX Hardware STORE High to Inhibit Off 25 tHLHX Hardware STORE Pulse Width 26 tHLBL Hardware STORE Low to Store Busy UNITS NOTES MIN MAX 10 1 700 15 ms i, o μs i, p ns o, q ns 300 ns Note o: E and G low for output behavior. Note p: E and G low and W high for output behavior. Note q: tRECOVER is only applicable after tSTORE is complete. HARDWARE STORE CYCLE 25 tHLHX HSB (IN) 24 tRECOVER 22 tSTORE 26 tHLBL HSB (OUT) HIGH IMPEDANCE HIGH IMPEDANCE 23 tDELAY DQ (DATA OUT) DATA VALID DATA VALID Document Control #ML0004 Rev 2.0 Feb, 2008 6 STK22C48 (VCC = 5.0V ± 10%)e AutoStore™/POWER-UP RECALL SYMBOLS STK22C48 NO. PARAMETER Standard Alternate MIN 550 μs r STORE Cycle Duration 10 ms p, s tRESTORE 28 tSTORE 29 tVSBL 30 tDELAY 31 VSWITCH Low Voltage Trigger Level 32 VRESET Low Voltage Reset Level Low Voltage Trigger (VSWITCH) to HSB Low tBLQZ NOTES Power-up RECALL Duration 27 tHLHZ UNITS MAX 300 Time Allowed to Complete SRAM Cycle 1 4.0 ns l μs o 4.5 V 3.6 V Note r: tRESTORE starts from the time VCC rises above VSWITCH. Note s: HSB is asserted low for 1μs when VCAP drops through VSWITCH. If an SRAM write has not taken place since the last nonvolatile cycle, HSB will be released and no STORE will take place. AutoStore™/POWER-UP RECALL VCC 31 VSWITCH 32 VRESET AutoStoreTM POWER-UP RECALL 29 tVSBL 27 tRESTORE 28 tSTORE HSB 30 tDELAY W DQ (DATA OUT) POWER-UP RECALL BROWN OUT NO STORE (NO SRAM WRITES) BROWN OUT AutoStore BROWN OUT AutoStore NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH Document Control #ML0004 Rev 2.0 Feb, 2008 7 STK22C48 nvSRAM OPERATION The STK22C48 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to Nonvolatile Elements (the STORE operation) or from Nonvolatile Elements to SRAM (the RECALL operation). In this mode SRAM functions are disabled. NOISE CONSIDERATIONS The STK22C48 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between VCAP and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK22C48 performs a READ cycle whenever E and G are low and W and HSB are high. The address specified on pins A0-10 determines which of the 2,048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low. POWER-UP RECALL During power up, or after any low-power condition (VCAP < VRESET), an internal RECALL request will be latched. When VCAP once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK22C48 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. AutoStore MODE The STK22C48 can be powered in one of three modes. During normal AutoStore operation, the STK22C48 will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC and initiate a STORE operation. Figure 2 shows the proper connection of capacitors for automatic store operation. A charge storage capacitor having a capacity of between 68μF and 220μF (± 20%) rated at 6V should be provided. In system power mode, both VCC and VCAP are connected to the + 5V power supply without the 68μF capacitor. In this mode the AutoStore function of the SRAM WRITE It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. 1 32 10kΩ 10k Ω∗ 31 + 0.1μF Bypass 30 68μF 6v, ±20% A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. 16 17 Figure 2: AutoStore Mode *If HSB is not used, it should be left unconnected. Document Control #ML0004 Rev 2.0 Feb, 2008 8 STK22C48 STK22C48 will operate on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10ms STORE cycle. AutoStore INHIBIT MODE 1 10KΩ 10K? 10KΩ 10K? 0.1µF Bypass If an automatic STORE on power loss is not required, then VCC can be tied to ground and + 5V applied to VCAP (Figure 3). This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the STK22C48 is operated in this configuration, references to VCC should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered with the HSB pin. To enable or disable AutoStore using an IO port pin, see “PREVENTING STORES” on page 9. 32 31 30 16 17 Figure 3: AutoStore Inhibit Mode In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. If the power supply drops faster than 20 μs/volt before VCC reaches VSWITCH, then a 2.2 ohm resistor should be inserted between VCC and the system supply to avoid momentary excess of current between Vcc and Vcap. HSB OPERATION The STK22C48 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven low, the STK22C48 will conditionally initiate a STORE operation after tDELAY; an actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pullup and is internally driven low to indicate a busy Document Control #ML0004 Rev 2.0 Feb, 2008 9 condition while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a driver. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK22C48 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple STK22C48s while using a single larger capacitor. To operate in this mode the HSB pin should be connected together to the HSB pins from the other STK22C48s. An external pull-up resistor to + 5V is required since HSB acts as an open drain pull down. The VCAP pins from the other STK22C48 parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the STK22C48s detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those STK22C48s that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the STK22C48 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK22C48 will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected. PREVENTING STORES The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20μs at the onset of a STORE. When the STK22C48 is connected for AutoStore operation (system VCC connected to VCC and a 68μF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK22C48 will attempt to pull HSB low; if HSB doesn’t actually get below VIL, the part will stop trying to pull HSB low and abort the STORE attempt. STK22C48 HARDWARE PROTECT The STK22C48 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. AutoStore can be completely disabled by tying VCCX to ground and applying + 5V to VCAP. This is the AutoStore Inhibit mode; in this mode STOREs are only initiated by explicit request using the HSB pin. LOW AVERAGE ACTIVE POWER shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 5 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK22C48 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. The STK22C48 draws significantly less current when it is cycled at times longer than 50ns. Figure 4 100 80 Average Active Current (mA) Average Active Current (mA) 100 60 40 TTL 20 80 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 Cycle Time (ns) 200 50 200 Figure 5: Icc (max) Writes Figure 4: Icc (max) Reads Document Control #ML0004 Rev 2.0 Feb, 2008 100 150 Cycle Time (ns) 10 STK22C48 BEST PRACTICES nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: • The non-volatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. • Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the Document Control #ML0004 Rev 2.0 Feb, 2008 11 desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.). • The Vcap value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers that want to use a larger Vcap value to make sure there is extra store charge should discuss their Vcap size selection with Simtek. STK22C48 ORDERING INFORMATION STK22C48 - N F 45 I TR Packing Option Blank = Tube TR = Tape and Reel Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (-40 to 85°C) Access Time 25 = 25ns 45 = 45ns Lead Finish F = 100% Sn (Matte Tin) Package N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 330 mil SIOC Document Control #ML0004 Rev 2.0 Feb, 2008 12 STK22C48 Ordering Information Item Number STK22C48-NF25 STK22C48-NF45 STK22C48-SF25 STK22C48-SF45 Item Name 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM SOP28-300 SOP28-300 SOP28-330 SOP28-330 Access Times 25 ns access time 45 ns access time 25 ns access time 45 ns access time Temperature Commercial Commercial Commercial Commercial STK22C48-NF25TR 5V 2Kx 8 AutoStore nvSRAM SOP28-300 25 ns access time Commercial STK22C48-NF45TR STK22C48-SF25TR STK22C48-SF45TR STK22C48-NF25I STK22C48-NF45I STK22C48-SF25I STK22C48-SF45I STK22C48-NF25ITR STK22C48-NF45ITR STK22C48-SF25ITR STK22C48-SF45ITR 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 5V 2Kx 8 AutoStore nvSRAM 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Document Control #ML0004 Rev 2.0 Feb, 2008 SOP28-300 SOP28-330 SOP28-330 SOP28-300 SOP28-300 SOP28-330 SOP28-330 SOP28-300 SOP28-300 SOP28-330 SOP28-330 13 STK22C48 Package Diagrams 28-Lead, 300 mil SOIC Gull Wing ( 0.292 7.42 0.300 7.59 ) 0.400 10.16 0.410 10.41 ( Pin 1 Index .050 (1.27) BSC ( 0.701 17.81 0.711 18.06 ) 0.097 2.46 0.104 2.64 ( ) ( 0.090 2.29 0.094 2.39 0.014 0.35 0.019 0.48 ( 0.009 0.23 0.013 0.32 ( ( 0.005 0.12 0.012 0.29 ) ( 0.024 0.61 Document Control #ML0004 Rev 2.0 Feb, 2008 ) 0° 8° ) 14 ) ) DIM = INCHES DIM = mm MIN MAX MIN ) ( MAX ) STK22C48 28-Lead, 330 mil SOIC Gull Wing 0.713 0.733 ( 18.11 ) 18.62 0.112 (2.845) 0.020 0.014 ( 0.508 ) 0.356 0.050 (1.270) 0.103 0.093 0.336 0.326 0.004 (0.102) ( 2.616 ) 2.362 ( 8.534 ) 8.280 0.477 0.453 ( 12.116 ) 11.506 Pin 1 0.014 0.008 10° 0° ( 0.356 ) 0.203 0.044 0.028 DIM = INCHES MIN ) ( MAX DIM = mm Document Control #ML0004 Rev 2.0 Feb, 2008 MIN MAX 15 ( 1.117 ) 0.711 STK22C48 Document Revision History Revision Date Summary 0.0 December 2002 Removed 20 nsec device. 0.1 September 2003 Added lead-free lead finish 0.2 March 2006 Obsolete: 35ns speed grade, Plastic DIP packages and Leaded Lead Finish 0.3 February 2007 Add Fast Power-Down Slew Rate Information Add Tape Reel Ordering Options Add Product Ordering Code Listing Add Package Drawings Reformat Entire Document 2.0 January 2008 In the block diagram and elsewhere in this data sheet, removed the “x” from Vccx. Page 4: in SRAM Read Cycles #1 & #2 table, revised description for tELQX and tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time. Page 4: updated SRAM Read Cycle #2 timing diagram and changed title to add G controlled. Page 9: under HSB Operation, revised first paragraph to read “The HSB pin has a very resistive pullup...” Page 11: added best practices section. Page 13: added access times to Ordering Information table. SIMTEK STK22C48 Datasheet, January 2008 Copyright 2008, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right. Document Control #ML0004 Rev 2.0 Feb, 2008 16