CY7C024AV/025AV/026AV 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM Features ■ INT flag for port-to-port communication ■ True dual-ported memory cells which enable simultaneous access of the same memory location ■ Separate upper byte and lower byte control ■ Pin select for Master or Slave (M/S) ■ 4, 8 or 16 K × 16 organization (CY7C024AV/025AV/026AV) ■ Commercial and industrial temperature ranges 0.35 micron CMOS for optimum speed and power ■ Available in 100-pin Pb-free TQFP and 100-pin TQFP ■ ■ High speed access: 20 ns and 25 ns ■ Low operating power ❐ Active: ICC = 115 mA (typical) ❐ Standby: ISB3 = 10 A (typical) ■ Fully asynchronous operation ■ Automatic power down ■ Expandable data bus to 32 bits or more using Master and Slave chip select when using more than one device ■ On chip arbitration logic ■ Semaphores included to permit software handshaking between ports Functional Description The CY7C024AV/025AV/026AV consist of an array of 4 K, 8 K, and 16 K words of 16 bits each of dual-port RAM cells, IO and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes and reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be used for port to port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). They also have an automatic power down feature controlled by CE. Each port has its own output enable control (OE), which enables data to be read from the device. For a complete list of related resources, click here. Selection Guide CY7C024AV/025AV/026AV -20 CY7C024AV/025AV/026AV -25 Unit Maximum Access Time 20 25 ns Typical Operating Current 120 115 mA Typical Standby Current for ISB1 (Both ports TTL Level) 35 30 mA Typical Standby Current for ISB3 (Both ports CMOS Level) 10 10 A Parameter Cypress Semiconductor Corporation Document Number: 38-06052 Rev. *R • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 11, 2014 CY7C024AV/025AV/026AV Logic Block Diagram R/WL UBL R/WR UBR CEL CER LBL LBR OEL OER [1] IO8L–IO15L IO0L–IO7L[2] 8 8 12/13/14 IO Control A0L–A11/1213L Address Decode [3] 12/13/14 [3] [1] 8 True Dual-Ported RAM Array A0L–A11/12/13L CEL OEL R/WL SEML [4] BUSYL INTL UBL LBL 8 IO Control IO8L– IO15R [2] IO0L– IO7R Address Decode 12/13/14 [3] A0R–A11/12/13R [3] 12/13/14 Interrupt Semaphore Arbitration A0R–A11/12/13R CER OER R/WR SEMR [4] M/S BUSYR INTR UBR LBR Notes 1. IO8–IO15 for × 16 devices 2. IO0–IO7 for × 16 devices 3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices. 4. BUSY is an output in master mode and an input in slave mode. Document Number: 38-06052 Rev. *R Page 2 of 24 CY7C024AV/025AV/026AV Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Write Operation ........................................................... 6 Read Operation ........................................................... 7 Interrupts ..................................................................... 7 Busy ............................................................................ 7 Master/Slave ............................................................... 7 Semaphore Operation ................................................. 8 Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 Electrical Characteristics ................................................. 9 Capacitance .................................................................... 10 AC Test Loads and Waveforms ..................................... 10 Data Retention Mode ...................................................... 10 Timing .............................................................................. 10 Switching Characteristics .............................................. 11 Switching Waveforms .................................................... 13 Document Number: 38-06052 Rev. *R Ordering Information ...................................................... 19 4 K × 16 3.3 V Asynchronous Dual-Port SRAM ........ 19 8 K × 16 3.3 V Asynchronous Dual-Port SRAM ........ 19 16 K × 16 3.3 V Asynchronous Dual-Port SRAM ...... 19 Ordering Code Definitions ......................................... 19 Package Diagram ............................................................ 20 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC® Solutions ...................................................... 24 Cypress Developer Community ................................. 24 Technical Support ..................................................... 24 Page 3 of 24 CY7C024AV/025AV/026AV Pin Configurations A7L A6L A9L A8L UBL LBL NC [5] A11L A10L OEL VCC R/WL SEML CEL IO 1L IO 0L IO 4L IO 3L IO 2L GND IO 9L IO 8L IO 7L IO 6L IO 5L Figure 1. 100-pin TQFP pinout (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CY7C024AV (4 K × 16) CY7C025AV (8 K × 16) NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IO 7R IO 8R IO 9R IO 10R IO 11R IO 12R IO 13R IO 14R GND IO 15R ŒR VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R NC NC NC NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A7R A6R A5R IO 10L IO 11L IO 12L IO 13L GND IO 14L IO 15L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 R\WR GND SEMR CER UBR LBR NC[6] A11R A10R A9R A8R NC NC NC NC Notes 5. A12L on the CY7C025AV. 6. A12R on the CY7C025AV. Document Number: 38-06052 Rev. *R Page 4 of 24 CY7C024AV/025AV/026AV Pin Configurations (continued) IO IO IO IO IO IO G IO1L IO O IO0L OEL R G VCC SE R/WL C SEML U CEL UBL N LBL A A13L A A12L A11L A10L A9L A8L A7L IO9L IO8L IO7L IO6L IO5L IO4L IO3L IO2L GND IO IO Figure 2. 100-pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 2 74 3 73 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 14 62 61 15 60 16 59 17 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC NC IO10L IO11L IO12L IO13L GND IO14L IO15L VCC GND IO0R IO1R IO2R VCC IO3R IO4R IO5R IO6R NC NC NC NC A9R A8R A7R A6R UBR LBR A13R A12R A11R A10R IO15R OER R/WR GND SEMR CER IO13R IO14R GND IO7R IO8R IO9R IO10R IO11R IO12R CY7C026AV (16 K × 16) NC NC NC A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R NC NC NC Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read and Write Enable OEL OER Output Enable A0L–A13L A0R–A13R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K) IO0L–IO15L IO0R–IO15R Data Bus Input and Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (IO8–IO15 for × 16 devices) LBL LBR Lower Byte Select (IO0–IO7 for × 16 devices) INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Document Number: 38-06052 Rev. *R Page 5 of 24 CY7C024AV/025AV/026AV Functional Overview The CY7C024AV/025AV/026AV are low power CMOS 4 K, 8 K, and 16 K × 16 dual port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. There are two ports permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual port static RAMs or multiple devices can be combined to function as a 32-bit or wider master and slave dual port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications. It does not need separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual port video and graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic has eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C024AV/025AV/026AV are available in 100-pin Pb-free Thin Quad Flat Pack (TQFP) and 100-pin TQFP. Write Operation Data must be set up for a duration of tSD before the rising edge of RW to guarantee a valid write. A write operation is controlled by either the RW pin (see Figure 7 on page 14) or the CE pin (see Figure 8 on page 14). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port tries to read that location, there must be a port to port flowthrough delay before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Table 1. Non-Contending Read/Write Inputs Outputs IO8–IO15 Operation CE R/W OE UB LB SEM IO0–IO7 H X X X X H X X X H H L L X L H L L X H L L L X L L L H L L H H L H L H L H L H L L L H X X H X X X H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write DIN0 into Semaphore Flag X X H H L Data In Data In Write DIN0 into Semaphore Flag High Z High Z Deselected: Power Down H High Z High Z Deselected: Power Down H Data In High Z Write to Upper Byte Only H High Z Data In Write to Lower Byte Only H Data In Data In Write to Both Bytes Data Out High Z Read Upper Byte Only High Z Data Out Read Lower Byte Only Data Out Data Out Read Both Bytes High Z High Z Outputs Disabled L X X L X L Not Allowed L X X X L L Not Allowed Document Number: 38-06052 Rev. *R Page 6 of 24 CY7C024AV/025AV/026AV Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wants to access a semaphore flag, then the SEM pin and OE must be asserted. Interrupts The upper two memory locations are for message passing. The highest memory location (FFF for the CY7C024AV, 1FFF for the CY7C025AV, 3FFF for the CY7C026AV) is the mailbox for the right port and the second highest memory location (FFE for the CY7C024AV, 1FFE for the CY7C025AV, 3FFE for the CY7C026AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH) [7] Left Port Function R/WL CEL OEL Right Port A0L–13L [8] INTL R/WR CER OER A0R–13R INTR X X X X X L[9] Set Right INTR Flag L L X FFF Reset Right INTR Flag X X X X X X L L FFF (or 1/3FFF) H[10] Set Left INTL Flag X X X X L[10] L L X FFE (or 1/3FFE) X H[9] X X X X X Reset Left INTL Flag X L L FFE [8] Busy Master/Slave The CY7C024AV/025AV/026AV provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW. A M/S pin helps to expand the word width by configuring the device as a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This enables the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin enables the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Notes 7. See Functional Overview on page 6 for specific highest memory locations by device. 8. See Functional Overview on page 6 for specific addresses by device. 9. If BUSYL=L, then no change. 10. If BUSYR=L, then no change. Document Number: 38-06052 Rev. *R Page 7 of 24 CY7C024AV/025AV/026AV Semaphore Operation The CY7C024AV/025AV/026AV provide eight semaphore latches, which are separate from the dual port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource. Otherwise (reads a one), it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and RW are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only IO0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all 16 data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one of them. But there is no guarantee which side controls the semaphore. Table 3. Semaphore Operation Example IO0–IO15 Left IO0–IO15 Right No action Function 1 1 Semaphore-free Status Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Document Number: 38-06052 Rev. *R Page 8 of 24 CY7C024AV/025AV/026AV DC Input Voltage [12] ........................... –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings [11] may shorten the useful life of the device. User guidelines are not tested. Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ........................................ > 2001 V Storage Temperature ............................... –65 °C to +150 °C Latch-up Current ................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Operating Range Range Supply Voltage to Ground Potential .............–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State ...................... –0.5 V to VCC + 0.5 V Ambient Temperature VCC Commercial 0 °C to +70 °C 3.3 V 300 mV Industrial [13] –40 °C to +85 °C 3.3 V 300 mV Electrical Characteristics Over the Operating Range CY7C024AV/025AV/026AV Parameter Description -20 -25 Unit Min Typ Max Min Typ Max VOH Output HIGH Voltage (VCC = Min, IOH = –4.0 mA) 2.4 – – 2.4 – – V VOL Output LOW Voltage (VCC = Min, IOH = +4.0 mA) – – 0.4 – – 0.4 V VIH Input HIGH Voltage – – 2.0 – – V – 0.8 – 0.8 V – 10 –10 – 10 A 2.0 VIL Input LOW Voltage IOZ Output Leakage Current IIX Input Leakage Current ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Commercial Standby Current (Both Ports TTL Level) CEL & CER VIH, f = fMAX Commercial Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Commercial ISB1 ISB2 ISB3 ISB4 Standby Current (Both Ports CMOS Level) CEL & CER VCC 0.2 V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX [15] –0.3 [14] –10 –10 – 10 –10 – 10 A – 120 175 – 115 165 mA 135 185 mA 30 40 mA 40 50 mA 65 95 mA 75 105 mA 10 500 A 10 500 A 60 80 mA 70 90 mA Industrial [13] Industrial Industrial – 35 [13] – 75 [13] Commercial Industrial [13] 110 – 10 Industrial [13] Commercial 45 500 – 70 95 – Notes 11. The voltage on any input or IO pin cannot exceed the power pin during power up. 12. Pulse width < 20 ns. 13. Industrial parts are available in CY7C024AV, CY7C025AV & CY7C026AV. 14. VIL > –1.5V for pulse width less than 10ns. 15. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 38-06052 Rev. *R Page 9 of 24 CY7C024AV/025AV/026AV Capacitance Parameter [16] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max Unit 10 pF 10 pF AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms 3.3 V 3.3 V R1 = 590 OUTPUT OUTPUT C = 30 pF RTH = 250 R1 = 590 OUTPUT C = 30 pF R2 = 435 C = 5 pF R2 = 435 VTH = 1.4 V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0 V GND 10% 90% 10% 90% 3 ns 3 ns Data Retention Mode The CY7C024AV/025AV/026AV are designed for battery backup. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V. 2. CE must be kept between VCC – 0.2 V and 70 percent of VCC during the power up and power down transitions. 3. The RAM can begin operation > tRC after VCC reaches the minimum operating voltage (3.0 V). Timing Data Retention Mode VCC CE Parameter ICCDR1 3.0 V VCC 2.0 V 3.0 V VCC to VCC – 0.2 V Test Conditions [17] at VCCDR = 2 V tRC V IH Max Unit 50 A Notes 16. Tested initially and after any design or process changes that may affect these parameters. 17. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested. Document Number: 38-06052 Rev. *R Page 10 of 24 CY7C024AV/025AV/026AV Switching Characteristics Over the Operating Range CY7C024AV/025AV/026AV Parameter [18] Description -20 -25 Unit Min Max Min Max Read Cycle tRC Read Cycle Time 20 – 25 – ns tAA Address to Data Valid – 20 – 25 ns tOHA Output Hold From Address Change 3 – 3 – ns tACE[19] CE LOW to Data Valid – 20 – 25 ns tDOE OE LOW to Data Valid – 12 – 13 ns tLZOE[20, 21, 22] tHZOE[20, 21, 22] tLZCE[20, 21, 22] tHZCE[20, 21, 22] tPU[22] tPD[22] tABE[19] OE Low to Low Z 3 – 3 – ns OE HIGH to High Z – 12 – 15 ns CE LOW to Low Z 3 – 3 – ns CE HIGH to High Z – 12 – 15 ns CE LOW to Power Up 0 – 0 – ns CE HIGH to Power Down – 20 – 25 ns Byte Enable Access Time – 20 – 25 ns tWC Write Cycle Time 20 – 25 – ns tSCE[19] CE LOW to Write End 15 – 20 – ns tAW Address Valid to Write End 15 – 20 – ns tHA Address Hold From Write End 0 – 0 – ns tSA[19] Address Setup to Write Start 0 – 0 – ns tPWE Write Pulse Width 15 – 20 – ns tSD Data Setup to Write End 15 – 15 – ns tHD Data Hold from Write End 0 – 0 – ns tHZWE[21, 22] tLZWE[21, 22] tWDD[23] tDDD[23] R/W LOW to High Z – 12 – 15 ns R/W HIGH to Low Z 3 – 0 – ns Write Pulse to Data Delay – 45 – 50 ns Write Data Valid to Read Data Valid – 30 – 35 ns Write Cycle Notes 18. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 19. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tACE/tSCE time. 20. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 21. Test conditions used are Load 3. 22. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 16. 23. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 16. Document Number: 38-06052 Rev. *R Page 11 of 24 CY7C024AV/025AV/026AV Switching Characteristics (continued) Over the Operating Range CY7C024AV/025AV/026AV Parameter [18] Description -20 -25 Unit Min Max Min Max Busy Timing [24] tBLA BUSY LOW from Address Match – 20 – 20 ns tBHA BUSY HIGH from Address Mismatch – 20 – 20 ns tBLC BUSY LOW from CE LOW – 20 – 20 ns tBHC BUSY HIGH from CE HIGH – 17 – 17 ns tPS Port Setup for Priority 5 – 5 – ns tWB R/W HIGH after BUSY (Slave) 0 – 0 – ns tWH R/W HIGH after BUSY HIGH (Slave) 15 – 17 – ns tBDD[25] BUSY HIGH to Data Valid – 20 – 25 ns Interrupt Timing [24] tINS INT Set Time – 20 – 20 ns tINR INT Reset Time – 20 – 20 ns Semaphore Timing tSOP SEM Flag Update Pulse (OE or SEM) 10 – 12 – ns tSWRD SEM Flag Write to Read Time 5 – 5 – ns tSPS SEM Flag Contention Window 5 – 5 – ns tSAA SEM Address Access Time – 20 – 25 ns Notes 24. Test conditions used are Load 2. 25. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual). Document Number: 38-06052 Rev. *R Page 12 of 24 CY7C024AV/025AV/026AV Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) [26, 27, 28] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [26, 29, 30] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Figure 6. Read Cycle No. 3 (Either Port) [26, 28, 29, 30] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes 26. R/W is HIGH for read cycles. 27. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 28. OE = VIL. 29. Address valid prior to or coincident with CE transition LOW. 30. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document Number: 38-06052 Rev. *R Page 13 of 24 CY7C024AV/025AV/026AV Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [31, 32, 33, 34] tWC ADDRESS tHZOE [37] OE tAW CE [35, 36] tPWE[34] tSA tHA R/W tHZWE[37] DATA OUT tLZWE NOTE 38 NOTE 38 tSD tHD DATA IN Figure 8. Write Cycle No. 2 (CE Controlled Timing) [31, 32, 33, 39] tWC ADDRESS tAW CE [35, 36] tSA tSCE tHA R/W tSD tHD DATA IN Notes 31. R/W or CE must be HIGH during all address transitions. 32. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 33. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 34. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to enable the IO drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 35. To access RAM, CE = VIL, SEM = VIH. 36. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 37. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested. 38. During this period, the IO pins are in the output state, and input signals must not be applied. 39. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document Number: 38-06052 Rev. *R Page 14 of 24 CY7C024AV/025AV/026AV Switching Waveforms (continued) Figure 9. Semaphore Read after Write Timing, either side [40] tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD IO 0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 10. Timing Diagram of Semaphore Contention [41, 42, 43] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes 40. CE = HIGH for the duration of the above timing (both write and read cycle). 41. IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH. 42. Semaphores are reset (available to both ports) at cycle start. 43. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable. Document Number: 38-06052 Rev. *R Page 15 of 24 CY7C024AV/025AV/026AV Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [44] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Figure 12. Write Timing with Busy Input (M/S = LOW) tPWE R/W BUSY tWB tWH Note 44. CEL = CER = LOW. Document Number: 38-06052 Rev. *R Page 16 of 24 CY7C024AV/025AV/026AV Switching Waveforms (continued) Figure 13. Busy Timing Diagram No.1 (CE Arbitration) [45] CELValid First ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Figure 14. Busy Timing Diagram No.2 (Address Arbitration) [45] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note 45. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted. Document Number: 38-06052 Rev. *R Page 17 of 24 CY7C024AV/025AV/026AV Switching Waveforms (continued) Figure 15. Interrupt Timing Diagram Left Side Sets INTR : ADDRESSL tWC WRITE FFF (OR 1/3FFF) tHA[46] CE L R/W L INT R tINS [47] Right Side Clears INT R : tRC READ FFF (OR 1/3FFF) ADDRESSR CE R tINR [47] R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE FFE (OR 1/3FFE) tHA[46] CE R R/W R INT L [47] tINS Left Side Clears INT L: tRC READ FFE (OR 1/3FFE) ADDRESSR CE L tINR[47] R/W L OE L INT L Notes 46. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 47. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document Number: 38-06052 Rev. *R Page 18 of 24 CY7C024AV/025AV/026AV Ordering Information 4 K × 16 3.3 V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Package Diagram Ordering Code Package Type Operating Range CY7C024AV-20AXC 51-85048 100-pin TQFP (Pb-free) Commercial CY7C024AV-20AXI 51-85048 100-pin TQFP (Pb-free) Industrial CY7C024AV-25AXC 51-85048 100-pin TQFP (Pb-free) Commercial CY7C024AV-25AXI 51-85048 100-pin TQFP (Pb-free) Industrial 8 K × 16 3.3 V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Package Diagram Ordering Code CY7C025AV-20AXC Package Type 51-85048 100-pin TQFP (Pb-free) Operating Range Commercial CY7C025AV-25AXC 51-85048 100-pin TQFP (Pb-free) Commercial CY7C025AV-25AXI 51-85048 100-pin TQFP (Pb-free) Industrial 16 K × 16 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Package Diagram Ordering Code Package Type 20 CY7C026AV-20AXC 51-85048 100-pin TQFP (Pb-free) 25 CY7C026AV-25AXC 51-85048 100-pin TQFP (Pb-free) CY7C026AV-25AI 51-85048 100-pin TQFP CY7C026AV-25AXI 51-85048 100-pin TQFP (Pb-free) Operating Range Commercial Industrial Ordering Code Definitions CY 7 C 02 X AV - XX X X X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: A = 100-pin TQFP Speed Grade: XX = 20 ns or 25 ns AV = 3.3 V Depth: X = 4 or 5 or 6 4 = 4K; 5 = 8K; 6 = 16K Width: 02 = × 16 Technology Code: C = CMOS Marketing Code: 7 = Dual Port SRAM Company ID: CY = Cypress Document Number: 38-06052 Rev. *R Page 19 of 24 CY7C024AV/025AV/026AV Package Diagram Figure 16. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048 51-85048 *I Document Number: 38-06052 Rev. *R Page 20 of 24 CY7C024AV/025AV/026AV Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere TQFP Thin Quad Flat Pack mm millimeter TTL Transistor-Transistor Logic mV millivolt ns nanosecond Document Number: 38-06052 Rev. *R Symbol Unit of Measure ohm % percent pF picofarad V volt Page 21 of 24 CY7C024AV/025AV/026AV Document History Page Document Title: CY7C024AV/025AV/026AV, 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM Document Number: 38-06052 Rev. ECN No. Orig. of Change Submission Date ** 110204 SZV 11/11/01 Change from Spec number: 38-00838 to 38-06052. *A 122302 RBI 12/27/02 Updated Maximum Ratings: Added Note 11 and referred the same note in maximum ratings. *B 128958 JFU 9/03/03 Updated Ordering Information: Added CY7C025AV-25AI. *C 237622 YDT See ECN Updated Features: Removed “Pin-compatible and functionally equivalent to IDT70V24, 70V25, and 7V0261”. *D 241968 WWZ See ECN Updated Ordering Information: Added CY7C024AV-25AI. *E 276451 SPN See ECN Updated Ordering Information: Updated 16 K × 16 3.3 V Asynchronous Dual-Port SRAM: Replaced “× 18” with “× 16” in heading (for 026AV part numbers). *F 279452 RUY See ECN Updated Pin Configurations: Updated Figure 2: Replaced A113L with A13L (for CY7C026AV pin list). Description of Change Updated Electrical Characteristics: Added minimum value of VIL parameter (0.3 V) Added Note 14 and referred the same note in minimum value of VIL parameter. Updated Ordering Information: Added Pb-free part numbers. *G 373580 RUY See ECN Updated Ordering Information: Replaced CY7C024AC-25AXC with CY7C024AV-25AXC. *H 380476 PCX See ECN Updated Ordering Information: Added CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI, CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI. *I 2543577 NXR / AESA 07/25/08 Updated Switching Waveforms: Updated Note 31 (Replaced “R/W must be HIGH during all address transitions” with “R/W or CE must be HIGH during all address transitions”). *J 2623540 VKN / PYRS 12/17/08 Added CY7C024BV part related information in all instances across the document. *K 2896038 RAME 03/19/10 Updated Ordering Information (Removed inactive parts). Updated Package Diagram. *L 3110406 ADMU 12/14/2010 Added Ordering Code Definitions. *M 3210221 ADMU 03/30/2011 Updated Package Diagram (spec 51-85048 (Changed revision from *D to *E)). Updated Ordering Information (Removed part CY7C025AV-25AC from Ordering Information table). Document Number: 38-06052 Rev. *R Page 22 of 24 CY7C024AV/025AV/026AV Document History Page (continued) Document Title: CY7C024AV/025AV/026AV, 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM Document Number: 38-06052 Rev. ECN No. Orig. of Change Submission Date Description of Change *N 3343888 ADMU 08/12/2011 Updated Document Title to read as “CY7C024AV/025AV/026AV, 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM”. Updated Features (Removed CY7C0241/251 and CY7C036 information). Updated Functional Description (Removed CY7C0241/251 and CY7C036 information). Updated Selection Guide (Removed CY7C0241/251 and CY7C036 information). Updated Pin Configurations (Removed CY7C0241/251 and CY7C036 information). Updated Pin Definitions. Updated Functional Overview (Removed CY7C0241/251 and CY7C036 information). Updated Electrical Characteristics (Removed CY7C0241/251 and CY7C036 information). Updated Switching Characteristics (Removed CY7C0241/251 and CY7C036 information). Added Acronyms and Units of Measure. Updated in new template. *O 3403638 ADMU 10/13/2011 Updated Ordering Information (Removed pruned part CY7C024BV-15AXI). *P 3698952 SMCH 07/31/2012 Updated Title to read as “CY7C024AV/025AV/026AV, 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM”. Updated Features (Removed CY7C024BV related information, removed 15 ns from the High speed access, removed the Note “CY7C024AV and CY7C024BV are functionally identical.” and its reference). Updated Functional Description (Removed CY7C024BV related information). Updated Selection Guide (Removed CY7C024BV related information). Updated Pin Configurations (Removed CY7C024BV related information). Updated Functional Overview (Removed CY7C024BV related information). Updated Electrical Characteristics (Removed CY7C024BV related information). Updated Switching Characteristics (Removed CY7C024BV related information). Updated Data Retention Mode (Removed CY7C024BV related information). Updated Ordering Information (Removed pruned part CY7C026AV-20AXC). Updated Package Diagram (spec 51-85048 (Changed revision from *E to *G)). *Q 4112664 SMCH 09/03/2013 Updated Ordering Information (Updated part numbers). Updated Package Diagram: spec 51-85048 – Changed revision from *G to *H. Updated to new template. Completing Sunset Review. *R 4592640 VINI 12/11/2014 Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Package Diagram: spec 51-85048 – Changed revision from *H to *I. Document Number: 38-06052 Rev. *R Page 23 of 24 CY7C024AV/025AV/026AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06052 Rev. *R Revised December 11, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 24 of 24