The following document contains information on Cypress products. MB9A420L Series ® 32-bit ARM Cortex®-M3 based Microcontroller MB9AF421K/L Data Sheet (Full Production) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number MB9A420L_DS706-00054 CONFIDENTIAL Revision 2.0 Issue Date March 31, 2015 D a t a S h e e t Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. 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MB9A420L_DS706-00054-2v0-E, March 31, 2015 CONFIDENTIAL MB9A420L Series 32-bit ARM® Cortex®-M3 based Microcontroller MB9AF421K/L Data Sheet (Full Production) Description The MB9A420L Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (CAN, UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE11 product categories in FM3 Family Peripheral Manual. Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. Publication Number MB9A420L_DS706-00054 Revision 2.0 Issue Date March 31, 2015 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. CONFIDENTIAL D a t a S h e e t Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 40 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] 64 Kbytes Read cycle: 0 wait-cycle Security function for code protection [SRAM] This series contains 4 Kbyte on-chip SRAM memories that is connected to System bus of Cortex-M3 core. SRAM1: 4 Kbyte CAN Interface (Max one channel) Compatible with CAN Specification 2.0A/B Maximum transfer rate: 1 Mbps Built-in 32 message buffer Multi-function Serial Interface (Max four channels) 4 channels without FIFO (ch.0, ch.1, ch.3, ch.5) Operation mode is selectable from the followings for each channel. UART CSIO LIN I 2C [UART] Full duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [LIN] LIN protocol Rev.2.1 supported Full duplex double buffer Master/Slave mode supported LIN break field generation (can be changed to 13-bit to 16-bit length) LIN break delimiter generation (can be changed to 1-bit to 4-bit length) Various error detection functions available (parity errors, framing errors, and overrun errors) 2 [I C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported 2 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t A/D Converter (Max eight channels) [12-bit A/D Converter] Successive Approximation type Conversion time: 0.8 μs @ 5 V Priority conversion available (priority at 2 levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) D/A Converter (Max one channel) R-2R type 10-bit resolution Base Timer (Max eight channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built-in. It can set which I/O port the peripheral function can be allocated to. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 51 high-speed general-purpose I/O Ports@64 pin Package Some ports are 5V tolerant See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. Free-running Periodic (=Reload) One-shot March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 3 D a t a S h e e t Multi-function Timer The Multi-function timer is composed of the following blocks. 16-bit free-run timer × 3ch. Input capture × 3ch. Output compare × 6ch. A/D activation compare × 1ch. Waveform generator × 3ch. 16-bit PPG timer × 3ch. IGBT mode is contained The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99. The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. External Interrupt Controller Unit Up to 19 external interrupt input pins @ 64 pin Package Include one non-maskable interrupt (NMI) input pin Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. The Hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption modes except RTC, Stop modes. Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL). Main Clock: Sub Clock: Built-in high-speed CR Clock: Built-in low-speed CR Clock: Main PLL Clock 4 MHz to 48 MHz 32.768 kHz 4 MHz 100 kHz [Resets] Reset requests from INITX pin Power-on reset Software reset Watchdog timers reset Low-voltage detection reset Clock Super Visor reset 4 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. If external clock failure (clock stop) is detected, reset is asserted. If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-Power Consumption Mode Four low-power consumption modes supported. Sleep Timer RTC Stop Debug Serial Wire JTAG Debug Port (SWJ-DP) Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage: VCC = 2.7 V to 5.5 V March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 5 D a t a S h e e t Product Lineup Memory size Product name MB9AF421K/L On-chip Flash memory 64 Kbytes On-chip SRAM 4 Kbytes SRAM1 Function Product name Pin count CPU Freq. Power supply voltage range CAN Multi-function Serial Interface (UART/CSIO/LIN/I2C) MB9AF421K MB9AF421L 48/52 64 Cortex-M3 40 MHz 2.7 V to 5.5 V 1ch. (Max) 4ch. (Max) ch.0, ch.1, ch.3, ch.5: No FIFO (In ch.5, only UART and LIN are available.) 4ch. (Max) ch.0, ch.1, ch.3, ch.5: No FIFO Base Timer 8ch. (Max) (PWC/Reload timer/PWM/PPG) A/D activation 1ch. compare Input capture 3ch. Free-run timer 3ch. MF1 unit Output compare 6ch. Timer Waveform 3ch. generator PPG 3ch. (IGBT mode) Dual Timer 1 unit Real-Time Clock 1 unit Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 14 pins (Max) + NMI × 1 19 pins (Max) + NMI × 1 I/O ports 36 pins (Max) 51 pins (Max) 12-bit A/D converter 8ch. (1 unit) 10-bit D/A converter 1ch. (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. High-speed 4 MHz Built-in CR Low-speed 100 kHz Debug Function SWJ-DP Unique ID Yes Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for accuracy of built-in CR. 6 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Packages Product name Package LQFP: FPT-48P-M49 (0.5 mm pitch) QFN: LCC-48P-M74 (0.5 mm pitch) LQFP: FPT-52P-M02 (0.65 mm pitch) LQFP: FPT-64P-M38 (0.5 mm pitch) LQFP: FPT-64P-M39 (0.65 mm pitch) QFN: LCC-64P-M25 (0.5 mm pitch) MB9AF421K - MB9AF421L : Supported Note: See Package Dimensions for detailed information on each package. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 7 D a t a S h e e t Pin Assignment ・FPT-64P-M38/M39 P0C/TIOA6_1/INT19_0 P0A/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 54 53 52 51 50 49 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 57 P0B/TIOB6_1/INT18_0 P62/SCK5_0/ADTG_3 58 55 P61/SOT5_0/TIOB2_2/DTTI0X_2 59 56 P80/INT16_1 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 P81/INT17_1 62 60 P82 63 61 VSS 64 (TOP VIEW) VCC 1 48 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 47 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 46 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 45 P19 P30/TIOB0_1/INT03_2 5 44 P18 P31/TIOB1_1/INT04_2 6 43 AVRL P32/TIOB2_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/INT06_0/ADTG_2 9 40 P17/INT04_1 P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10 39 P15/AN05/SOT0_1/INT14_0/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/SIN0_1/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1/INT18_2 12 37 AVSS P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/TX1_2/IC00_2 P3E/RTO04_0/TIOA4_1/INT19_2 14 35 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00/SCK1_1 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SOT3_2/INT20_1/DA0_0 P4A/TIOB1_0/SCK3_2/INT21_1 P4B/TIOB2_0/INT22_1/IGTRG_0 P4C/TIOB3_0/INT12_0 P4D/TIOB4_0/INT13_0 P4E/TIOB5_0/INT06_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP- 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 8 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t ・LCC-64P-M25 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 52 51 50 49 57 P0A/INT00_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 58 53 P62/SCK5_0/ADTG_3 59 54 P61/SOT5_0/TIOB2_2/DTTI0X_2 60 P0C/TIOA6_1/INT19_0 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 61 P0B/TIOB6_1/INT18_0 P80/INT16_1 62 55 P81/INT17_1 63 56 VSS P82 64 (TOP VIEW) VCC 1 48 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 47 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 46 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 45 P19 P30/TIOB0_1/INT03_2 5 44 P18 P31/TIOB1_1/INT04_2 6 43 AVRL P32/TIOB2_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/INT06_0/ADTG_2 9 40 P17/INT04_1 P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10 39 P15/AN05/SOT0_1/INT14_0/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/SIN0_1/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1/INT18_2 12 37 AVSS P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/TX1_2/IC00_2 P3E/RTO04_0/TIOA4_1/INT19_2 14 35 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00/SCK1_1 VSS 16 33 VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SOT3_2/INT20_1/DA0_0 P4A/TIOB1_0/SCK3_2/INT21_1 P4B/TIOB2_0/INT22_1/IGTRG_0 P4C/TIOB3_0/INT12_0 P4D/TIOB4_0/INT13_0 P4E/TIOB5_0/INT06_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN- 64 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 9 D a t a S h e e t ・FPT-48P-M49 P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX 40 39 38 37 P61/SOT5_0/TIOB2_2/DTTI0X_2 43 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 44 P04/TDO/SWO P80/INT16_1 45 41 P81/INT17_1 46 42 VSS P82 47 1 36 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 35 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 34 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 33 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 10 27 P12/AN02/SOT1_1/TX1_2/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2 VSS 12 25 P10/AN00/SCK1_1 24 20 PE0/MD1 VSS 19 P4A/TIOB1_0/INT21_1 23 18 P49/TIOB0_0/INT20_1/DA0_0 PE3/X1 17 INITX 22 16 P47/X1A 21 15 P46/X0A MD0 14 PE2/X0 13 C LQFP- 48 VCC VCC 48 (TOP VIEW) <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 10 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t ・LCC-48P-M74 P02/TDI P00/TRSTX 37 P03/TMS/SWDIO 40 P01/TCK/SWCLK P04/TDO/SWO 41 38 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 42 39 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 P80/INT16_1 45 P61/SOT5_0/TIOB2_2/DTTI0X_2 P81/INT17_1 46 43 P82 47 44 VSS 48 (TOP VIEW) VCC 1 36 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 35 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 34 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 33 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 10 27 P12/AN02/SOT1_1/TX1_2/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2 VSS 12 25 P10/AN00/SCK1_1 13 14 15 16 17 18 19 20 21 22 23 24 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/INT20_1/DA0_0 P4A/TIOB1_0/INT21_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN- 48 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 11 D a t a S h e e t ・FPT-52P-M02 P80/INT16_1 P60/SIN5_0/TIOA2_2/INT15_1/IGTRG_1 P61/SOT5_0/TIOB2_2/DTTI0X_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX NC 47 46 45 44 43 42 41 40 P81/INT17_1 50 48 P82 51 49 VSS 52 (TOP VIEW) VCC 1 39 P21/AN14/SIN0_0/INT06_1 P50/INT00_0/SIN3_1 2 38 P22/AN13/SOT0_0/TIOB7_1 P51/INT01_0/SOT3_1 3 37 P23/AN12/SCK0_0/TIOA7_1 P52/INT02_0/SCK3_1 4 36 NC NC 5 35 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 6 34 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 7 33 AVCC P3B/RTO01_0/TIOA1_1 8 32 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 9 31 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 10 30 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 11 29 P12/AN02/SOT1_1/TX1_2/IC00_2 P3F/RTO05_0/TIOA5_1 12 28 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2 VSS 13 27 P10/AN00/SCK1_1 14 15 16 17 18 19 20 21 22 23 24 25 26 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/INT20_1/DA0_0 P4A/TIOB1_0/INT21_1 NC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP- 52 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 12 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-64 QFN-64 LQFP-52 LQFP-48 QFN-48 Pin Name 1 1 1 2 2 2 3 3 3 4 4 4 5 - - 6 - - 7 - - 8 - - 9 6 5 10 7 6 11 8 7 VCC P50 INT00_0 SIN3_1 P51 INT01_0 SOT3_1 (SDA3_1) P52 INT02_0 SCK3_1 (SCL3_1) P30 TIOB0_1 INT03_2 P31 TIOB1_1 INT04_2 P32 TIOB2_1 INT05_2 P33 INT04_0 TIOB3_1 ADTG_6 P39 DTTI0X_0 INT06_0 ADTG_2 P3A RTO00_0 (PPG00_0) TIOA0_1 INT07_0 SUBOUT_2 RTCCO_2 P3B RTO01_0 (PPG00_0) TIOA1_1 March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL I/O circuit type Pin state type - H*1 K H*2 K H*2 K E K E K E K E K E K G K G J 13 D a t a S h e e t Pin No LQFP-64 QFN-64 LQFP-52 LQFP-48 QFN-48 12 9 8 13 10 9 14 11 10 15 12 11 16 17 18 13 14 15 12 13 14 19 16 15 20 17 16 21 18 17 19 18 22 - - 20 19 23 - - 24 - - 25 - - 26 - - 14 CONFIDENTIAL Pin Name P3C RTO02_0 (PPG02_0) TIOA2_1 INT18_2 P3D RTO03_0 (PPG02_0) TIOA3_1 P3E RTO04_0 (PPG04_0) TIOA4_1 INT19_2 P3F RTO05_0 (PPG04_0) TIOA5_1 VSS C VCC P46 X0A P47 X1A INITX P49 TIOB0_0 INT20_1 DA0_0 SOT3_2 (SDA3_2) P4A TIOB1_0 INT21_1 SCK3_2 (SCL3_2) P4B TIOB2_0 INT22_1 IGTRG_0 P4C TIOB3_0 INT12_0 P4D TIOB4_0 INT13_0 I/O circuit type Pin state type G K G J G K G J - D F D G B C K K E K E K E K E K MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Pin No LQFP-64 QFN-64 LQFP-52 LQFP-48 QFN-48 27 - - 28 22 20 29 23 21 30 24 22 31 25 23 32 33 26 - 24 - 34 27 25 35 28 26 36 29 27 37 30 28 38 31 29 39 32 30 40 - - 41 42 43 44 45 33 34 35 - 31 32 33 - March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Pin Name P4E TIOB5_0 INT06_2 PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 AN00 SCK1_1 (SCL1_1) P11 AN01 SIN1_1 INT02_1 RX1_2 FRCK0_2 P12 AN02 SOT1_1 (SDA1_1) TX1_2 IC00_2 AVSS P14 AN04 SIN0_1 INT03_1 IC02_2 P15 AN05 SOT0_1 (SDA0_1) INT14_0 IC03_2 P17 INT04_1 AVCC AVRH AVRL P18 P19 I/O circuit type Pin state type E K C E J D A A A B - F L F M F L - F M F M E K - E E J J 15 D a t a S h e e t Pin No LQFP-64 QFN-64 LQFP-52 LQFP-48 QFN-48 46 37 34 47 38 35 48 39 36 49 41 37 50 42 38 51 43 39 52 44 40 53 45 41 54 - - 55 - - 56 - - 57 46 42 58 - - 16 CONFIDENTIAL Pin Name P23 AN12 SCK0_0 (SCL0_0) TIOA7_1 P22 AN13 SOT0_0 (SDA0_0) TIOB7_1 P21 AN14 SIN0_0 INT06_1 P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P0A INT00_2 P0B TIOB6_1 INT18_0 P0C TIOA6_1 INT19_0 P0F NMIX SUBOUT_0 CROUT_1 RTCCO_0 P62 SCK5_0 (SCL5_0) ADTG_3 I/O circuit type Pin state type I*2 M I*2 M I*1 M E I E I E I E I E I E K E K E K E H E J MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Pin No LQFP-64 QFN-64 LQFP-52 LQFP-48 QFN-48 59 47 43 60 48 44 61 49 45 62 50 46 63 51 64 52 5, 21, 36, 40 *1: 5 V tolerant I/O, without PZR function *2: 5 V tolerant I/O, with PZR function March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 47 48 - Pin Name P61 SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 P60 SIN5_0 TIOA2_2 INT15_1 IGTRG_1 P80 INT16_1 P81 INT17_1 P82 VSS NC I/O circuit type Pin state type E J I*2 K L K L K L J - 17 D a t a S h e e t List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Debugger Pin name ADTG_2 ADTG_3 ADTG_6 AN00 AN01 AN02 AN04 AN05 AN12 AN13 AN14 TIOA0_1 TIOB0_0 TIOB0_1 TIOA1_1 TIOB1_0 TIOB1_1 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_1 TIOB3_0 TIOB3_1 TIOA4_1 TIOB4_0 TIOA5_1 TIOB5_0 TIOA6_1 TIOB6_1 TIOA7_1 TIOB7_1 SWCLK SWDIO SWO TCK TDI TDO TMS TRSTX 18 CONFIDENTIAL Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin J-TAG test clock input pin J-TAG test data input pin J-TAG debug data output pin J-TAG test mode state input/output pin J-TAG test reset input pin Pin No LQFP-64 LQFP-48 LQFP-52 QFN-64 QFN-48 9 6 5 58 8 34 27 25 35 28 26 36 29 27 38 31 29 39 32 30 46 37 34 47 38 35 48 39 36 10 7 6 22 19 18 5 11 8 7 23 20 19 6 12 9 8 60 48 44 24 7 59 47 43 13 10 9 25 8 14 11 10 26 15 12 11 27 56 55 46 37 34 47 38 35 50 42 38 52 44 40 53 50 51 53 52 49 45 42 43 45 44 41 41 38 39 41 40 37 MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Pin function External Interrupt Pin name INT00_0 INT00_2 INT01_0 INT02_0 INT02_1 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_2 INT06_0 INT06_1 INT06_2 INT07_0 INT12_0 INT13_0 INT14_0 INT15_1 INT16_1 INT17_1 INT18_0 INT18_2 INT19_0 INT19_2 INT20_1 INT21_1 INT22_1 NMIX Function description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin External interrupt request 16 input pin External interrupt request 17 input pin External interrupt request 18 input pin External interrupt request 19 input pin External interrupt request 20 input pin External interrupt request 21 input pin External interrupt request 22 input pin Non-Maskable Interrupt input pin March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Pin No LQFP-64 LQFP-48 LQFP-52 QFN-64 QFN-48 2 2 2 54 3 3 3 4 4 4 35 28 26 38 31 29 5 8 40 6 7 9 6 5 48 39 36 27 10 7 6 25 26 39 32 30 60 48 44 61 49 45 62 50 46 55 12 9 8 56 14 11 10 22 19 18 23 20 19 24 57 46 42 19 D a t a S h e e t Pin function GPIO 20 CONFIDENTIAL Pin name P00 P01 P02 P03 P04 P0A P0B P0C P0F P10 P11 P12 P14 P15 P17 P18 P19 P21 P22 P23 P30 P31 P32 P33 P39 P3A P3B P3C P3D P3E P3F P46 P47 P49 P4A P4B P4C P4D P4E P50 P51 P52 P60 P61 P62 P80 P81 P82 PE0 PE2 PE3 Function description General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Pin No LQFP-64 LQFP-48 LQFP-52 QFN-64 QFN-48 49 41 37 50 42 38 51 43 39 52 44 40 53 45 41 54 55 56 57 46 42 34 27 25 35 28 26 36 29 27 38 31 29 39 32 30 40 44 45 48 39 36 47 38 35 46 37 34 5 6 7 8 9 6 5 10 7 6 11 8 7 12 9 8 13 10 9 14 11 10 15 12 11 19 16 15 20 17 16 22 19 18 23 20 19 24 25 26 27 2 2 2 3 3 3 4 4 4 60 48 44 59 47 43 58 61 49 45 62 50 46 63 51 47 28 22 20 30 24 22 31 25 23 MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Pin function Multifunction Serial 0 Pin name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Multifunction Serial 1 SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) Multifunction Serial 3 SIN3_1 SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Function description Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation mode 2) and as SCL3 when it is used in an I2C (operation mode 4). March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Pin No LQFP-64 LQFP-48 LQFP-52 QFN-64 QFN-48 48 39 36 38 31 29 47 38 35 39 32 30 46 37 34 35 28 26 36 29 27 34 27 25 2 2 2 3 3 3 22 - - 4 4 4 23 - - 21 D a t a S h e e t Pin function Multifunction Serial 5 Pin name Function description SIN5_0 Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 16-bit input capture input pin of Multi-function timer 0. ICxx describes channel number. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. SOT5_0 (SDA5_0) SCK5_0 (SCL5_0) Multifunction Timer 0 DTTI0X_0 DTTI0X_2 FRCK0_2 IC00_2 IC02_2 IC03_2 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) IGTRG_0 IGTRG_1 22 CONFIDENTIAL PPG IGBT mode external trigger input pin Pin No LQFP-64 LQFP-48 LQFP-52 QFN-64 QFN-48 60 48 44 59 47 43 58 - - 9 6 5 59 47 43 35 28 26 36 38 39 29 31 32 27 29 30 10 7 6 11 8 7 12 9 8 13 10 9 14 11 10 15 12 11 24 60 48 44 MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Pin function CAN Real-time clock DAC RESET Pin name TX1_2 RX1_2 RTCCO_0 RTCCO_2 SUBOUT_0 SUBOUT_2 DA0_0 INITX Mode MD0 MD1 Function description CAN interface TX output pin CAN interface RX input pin 0.5 seconds pulse output pin of Real-time clock Sub clock output pin D/A converter ch.0 analog output pin External Reset Input pin. A reset is valid when INITX="L". Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Power VCC Power supply Pin VSS GND Pin GND Clock Analog Power Analog GND C pin X0 X0A X1 X1A CROUT_1 AVCC AVRH AVSS AVRL C Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin A/D converter and D/A converter GND pin A/D converter analog reference voltage input pin Power supply stabilization capacity pin March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Pin No LQFP-64 LQFP-48 LQFP-52 QFN-64 QFN-48 36 29 27 35 28 26 57 46 42 10 7 6 57 46 42 10 7 6 22 19 18 21 18 17 29 23 21 28 22 20 1 18 33 16 32 64 30 19 31 20 57 1 15 13 26 52 24 16 25 17 46 1 14 12 24 48 22 15 23 16 42 41 33 31 42 37 43 17 34 30 35 14 32 28 33 13 23 D a t a S h e e t I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. Oscillation feedback resistor : Approximately 1 MΩ With Standby mode control Pull-up resistor P-ch P-ch Digital output X1A N-ch Digital output R Pull-up resistor control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -4 mA, IOL= 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control CMOS level hysteresis input Pull-up resistor : Approximately 50 kΩ B Pull-up resistor Digital input 24 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Type Circuit Remarks C Digital input Open drain output CMOS level hysteresis input Digital output N-ch D It is possible to select the sub oscillation / GPIO function Pull-up resistor P-ch P-ch Digital output X1A N-ch Digital output R Pull-up resistor control Digital input When the sub oscillation is selected. Oscillation feedback resistor : Approximately 5 MΩ With Standby mode control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -4 mA, IOL= 4 mA Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 25 D a t a S h e e t Type Circuit Remarks E P-ch P-ch N-ch CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off +B input is available Digital output Digital output R Pull-up resistor control Digital input Standby mode control F P-ch P-ch N-ch R CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -4 mA, IOL= 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off +B input is available Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control 26 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Type Circuit Remarks G P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -12 mA, IOL= 12 mA +B input is available Digital output R Pull-up resistor control Digital input Standby mode control H P-ch P-ch N-ch Digital output Digital output R CMOS level output CMOS level hysteresis input 5 V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -4 mA, IOL= 4 mA Available to control PZR registers. Only P51, P52. When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 27 D a t a S h e e t Type Circuit Remarks I P-ch P-ch N-ch R CMOS level output CMOS level hysteresis input With input control Analog input 5 V tolerant Digital output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH= -4 mA, IOL= 4 mA Available to control PZR Digital output registers. Only P23, P22, P60. When this pin is used as an I2C pin, the digital output Pull-up resistor control P-ch transistor is always off Digital input Standby mode control Analog input Input control J CMOS level hysteresis input Mode input K P-ch P-ch N-ch R CMOS level output CMOS level hysteresis input With input control Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ IOH = -4 mA, IOL = 4 mA When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog output 28 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Type Circuit Remarks L P-ch N-ch CMOS level output CMOS level hysteresis input With standby mode control IOH= -4 mA, IOL= 4 mA Digital output Digital output R Digital input Standby mode control March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 29 D a t a S h e e t Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS00-00004-3E 30 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended conditions. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 31 D a t a S h e e t Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 32 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Spansion products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 33 D a t a S h e e t Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin, between AVRH pin and AVRL pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ・ Surface mount type Size : More than 3.2 mm × 1.5 mm Load capacitance : Approximately 6 pF to 7 pF ・ Lead type Load capacitance : Approximately 6 pF to 7 pF 34 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. • Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. Set as External clock input X1(PE3), X1A (P47) Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. C Device CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 35 D a t a S h e e t Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC → AVCC → AVRH Turning off : AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. 36 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Block Diagram MB9AF421K/L TRSTX,TCK, TDI,TMS TDO SWJ-DP ROM Table I Multi-layer AHB (Max 40MHz) Cortex-M3 Core @40MHz (Max) D NVIC Sys AHB-APB Bridge : APB0(Max 40MHz) Dual-Timer WatchDog Timer ( Software) INITX Clock Reset Generator WatchDog Timer ( Hardware ) SRAM1 4 Kbytes Flash I/F Security On- Chip Flash 64 Kbytes CSV CLK X0A X1A CROUT AVCC, AVSS, AVRH, AVRL ANxx Main Osc Sub Osc Source clock PLL CR 4 MHz CR 100kHz AHB- AHB Bridge X0 X1 12- bit A /D Converter CAN TX1_2 , RX1_2 Unit 0 ADTG_x T IOBx Base Timer 16 -bit 8ch./ 32 -bit 4ch. A /D Activation Compare 1ch. IC0x 16 - bit Input Capture 3ch. FRCKx 16- bit Free-run Timer 3ch. 16 - bit Output Compare 6ch. DTTI0X RTO0x IGTRG_x LVD Ctrl AHB-APB Bridge : APB2 (Max 40MHz) TIOAx CAN Prescaler 10-bit D/A Converter 1 units AHB-APB Bridge : APB1 (Max 40MHz) DAx LVD Regulator C IRQ - Monitor Real -Time Colck RTCCO_x, SUBOUT_ x External Interrupt Controller 19 pin + NMI INTx NMIX MD0, MD1 P0x, P1x, MODE-Ctrl GPIO Waveform Generator 3ch. 16- bit PPG 3ch. Power-On Reset PIN- Function-Ctrl ・ ・ ・ Pxx Multi - function Serial I /F 4ch. ( without FIFO ch.0/1/3/5) SCKx SINx SOTx Multi -function Timer Memory Size See Memory size in Product Lineup to confirm the memory size. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 37 D a t a S h e e t Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved 0x6000_0000 Reserved 0x4400_0000 0x4200_0000 0x4000_0000 0x2400_0000 0x2200_0000 0x2008_0000 0x2000_0000 0x1FF8_0000 See " Memory Map (2)" for the memory size details. 0x0020_8000 0x0020_0000 0x0010_0008 0x0010_0000 32Mbytes Bit band alias Peripherals Reserved 32Mbytes Bit band alias Reserved SRAM1 Reserved Reserved Reserved Reserved Security/CR Trim 0x4006_4000 0x4006_3000 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 0x4003_C000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_7000 0x4003_6000 0x4003_5800 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4002_9000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4001_6000 0x4001_5000 0x0000_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 38 CONFIDENTIAL Reserved Reserved Reserved Reserved Reserved RTC Reserved Reserved MFS CAN Prescaler Reserved Reserved LVD Reserved GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved D/AC A/DC Reserved Base Timer PPG Reserved 0x4002_1000 0x4002_0000 Flash CAN ch.1 MFT unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Memory Map (2) MB9AF421L 0x2008_0000 Reserved 0x2000_1000 0x2000_0000 SRAM1 4Kbytes Reserved 0x0010_0008 0x0010_0004 0x0010_0000 CR trimming Security Reserved 0x0000_FFF8 SA0-7 (8KBx8) Flash 64Kbytes * 0x0000_0000 *: See MB9A420L/120L/MB9B120J Series Flash Programming Manual to confirm the detail of Flash memory. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 39 D a t a S h e e t Peripheral Address Map Start address End address Bus 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF AHB APB0 Peripherals Flash Memory I/F register Reserved Software Watchdog timer Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Resister 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF 0x4006_1000 0x4006_2FFF 0x4006_3000 0x4006_3FFF CAN ch.1 0x4006_4000 0x41FF_FFFF Reserved 40 CONFIDENTIAL APB1 APB2 AHB Reserved A/D Converter Reserved Reserved Reserved Reserved MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX=0 This is the period when the INITX pin is the L level. INITX=1 This is the period when the INITX pin is the H level. SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. Input enabled Indicates that the input function can be used. Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is enabled Indicates that the analog input is enabled. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 41 D a t a S h e e t Pin status type List of Pin Status Power-on reset or low-voltage detection state Device internal Run mode or reset state Sleep mode state Timer mode, RTC mode, or Stop mode state Function group Power supply unstable GPIO selected A INITX input state Main crystal oscillator input pin/ External main clock input selected Power supply stable INITX = 0 - INITX = 1 - Setting disabled Setting disabled Setting disabled Input enabled Input enabled Input enabled Power supply stable INITX = 1 - Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 B Main crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal input fixed at 0 Maintain previous Maintain previous Maintain previous state / When state / When state / When Hi-Z / Internal oscillation stops*1, oscillation stops*1, oscillation stops*1, input fixed at 0 Hi-Z / Hi-Z / Hi-Z / Internal input fixed Internal input fixed Internal input fixed at 0 at 0 at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E GPIO selected 42 CONFIDENTIAL Setting disabled Setting disabled Setting disabled Maintain previous Maintain previous state state Hi-Z / Input enabled MB9A420L_DS706-00054-2v0-E, March 31, 2015 Pin status type D a t a S h e e t Power-on reset or low-voltage detection state INITX input state Device internal Run mode or reset state Sleep mode state Timer mode, RTC mode, or Stop mode state Function group Power supply unstable - GPIO selected Power supply stable INITX = 0 - INITX = 1 - Setting disabled Setting disabled Setting disabled Power supply stable INITX = 1 - Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 F Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 G H Maintain previous Maintain previous state / When state / When Hi-Z / Internal Maintain previous oscillation stops*2, oscillation stops*2, input fixed at 0 state Hi-Z / Internal input Hi-Z / Internal input fixed at 0 fixed at 0 Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable NMIX selected Setting disabled Setting disabled Setting disabled Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Pull-up / Input enabled Pull-up / Input enabled GPIO selected JTAG selected Hi-Z / Internal input fixed at 0 Maintain previous Maintain previous state state Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous Maintain previous state state I GPIO selected Setting disabled Setting disabled Setting disabled March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Maintain previous state Hi-Z / Internal input fixed at 0 43 Pin status type D a t a S h e e t Power-on reset or low-voltage detection state Power supply unstable Resource selected Hi-Z GPIO selected External interrupt enabled selected Resource other than above selected Analog input selected Resource other than above selected Power supply stable INITX = 0 - INITX = 1 - Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Setting disabled GPIO selected Analog input selected M Timer mode, RTC mode, or Stop mode state Power supply stable INITX = 1 - Power supply stable INITX = 1 SPL = 0 Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Maintain previous Maintain previous state state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected 44 CONFIDENTIAL Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Resource other than above selected SPL = 1 Maintain previous Maintain previous Hi-Z / Internal input state state fixed at 0 Setting disabled Setting disabled Setting disabled GPIO selected L Device internal Run mode or reset state Sleep mode state Function group J K INITX input state Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Setting disabled Setting disabled Setting disabled Maintain previous Maintain previous state state Hi-Z / Internal input fixed at 0 MB9A420L_DS706-00054-2v0-E, March 31, 2015 Pin status type D a t a S h e e t Power-on reset or low-voltage detection state INITX input state Timer mode, RTC mode, or Stop mode state Device internal Run mode or reset state Sleep mode state Function group Power supply unstable - Power supply stable INITX = 0 - INITX = 1 - Analog output selected Setting disabled Setting disabled Setting disabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Power supply stable INITX = 1 - Power supply stable INITX = 1 SPL = 0 SPL = 1 *3 *4 Maintain previous state Maintain previous state N Resource other than above selected Maintain previous state Hi-Z Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode. *2: Oscillation is stopped at Stop mode. *3: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *4: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 45 D a t a S h e e t Electrical Characteristics 1. Absolute Maximum Ratings Parameter Power supply voltage*1, *2 Analog power supply voltage*1, *3 Analog reference voltage*1, *3 Symbol Min Max Unit Remarks VSS + 6.5 V VSS + 6.5 V VSS + 6.5 V VCC + 0.5 VSS - 0.5 V (≤ 6.5 V) Input voltage*1 VI VSS - 0.5 VSS + 6.5 V 5 V tolerant AV + 0.5 CC Analog pin input voltage*1 VIA VSS - 0.5 V (≤ 6.5 V) VCC + 0.5 Output voltage*1 VO VSS - 0.5 V (≤ 6.5 V) Clamp maximum current ICLAMP -2 +2 mA *7 Σ[ICLAMP] Clamp total maximum current +20 mA *7 10 mA 4 mA type L level maximum output current*4 IOL 20 mA 12 mA type 4 mA 4 mA type 5 L level average output current* IOLAV 12 mA 12 mA type L level total maximum output current ∑IOL 100 mA L level total average output current*6 ∑IOLAV 50 mA 10 mA 4 mA type H level maximum output current*4 IOH - 20 mA 12 mA type -4 mA 4 mA type 5 H level average output current* IOHAV - 12 mA 12 mA type H level total maximum output current ∑IOH - 100 mA H level total average output current*6 ∑IOHAV - 50 mA Power consumption PD 350 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that V SS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. 46 CONFIDENTIAL VCC AVCC AVRH Rating VSS - 0.5 VSS - 0.5 VSS - 0.5 MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t *7: ・ ・ ・ ・ ・ ・ ・ ・ See List of Pin Functions and I/O Circuit Type about +B input available pin. Use within recommended operating conditions. Use at DC voltage (current) the +B input. The +B signal should always be applied a limiting resistance placed between the +B signal and the device. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices. Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. The following is a recommended circuit example (I/O equivalent circuit). Protection Diode VCC VCC Limiting resistor P-ch Digital output +B input (0V to 16V) N-ch Digital input R AVCC Analog input <WARNING> Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 47 D a t a S h e e t 2. Recommended Operating Conditions (VSS = AVSS = AVRL = 0.0V) Parameter Symbol Conditions Value Min Max Unit Remarks 2.7*2 5.5 V 2.7 5.5 V AVCC = VCC 2.7 AVCC V Analog reference voltage AVSS AVSS V Smoothing capacitor 1 10 μF For Regulator*1 When mounted FPT-64P-M39, on four-layer - 40 + 105 °C FPT-52P-M02, PCB Operating FPT-64P-M38, TA temperature FPT-48P-M49, When mounted LCC-64P-M25, on double-sided - 40 + 85 °C LCC-48P-M74 single-layer PCB *1: See C Pin in Handling Devices for the connection of the smoothing capacitor. *2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. Power supply voltage Analog power supply voltage VCC AVCC AVRH AVRL CS <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions, or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. 48 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 3. DC Characteristics (1) Current Rating (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions PLL Run mode Run mode current ICC VCC Sleep mode current ICCS High-speed CR Run mode Sub Run mode Low-speed CR Run mode PLL Sleep mode High-speed CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode CPU: 40 MHz, Peripheral: 40 MHz Instruction on Flash CPU: 40 MHz, Peripheral: the clock stops NOP operation Instruction on Flash CPU: 40 MHz, Peripheral: 40 MHz Instruction on RAM Value Unit Remarks Typ Max 15.5 16 mA *1, *5 9 10.6 mA *1, *5 14 15 mA *1 CPU/ Peripheral: 4 MHz*2 Instruction on Flash 1.7 3.0 mA *1 CPU/ Peripheral: 32 kHz Instruction on Flash 63 900 μA *1, *6 CPU/ Peripheral: 100 kHz Instruction on Flash 88 920 μA *1 Peripheral: 40 MHz 9 12 mA *1, *5 Peripheral: 4 MHz*2 1 2.1 mA *1 Peripheral: 32 kHz 58 880 μA *1, *6 Peripheral: 100 kHz 71 890 μA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=5.5 V *4: TA=+105°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 49 D a t a S h e e t (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Main Timer mode ICCT Timer mode current Sub Timer mode ICCT VCC RTC mode current ICCR Stop mode current ICCH Value Unit Remarks Typ Max Conditions RTC mode Stop mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off mA *1 - mA *1 13 44 μA *1 - 730 μA *1 10 38 μA *1 - 570 μA *1 9 32 μA *1 - 540 μA *1 *1: When all ports are fixed. *2: VCC=5.5 V *3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) ・ LVD current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Low-Voltage detection circuit (LVD) power supply current Symbol Pin name Conditions VCC At operation for reset Vcc = 5.5 V At operation for interrupt Vcc = 5.5 V ICCLVD Value Typ Max Unit Remarks 0.13 0.3 μA At not detect 0.13 0.3 μA At not detect ・ Flash memory current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Flash memory write/erase current Symbol Pin name Conditions ICCFLASH VCC At Write/Erase Value Typ Max Unit 9.5 mA 11.2 Remarks ・ A/D convertor current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Symbol Pin name Power supply current ICCAD AVCC Reference power supply current ICCAVRH AVRH Parameter 50 CONFIDENTIAL Conditions At operation At stop At operation AVRH=5.5 V At stop AVRH=5.5 V Value Typ Max Unit 0.7 0.13 0.9 13 mA μA 1.1 1.97 mA 0.1 1.7 μA Remarks MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t ・ D/A convertor current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions AVCC At operation AVCC = 3.3 V At operation AVCC = 5.0 V At stop IDDA Power supply current *: IDSA Value Typ Max Unit Remarks 315 380 μA * 475 580 μA * - 8 μA * No-load March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 51 D a t a S h e e t (2) Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name H level input voltage (hysteresis input) VIHS L level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin 4mA type H level output voltage VOH 12mA type 4mA type L level output voltage VOL 12mA type Input leak current Pull-up resistance value Input capacitance 52 CONFIDENTIAL IIL - RPU Pull-up pin CIN Other than VCC, VSS, AVCC, AVSS, AVRH, AVRL Min Value Typ Max - VCC × 0.8 - VCC + 0.3 V - VCC × 0.8 - VSS + 5.5 V - VSS - 0.3 - VCC × 0.2 V - VSS - 0.3 - VCC × 0.2 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VSS - 0.4 V VSS - 0.4 V - -5 - +5 μA VCC ≥ 4.5 V 33 50 90 VCC < 4.5 V - - 180 - - 5 15 Conditions VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 2 mA VCC ≥ 4.5 V, IOH = - 12 mA VCC < 4.5 V, IOH = - 8 mA VCC ≥ 4.5 V, IOL = 4 mA VCC < 4.5 V, IOL = 2 mA VCC ≥ 4.5 V, IOL = 12 mA VCC < 4.5 V, IOL = 8 mA Unit Remarks kΩ pF MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 4. AC Characteristics (1) Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time Symbol Pin Conditions name Value Min Max Unit VCC ≥ 4.5 V VCC < 4.5 V 4 4 48 20 MHz - 4 48 MHz - 20.83 250 ns - PWH/tCYLH, PWL/tCYLH 45 55 % tCF, tCR - - 5 ns - - 40 MHz fCH tCYLH fCM X0, X1 - Remarks When crystal oscillator is connected When using external Clock When using external Clock When using external Clock When using external Clock Master clock Base clock fCC 40 MHz (HCLK/FCLK) Internal operating clock frequency*1 fCP0 40 MHz APB0 bus clock*2 fCP1 40 MHz APB1 bus clock*2 fCP2 40 MHz APB2 bus clock*2 Base clock tCYCC 25 ns (HCLK/FCLK) Internal operating t 25 ns APB0 bus clock*2 CYCP0 clock cycle time*1 tCYCP1 25 ns APB1 bus clock*2 tCYCP2 25 ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 53 D a t a S h e e t (2) Sub Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Input frequency Symbol Max - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs Unit fCL X0A, X1A Input clock cycle Min Value Typ Pin Conditions name tCYLL Input clock pulse PWH/tCYLL, 45 55 width PWL/tCYLL *: See Sub crystal oscillator in Handling Devices for the crystal oscillator used. % Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock X0A 54 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t (3) Built-in CR Oscillation Characteristics ・ Built-in High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Clock frequency Symbol fCRH Value Min Typ Max Conditions TA = + 25°C, 3.6 V < VCC ≤ 5.5 V TA =0°C to + 85°C, 3.6 V < VCC ≤ 5.5 V TA = - 40°C to + 105°C, 3.6 V < VCC ≤ 5.5 V TA = + 25°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 20°C to + 85°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 20°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 40°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V TA = - 40°C to + 105°C 3.92 4 4.08 3.9 4 4.1 3.88 4 4.12 3.94 4 4.06 Unit Remarks When trimming*1 MHz 3.92 4 4.08 3.9 4 4.1 3.88 4 4.12 2.8 4 5.2 When not trimming Frequency tCRWT 30 μs *2 stabilization time *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming. *2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. ・ Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Clock frequency Symbol Conditions fCRL - March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Min Value Typ Max 50 100 150 Unit Remarks kHz 55 D a t a S h e e t (4-1) Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Min Value Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 100 μs (LOCK UP time) PLL input clock frequency fPLLI 4 16 MHz PLL multiplication rate 5 37 multiplier PLL macro oscillation clock frequency fPLLO 75 150 MHz Main PLL clock frequency*2 fCLKPLL 40 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. (4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time*1 tLOCK 100 μs (LOCK UP time) PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate 19 35 multiplier PLL macro oscillation clock frequency fPLLO 72 150 MHz Main PLL clock frequency*2 fCLKPLL 40 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main PLL connection PLL input clock K divider Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider 56 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t (5) Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Reset input time tINITX Value Pin Conditions name Min Max INITX 500 - - Unit Remarks ns (6) Power-on Reset Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Power supply rising time tVCCR Power supply shut down time Time until releasing Power-on reset tOFF Pin name Value Max 0 - ms 1 - ms 0.34 3.15 ms VCC tPRT Unit Min Remarks VCC_minimum VCC VDH_minimum 0.2V 0.2V 0.2V tVCCR tPRT Internal reset Reset active CPU Operation Glossary ・VCC_minimum: ・VDH_minimum: Release start Minimum VCC of recommended operating conditions. Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset. See 7. Low-Voltage Detection Characteristics. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL tOFF 57 D a t a S h e e t (7) Base Timer Input Timing ・ Timer input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Input pulse width Symbol Pin name Conditions tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK TIN VIHS VIHS VILS VILS ・ Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Input pulse width Symbol Pin name Conditions tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. 58 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t (8) CSIO/UART Timing ・ CSIO (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol VCC < 4.5 V Min Max SCKx SCKx, SOTx SCKx, Master mode SINx SCKx, SINx 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time Notes: ・ ・ ・ ・ ・ tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 10 tCYCP + 10 - 2tCYCP 10 tCYCP + 10 Unit - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL VCC ≥ 4.5 V Min Max Pin Conditions name 59 D a t a S h e e t tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL Master mode tSLSH SCK tSHSL VIH VIH tF VIL VIL VIH tR tSLOVE SOT SIN VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL Slave mode 60 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t ・ CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol VCC < 4.5 V Min Max SCKx SCKx, SOTx SCKx, Master mode SINx SCKx, SINx 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK falling time SCK rising time Notes: ・ ・ ・ ・ ・ tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 10 tCYCP + 10 - 2tCYCP 10 tCYCP + 10 Unit - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL VCC ≥ 4.5 V Min Max Pin Conditions name 61 D a t a S h e e t tSCYC SCK VOH VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH SIN tSLIXI VIH VIL VIL Master mode tSHSL SCK VIH VIH VIL tR SOT tSLSH tF tSHOVE VOH VOL tIVSLE SIN VIL VIL VIH VIL tSLIXE VIH VIL Slave mode 62 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t ・ CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol VCC < 4.5 V Min Max SCKx SCKx, SOTx SCKx, SINx Master mode SCKx, SINx SCKx, SOTx 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns - ns - ns - ns Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓→ SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock L pulse width tSLSH SCKx Serial clock H pulse width tSHSL SCKx SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓→ SIN hold time tSLIXE SCK falling time SCK rising time Notes: ・ ・ ・ ・ ・ tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 Unit - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL VCC ≥ 4.5 V Min Max Pin Conditions name 63 D a t a S h e e t tSCYC VOH SCK VOL tSOVLI SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI VIH VIL Master mode tSLSH VIH SCK SOT VIL VIL tF * VOH VOL tR tIVSLE SIN tSHSL VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register 64 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t ・ CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin Conditions name VCC < 4.5 V Min Max VCC ≥ 4.5 V Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI - ns Serial clock L pulse width tSLSH SCKx - ns Serial clock H pulse width tSHSL SCKx - ns SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK falling time SCK rising time Notes: ・ ・ ・ ・ ・ tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 2tCYCP 30 2tCYCP 10 tCYCP + 10 - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Slave mode The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pF. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL SCKx, SINx Master mode SCKx, SINx SCKx, SOTx 65 D a t a S h e e t tSCYC VOH SCK tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL Master mode tR SCK VIL tF tSHSL VIH VIH tSLSH VIL VIL tSLOVE VOH VOL SOT VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode ・ UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time tSLSH tSHSL tF tR CL = 30 pF tR SCK 66 CONFIDENTIAL Value Symbol Conditions VIL Max tCYCP + 10 tCYCP + 10 - 5 5 tF tSHSL VIH Min VIH VIL Unit Remarks ns ns ns ns tSLSH VIL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t (9) External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Min Max Unit ADTG FRCKx Input pulse width tINH, tINL - 2tCYCP*1 - ns Remarks A/D converter trigger input Free-run timer input clock Input capture Waveform enerator PPG IGBT mode External interrupt, NMI ICxx DTTIxX 2tCYCP*1 ns IGTRG 2tCYCP*1 ns *2 2tCYCP + 100*1 ns INTxx, NMIX *3 500 ns *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in stop mode, in RTC mode, in timer mode. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 67 D a t a S h e e t 2 (10) I C Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency fSCL 0 100 0 400 kHz (Repeated) Start condition hold time tHDSTA 4.0 0.6 μs SDA ↓ → SCL ↓ SCLclock L width tLOW 4.7 1.3 μs SCLclock H width tHIGH 4.0 0.6 μs (Repeated) Start condition setup time tSUSTA 4.7 0.6 μs CL = 30 pF, SCL ↑ → SDA ↓ R= Data hold time (Vp/IOL)*1 tHDDAT 0 3.45*2 0 0.9*3 μs SCL ↓ → SDA ↓ ↑ Data setup time tSUDAT 250 100 ns SDA ↓ ↑ → SCL ↑ Stop condition setup time tSUSTO 4.0 0.6 μs SCL ↑ → SDA ↑ Bus free time between Stop condition and tBUF 4.7 1.3 μs Start condition Noise filter tSP 2 tCYCP*4 2 tCYCP*4 ns *1:R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2:The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3:A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4:tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL 68 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t (11) JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions TCK, TMS, TDI TCK, TMS, TDI VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V TMS, TDI setup time tJTAGS TMS, TDI hold time tJTAGH TDO delay time tJTAGD TCK, TDO VCC < 4.5 V Note: When the external load capacitance CL = 30 pF. Value Min Max Unit 15 - ns 15 - ns - 25 - 45 Remarks ns TCK TMS/TDI TDO March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 69 D a t a S h e e t 5. 12-bit A/D Converter ・Electrical characteristics for the A/D converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage Full-scale transition voltage Conversion time Symbol Pin name Min Value Typ Max Unit VZT ANxx - ± 2.0 ± 1.5 ±8 12 ± 4.5 ± 2.5 ± 15 bit LSB LSB mV VFST ANxx - AVRH ± 8 AVRH ± 15 mV - - tS tCCK - 0.8*1 1.0*1 0.24 40 - 10 1000 μs μs μs ns Sampling time*2 Compare clock cycle*3 State transition time to operation permission Analog input capacity tSTT - - - 1.0 μs CAIN - - - pF Analog input resistor RAIN - - - Interchannel disparity Analog port input leak current Analog input voltage - - - - 9.7 1.5 2.2 4 LSB - ANxx - - 5 μA kΩ Remarks AVRH = 2.7 V to 5.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V ANxx AVRL AVRH V AVRH 2.7 AVCC Reference voltage V AVRL AVSS AVSS *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 4.5 V, HCLK=25 MHz sampling time: 240 ns, compare time: 560 ns AVCC < 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2). 70 CONFIDENTIAL - MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Comparator REXT ANxx RAIN Analog signal source CAIN (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: RAIN: CAIN: REXT: Sampling time Input resistor of A/D = 1.3 kΩ at 4.5 V < AVCC < 5.5 V ch.0 to ch.2, ch.4, ch.5 Input resistor of A/D = 1.5 kΩ at 4.5 V < AVCC < 5.5 V ch.12 to ch.14 Input resistor of A/D = 1.9 kΩ at 2.7 V < AVCC < 4.5 V ch.0 to ch.2, ch.4, ch.5 Input resistor of A/D = 2.2 kΩ at 2.7 V < AVCC < 4.5 V ch.12 to ch.14 Input capacity of A/D = 9.7 pF at 2.7 V < AVCC < 5.5 V Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: tCCK: Compare time Compare clock cycle March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 71 D a t a S h e e t ・Definition of 12-bit A/D Converter Terms ・ Resolution: ・ Integral Nonlinearity: ・ Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD 0xN Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics 0x002 VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVRL Actual conversion characteristics AVRH AVRL AVRH Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: 72 CONFIDENTIAL Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 6. 10-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Resolution Symbol Integral Nonlinearity Differential Nonlinearity tC20 tC100 INL DNL Output Voltage offset VOFF Conversion time Analog output impedance Output undefined period *: No-load RO tR March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Pin name DAx Min Value Typ Max 0.47 2.37 - 4.0 - 0.9 - 20.0 3.10 2.0 - 0.58 2.90 3.80 - 10 0.69 3.43 + 4.0 + 0.9 10.0 + 5.4 4.50 70 Unit Remarks bit μs μs LSB LSB mV mV kΩ MΩ ns Load 20 pF Load 100 pF * * Code is 0x000 Code is 0x3FF D/A operation D/A stop 73 D a t a S h e e t 7. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset (TA = - 40°C to + 105°C) Parameter Symbol Conditions Min Value Typ Max Unit Remarks Detected voltage VDL 2.25 2.45 2.65 V When voltage drops SVHR*1 = 00000 Released voltage VDH 2.30 2.50 2.70 V When voltage rises Detected voltage VDL 2.39 2.60 2.81 V When voltage drops SVHR*1 = 00001 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 2.48 2.70 2.92 V When voltage drops SVHR*1 = 00010 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 2.58 2.80 3.02 V When voltage drops *1 SVHR = 00011 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 2.76 3.00 3.24 V When voltage drops *1 SVHR = 00100 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 2.94 3.20 3.46 V When voltage drops SVHR*1 = 00101 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 3.31 3.60 3.89 V When voltage drops SVHR*1 = 00110 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 3.40 3.70 4.00 V When voltage drops *1 SVHR = 00111 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 3.68 4.00 4.32 V When voltage drops *1 SVHR = 01000 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 3.77 4.10 4.43 V When voltage drops SVHR*1 = 01001 Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL 3.86 4.20 4.54 V When voltage drops SVHR*1 = 01010 Released voltage VDH Same as SVHR = 0000 value V When voltage rises LVD stabilization 8160 × tLVDW μs wait time tCYCP*2 LVD detection tLVDDL 200 μs delay time *1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low voltage detection reset. *2: tCYCP indicates the APB2 bus clock cycle time. 74 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t (2) Interrupt of Low-Voltage Detection (TA = - 40°C to + 105°C) Parameter Symbol Conditions Detected voltage VDL SVHI = 00011 Released voltage VDH Detected voltage VDL SVHI = 00100 Released voltage VDH Detected voltage VDL SVHI = 00101 Released voltage VDH Detected voltage VDL SVHI = 00110 Released voltage VDH Detected voltage VDL SVHI = 00111 Released voltage VDH Detected voltage VDL SVHI = 01000 Released voltage VDH Detected voltage VDL SVHI = 01001 Released voltage VDH Detected voltage VDL SVHI = 01010 Released voltage VDH LVD stabilization tLVDW wait time LVD detection tLVDDL delay time *: tCYCP indicates the APB2 bus clock cycle time. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Min Value Typ 2.58 2.67 2.76 2.85 2.94 3.04 3.31 3.40 3.40 3.50 3.68 3.77 3.77 3.86 3.86 3.96 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 - - - - Max 3.02 3.13 3.24 3.35 3.46 3.56 3.89 4.00 4.00 4.10 4.32 4.43 4.43 4.54 4.54 4.64 8160 × tCYCP* 200 Unit Remarks V V V V V V V V V V V V V V V V When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises μs μs 75 D a t a S h e e t 8. Flash Memory Write/Erase Characteristics (1) Write / Erase time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Value Parameter Typ Max Unit Remarks Includes write time prior to internal erase Not including system-level overhead Half word (16-bit) write time 16 282 μs time Includes write time prior to internal Chip erase time 2.4 5.6 s erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycle of erase/write. Sector erase time 0.3 0.7 s (2) Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* 10,000 *: At average + 85C 76 CONFIDENTIAL Remarks 10* MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 9. Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. ・ Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Typ tICNT Sub Timer mode Unit Remarks μs 43 83 μs 310 620 μs 534 724 μs 479 μs RTC mode, 278 Stop mode *: The maximum value depends on the accuracy of built-in CR. ・ Max* tCYCC Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode Value Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 77 D a t a S h e e t ・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: 78 CONFIDENTIAL ・ The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. ・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t (2) Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. ・ Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Typ Max* 149 264 μs 149 264 μs 318 603 μs Sub Timer mode 308 583 μs RTC/Stop mode 248 443 μs Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode tRCNT Remarks *: The maximum value depends on the accuracy of built-in CR. ・ Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Start 79 D a t a S h e e t ・ Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: 80 CONFIDENTIAL ・ The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. ・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. ・ The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low -voltage detection reset. ・ When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. ・ The internal resource reset means the watchdog reset and the CSV reset. MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Ordering Information On-chip Flash memory On-chip SRAM Package MB9AF421KWQN-G-JNE2 64 Kbyte 4 Kbyte Plastic QFN (0.5 mm pitch), 48-pin (LCC-48P-M74) MB9AF421KPMC-G-JNE2 64 Kbyte 4 Kbyte Plastic LQFP (0.5 mm pitch), 48-pin (FPT-48P-M49) MB9AF421KPMC1-G-JNE2 64 Kbyte 4 Kbyte Plastic LQFP (0.65 mm pitch), 52-pin (FPT-52P-M02) Part number MB9AF421LPMC1-G-JNE2 64 Kbyte 4 Kbyte Plastic LQFP (0.5 mm pitch), 64-pin (FPT-64P-M38) MB9AF421LPMC-G-JNE2 64 Kbyte 4 Kbyte Plastic LQFP (0.65 mm pitch), 64-pin (FPT-64P-M39) MB9AF421LWQN-G-JNE2 64 Kbyte 4 Kbyte Plastic QFN (0.5 mm pitch), 64-pin (LCC-64P-M25) March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Packing Tray 81 D a t a S h e e t Package Dimensions 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g (FPT-64P-M38) 64-pin plastic LQFP (FPT-64P-M38) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 48 0.145 ± 0.055 (.006 ± .002) 33 Details of "A" part 32 49 0.08(.003) +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° INDEX 1 0.22±0.05 (.009±.002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2 82 CONFIDENTIAL 0.10 ± 0.10 (.004±.004) (Stand off) "A" 16 0.50(.020) C 0.50±0.20 (.020±.008) 0.60 ± 0.15 (.024±.006) 17 64 M Dimensions in mm (inches). Note: The values in parentheses are reference values. MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-64P-M39) 64-pin plastic LQFP (FPT-64P-M39) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ *12.00±0.10(.472±.004)SQ 48 0.145± 0.055 (.006 ±. 002) 33 Details of "A" part 32 49 +0.20 1.50 –0.10 .059 +.008 –.004 0.10(.004) INDEX 64 16 0.65(.026) C 0.32±0.05 (.013±.002) 2010-2013 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-4-3 March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 17 1 0~8˚ 0.10±0.10 (.004±.004) 0.25(.010)BSC "A" 0.13(.005) M Dimensions in mm (inches). Note: The values in parentheses are reference values. 83 D a t a S h e e t 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.17 g (FPT-48P-M49) 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00 ± 0.20(.354 ± .008)SQ *7.00± 0.10(.276 ± .004)SQ 36 0.145± 0.055 (.006 ± .002) 25 24 37 0.08(.003) 13 48 "A" 1 C CONFIDENTIAL 0°~8° 0.10 ± 0.10 (.004 ± .004) (Stand off) 12 0.22 ± 0.05 (.008 ± .002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 84 +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 INDEX 0.50(.020) Details of "A" part 0.25(.010) M 0.60 ± 0.15 (.024 ± .006) Dimensions in mm (inches). Note: The values in parentheses are reference values. MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 52-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 10.00 × 10.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g Code (Reference) P-LFQFP52-10 × 10-0.65 (FPT-52P-M02) 52-pin plastic LQFP (FPT-52P-M02) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 39 0.145±0.055 (.006±.002) 27 40 Details of "A" part 26 +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 0.25(.010) INDEX 0.10(.004) 52 14 "A" 1 13 0.65(.026) +0.065 0.30 –0.035 +.0026 .012 –.0014 C 2010 FUJITSU SEMICONDUCTOR LIMITED F52002Sc-2-1 March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 0~8˚ 0.13(.005) M 0.50±0.20 (.020±.008) 0.10±0.10 (.004±.004) (Stand off) 0.60±0.15 (.024±.006) Dimensions in mm (inches). Note: The values in parentheses are reference values 85 D a t a S h e e t 48-pin plastic QFN Lead pitch 0.50 mm Package width× package length 7.00 mm × 7.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.12 g (LCC-48P-M74) 48-pin plastic QFN (LCC-48P-M74) 7.00±0.10 (.276±.004) INDEX AREA 4.65±0.15 (.183±.006) 7.00±0.10 (.276±.004) 4.65±0.15 (.183±.006) +0.05 0.25 -0.07 (.010 +.002 ) -.003 1PIN CORNER C0.30(C.020) 0.50(.020) (TYP) 0.75±0.05 (.030±.002) +0.03 (0.20) ((.008)) C 0.50±0.05 (.020±.002) 0.02 -0.02 (.0008 +.0012 ) -.0008 2013 FUJITSU SEMICONDUCTOR LIMITED HMbC48-74Sc-1-1 86 CONFIDENTIAL Dimensions in mm (inches). Note: The values in parentheses are reference values. MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t 64-pin plastic QFN Lead pitch 0.50 mm Package width × package length 9.00 mm × 9.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.21 g (LCC-64P-M25) 64-pin plastic QFN (LCC-64P-M25) 9.00±0.10 (.354±.004) INDEX AREA 7.20±0.15 (.283±.006) 9.00±0.10 (.354±.004) 7.20±0.15 (.283±.006) 0.25±0.05 (.010±.002) 1PIN CORNER C0.50(C.020) 0.50(.020) (TYP) 0.75±0.05 (.030±.002) (0.20) ((.008)) C +0.03 0.02 -0.02 (.0008 +.0012 -.0008 ) 2013 FUJITSU SEMICONDUCTOR LIMITED HMbC64-25Sc-1-1 March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL 0.40±0.05 (.016±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. 87 D a t a S h e e t Major Changes Page Section Revision 0.1 Revision 0.2 Revision 1.0 2 FEATURES 3 FEATURES 4 FEATURES 6 17 29 37 47 48,49 49 55 66 68 71 72,73 74 - Initial release - Company name and layout design change - Preliminary → Full Production Revised I2C operation mode name Revised the value of A/D conversion time Revised Channel number of MFT A/D activation compare ・Added notes of Built-in high speed CR accuracy ・Revised channel number of MFT A/D activation compare PRODUCT LINEUP LIST OF PIN FUNCTION ・List of pin numbers I/O CIRCUIT TYPE BLOCK DIAGRAM ELECTRICAL CHARACTERISTICS 2. Recommended Operating Conditions ELECTRICAL CHARACTERISTICS 3.DC Characteristics (1) Current Rating ELECTRICAL CHARACTERISTICS 3.DC Characteristics (1) Current Rating ・A/D converter current ELECTRICAL CHARACTERISTICS 3.AC Characteristics (6)Power-on Reset Timing ELECTRICAL CHARACTERISTICS 3.AC Characteristics (10) I2C Timing ELECTRICAL CHARACTERISTICS 5. 12-bit A/D Converter ELECTRICAL CHARACTERISTICS 6. 10-bit D/A Converter ELECTRICAL CHARACTERISTICS 7. Low-Voltage Detection Characteristics ELECTRICAL CHARACTERISTICS 8. Flash Memory Write/Erase Characteristics ELECTRICAL CHARACTERISTICS 9. Return Time from Low-Power Consumption Mode 84,85 PACKAGE DIMENSIONS Revision 2.0 26 I/O Circuit Type Memory Map 39 · Memory map(2) Electrical Characteristics 46, 47 1. Absolute Maximum Ratings Electrical Characteristics 48 2. Recommended Operation Conditions Electrical Characteristics 49, 50 3. DC Characteristics (1) Current rating Electrical Characteristics 4. AC Characteristics 56 (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 57 4. AC Characteristics (6) Power-on Reset Timing Electrical Characteristics 59-66 4. AC Characteristics (8) CSIO/UART Timing Electrical Characteristics 70 5. 12bit A/D Converter 75,77 88 CONFIDENTIAL Change Results Corrected I/O circuit type of P80,P81,P82 Added the remarks of type L Revised Channel number of MFT A/D activation compare Corrected the minimum value of AVRH voltage Revised the values of “TBD” ・Corrent the pin name of power supply current ・Added the at stop condition of power supply current ・Added the remark of reference power supply current Revised the values of “TBD” ・Revised I2C operation mode name ・Revised the value of noise filter ・Revised the value of zero transition valtage and full-scale transiton valtage ・Revised the value of conversion time, sampling time, compare clock cycle ・Corrected the value of state transition time to operation permission ・Corrected the minimum value of AVRH voltage ・Revised the notes explanation ・Delete (Preliminary value) description ・Delete (Preliminary value) description ・Corrected the values of SVHR and SVHI ・Revised the values of “TBD” ・Revised the values of typical ・Revised the notes of Erase/write cycles and data hold time ・Delete (target value) description Revised the values of “TBD” Added the figures of LCC-48P-M74 and LCC-64P-M25 Added about +B input Added the summary of Flash memory sector and the note · Added the Clamp maximum current · Added about +B input Added the note about less than the minimum power supply voltage · Changed the table format · Added Main TIMER mode current Added the figure of Main PLL connection Changed the figure of timing · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage MB9A420L_DS706-00054-2v0-E, March 31, 2015 D a t a S h e e t Page 81 Section Ordering Information March 31, 2015, MB9A420L_DS706-00054-2v0-E CONFIDENTIAL Change Results Changed notation of part number 89 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2013-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM , Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 90 CONFIDENTIAL MB9A420L_DS706-00054-2v0-E, March 31, 2015