Q1 - 2004

CYPRESS
QUALITY & RELIABILITY
2004 Q1 RELIABILITY REPORT
TABLE OF CONTENTS
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY
MANAGEMENT SYSTEM
2.0 EARLY FAILURE RATE SUMMARY
3.0 LONG TERM FAILURE RATE SUMMARY
4.0 PRESSURE COOKER TEST
5.0 HAST (Highly Accelerated Stress Test)
6.0 TEMPERATURE CYCLE
Note: The results reported herein are for 1st Quarter 2004.
CYPRESS
QUALITY & RELIABILITY
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM
This report summarizes Cypress Semiconductor Product Reliability for the period of the 1st quarter of
2004. It includes data from product fabricated at the San Jose, California; Round Rock, Texas; and
Bloomington, Minnesota facilities.
Cypress Semiconductor has established aggressive reliability objectives to assure that all products
exhibit reliability, which exceeds customer reliability requirements for purchased components. The
quality standard at Cypress is zero defects resulting in a culture requiring continuous improvement in
quality and reliability.
Product reliability is assured by a total quality management system. The quality management system
is described in detail in the Cypress Semiconductor Quality Manual (Cypress Semiconductor
Document Number 90-00001). Key reliability-related programs of the total quality management
system are: (1) design rule review and approval; (2) control of raw materials and vendor quality; (3)
manufacturing statistical process controls; (4) manufacturing identification of "Maverick Lot" yield
limits; (5) formal training and certification of manufacturing personnel; (6) qualification of new products
and manufacturing processes; (7) continuous reliability monitoring; (8) formal failure analysis and
corrective action; and (9) competitive benchmarking.
Product Reliability data is accumulated as a result of new product Qualification Test Plan activities
(Cypress Semiconductor Document Number 25-00040) as well as from the Reliability Monitor Program
(Cypress Semiconductor Document Number 25-00008). All reliability test samples are obtained from
standard production material. Sample selection is based on generic product families. These generic
products are designed with very similar design rules and manufactured from a core set of processes.
Reliability strategy requires that every failure that occurs during reliability testing be subjected to failure
analysis (Cypress Semiconductor Document Number 25-00039) to determine the failure mechanism.
Corrective action is then implemented to prevent future failures, resulting in continuous improvement
in product reliability.
Copies of the Cypress Semiconductor documents referenced herein are available through your
Cypress Semiconductor sales representative. Questions about product reliability may be addressed to
the undersigned.
____________________
Director of Reliability
___________________
Director of Quality
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134-1599
Cypress Quality Fax: (408) 943-2165
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QUALITY & RELIABILITY
CYPRESS
2.0 EARLY FAILURE RATE SUMMARY
Early Failure Rate Determination: High Temperature Operating Life testing (HTOL), for as long as 96
hours, is used to estimate device early failure rate.
Test:
Conditions:
Duration:
Failure:
Fit Rate:
High Temperature Operating Life Test (HTOL)
Dynamic Operating Conditions, VCC nominal + 15%, 150°C or 125°C.
48 hours HTOL at 150°C or 96 hours at 125°C.
A failure is any device that fails to meet data sheet electrical requirements.
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Early Failure Rate Summary
Technology
Device Hours
# Failed
FIT Rate
0.165um
B55
B53
FL28
L28
NEC 0.25
Promos 0.17
R28
R32
R42
R52
132,751
170,623
76,320
14,090
74,008
72,000
190,637
16,150
322,416
316,756
1,920,768
0
1
0
0
0
0
2
0
0
0
8
Insufficient
35
Insufficient
Insufficient
Insufficient
Insufficient
48
Insufficient
17
17
14
R6
23,168
0
Insufficient
R7
2,415,104
9
13
R8
1,787,529
4
9
347,141
60,697
31,401
146,160
0
0
0
0
16
Insufficient
Insufficient
37
S4
T015
TSMC 0.18
TSMC 0.25
Failure Mode
None
1 unit (particle)
None
None
None
None
2 units (non-visual)
None
None
None
3 units (burnt metallization)
3 units (poly protrusions)
1 unit (shorted metal)
1 unit (unknown)
1 unit (metal line scratched)
3 units (poly protrusions)
4 units (burned metallization)
2 unit s (poly protrusions)
1 unit (inconclusive)
1 unit (nitride particle)
1 unit (non-visual)
1 unit (nitride/poly protrusions)
1 unit (inconclusive)
1 unit (burnt metallization)
1 unit (die crack)
None
None
None
None
Notes: Data reported is a 4-quarter rolling average.
Insufficient data – interpret as insufficient accumulated life-time hours to project a 60%
confidence bound for a zero-fails sample.
QUALITY & RELIABILITY
CYPRESS
3.0 LONG TERM FAILURE RATE SUMMARY
Long Term Failure Rate Determination A High Temperature Operating Life test (HTOL) is used to
estimate long-term reliability. By operating the devices at accelerated temperature and voltage,
hundreds of thousands of use hours can be compressed into hundreds of test hours.
Test:
High Temperature Operating Life Test (HTOL)
Conditions: Dynamic Operating Conditions, VCC nominal +15% 150°C or 125°C.
Duration: A minimum of 80 hours at 150°C or 168 hours at 125°C
Generally 500 hours at 150°C or 1000 hours at 125°C.
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Fit Rate:
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Long Term Failure Rate Summary
Technology
Device Hours
0.165um
B5
FL28
L28
NEC 0.25
Promos .17
R28
R42
R52
R6
R7
R8
S4
TSMC 0.18
TSMC 0.25
373,871
405,403
83,871
278,032
108,052
752,440
96,129
1,021,357
1,023,859
195,196
2,051,060
1,926,475
720,997
78,039
168,560
# Failed
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
FIT Rate
Failure Mode
14
None
13
None
Insufficient None
19
None
Insufficient None
7
None
Insufficient None
5
None
5
None
28
None
3
None
3
None
8
1 unit (inconclusive)
Insufficient None
32
None
Notes: Data reported is a 4-quarter rolling average.
Insufficient data – interpret as insufficient accumulated lifetime hours to project a 60%
confidence bound for a zero-fails sample.
QUALITY & RELIABILITY
CYPRESS
4.0 PRESSURE COOKER TEST (PCT)
The Pressure Cooker Test is a highly accelerated packaging stress test used to ensure environmental
durability of epoxy-packaged parts.
Passivation cracks, ionic contamination, and corrosion
susceptibility are all accelerated by this stress.
Test:
Conditions:
Pre-Conditioning:
Failure:
Pressure Cooker Test (PCT)
15 PSIG, 121°C, No bias, for a minimum of 168 hours.
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
A failure is any device that fails to meet data sheet electrical requirements.
Pressure Cooker Test Failure Rate Summary
Package
Sample
Size
# Failed
Defects %
Failure Mode
TQFP
1585
TQFP (10x10) 100
0
0
0
0
None
None
TQFP
(Thermal)
FBGA (0.750.8)
FBGA (1.0)
PBGA (1.27)
282
0
0
None
1106
0
0
None
327
227
0
0
0
0
None
None
VFBGA (0.75- 982
0.8)
PLCC
952
MLF
149
PQFP
377
SSOP
812
PDIP
719
0
0
None
0
0
0
0
0
0
0
0
0
0
None
None
None
None
None
SOIC
1506
(GullWing)
SOIC
414
(GullWing, 300)
SOIC (J)
801
TSOP
1384
TSOP I
98
ETSSOP
142
0
0
None
0
0
None
0
0
0
0
0
0
0
0
None
None
None
None
TSOP II
0
0
None
241
Note: Data reported is a 4-quarter rolling average.
QUALITY & RELIABILITY
CYPRESS
5.0 HIGHLY ACCELERATED STRESS TEST (HAST)
Cypress uses HAST to accelerate temperature, humidity, bias failure mechanisms. This change was
necessary because our package reliability had improved to the point where the old 85°C/85% R.H.
Temperature-humidity-bias testing would not induce failures. Failures are necessary to judge
progress and compare packaging changes. HAST testing has been shown to be at least twenty times
more accelerated then 85°C/85% R.H. temperature-humidity-bias testing.
Test:
Conditions:
Highly Accelerated Stress Test (HAST)
Present Conditions: 130°C / 85% RH minimum power dissipation, for a
minimum of 128 hours.
Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Highly Accelerated Stress Test (HAST) Failure Rate Summary
Package
Sample Size
# Failed
Defects %
Failure Mode
TQFP
706
TQFP(10x10)
194
TQFP(Thermal)
231
FBGA(0.75-0.8)
608
FBGA(1.0)
96
VFBGA(0.75-0.8) 659
PLCC
483
MLF(QFN)
98
PQFP
100
SSOP
PDIP
388
SOIC(GullWing)
1286
SOIC(GullWing,300)353
SOIC(J)
663
0
0
0
1
0
0
0
0
0
0
0
0
0.2
0.0
0
0
0
0
None
None
None
1 unit (die crack)
None
None
None
None
None
0
0
0
0
0
0
0
0
None
None
None
None
TSOP
TSOPI
TSOP(Reverse)
TSOPII
0
0
0
0
0
0
0
0
None
None
None
None
1133
100
49
261
Note: Data reported is a 4-quarter rolling average.
QUALITY & RELIABILITY
CYPRESS
6.0 TEMPERATURE CYCLE TEST (TC)
Differences in thermal expansion coefficients are accentuated by cycling devices through temperature
extremes. If the materials do not expand and contract equally, large stresses can develop. The
Temperature Cycle test stresses mechanical integrity by exposing a device to alternating temperature
extremes. Weakness and thermal expansion mismatches in die interconnections, die attach, and wire
bonds are often detected with this acceleration test.
Test:
Condition:
Temperature Cycle
MIL-STD-883D, Method 1010, Condition C, -65°C to 150°C.
JEDEC 22-A104 Condition B, -40°C to 125°C
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
300 cycles minimum at Condition C, 1000 cycles minimum at Condition B
A failure is any device that fails to meet data sheet electrical requirements.
Pre-Condition:
Duration:
Failure:
Temperature Cycling Failure Rate Summary
Package
Sample Size
# Failed
Defects %
Failure Mode
FBGA (0.75-0.8)
FBGA (1.0)
PBGA (1.27)
PDIP
PLCC
1524
579
187
569
966
0
0
0
0
1
0
0
0
0
0.1
PQFP
SOIC (GullWing)
SOIC (GullWing, 300)
SOIC (J)
SSOP
TQFP (10x10)
TQFP
TQFP (Thermal)
TSOP
TSOP (Reverse)
TSOP I
TSOP II
VFBGA (0.75-0.8)
ETSSOP
362
1796
506
845
998
98
2100
382
1893
100
100
234
992
144
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
None
None
None
None
1 unit burnt
metallization
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Note: Data reported is a 4-quarter rolling average.