Q1 - 2003

CYPRESS
QUALITY & RELIABILITY
2003 Q1 RELIABILITY REPORT
TABLE OF CONTENTS
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY
MANAGEMENT SYSTEM
2.0 EARLY FAILURE RATE SUMMARY
3.0 LONG TERM FAILURE RATE SUMMARY
4.0 PRESSURE COOKER TEST
5.0 HAST (Highly Accelerated Stress Test)
6.0 TEMPERATURE CYCLE
Note: The results reported herein are for 1st Quarter 2003.
CYPRESS
QUALITY & RELIABILITY
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM
This report summarizes Cypress Semiconductor Product Reliability for the period of the 1st quarter of
2003. It includes data from product fabricated at the San Jose, California; Round Rock, Texas; and
Bloomington, Minnesota facilities.
Cypress Semiconductor has established aggressive reliability objectives to assure that all products
exhibit reliability, which exceeds customer reliability requirements for purchased components. The
quality standard at Cypress is zero defects resulting in a culture requiring continuous improvement in
quality and reliability.
Product reliability is assured by a total quality management system. The quality management system
is described in detail in the Cypress Semiconductor Quality Manual (Cypress Semiconductor
Document Number 90-00001). Key reliability-related programs of the total quality management
system are: (1) design rule review and approval; (2) control of raw materials and vendor quality; (3)
manufacturing statistical process controls; (4) manufacturing identification of "Maverick Lot" yield
limits; (5) formal training and certification of manufacturing personnel; (6) qualification of new products
and manufacturing processes; (7) continuous reliability monitoring; (8) formal failure analysis and
corrective action; and (9) competitive benchmarking.
Product Reliability data is accumulated as a result of new product Qualification Test Plan activities
(Cypress Semiconductor Document Number 25-00040) as well as from the Reliability Monitor Program
(Cypress Semiconductor Document Number 25-00008). All reliability test samples are obtained from
standard production material. Sample selection is based on generic product families. These generic
products are designed with very similar design rules and manufactured from a core set of processes.
Reliability strategy requires that every failure that occurs during reliability testing be subjected to failure
analysis (Cypress Semiconductor Document Number 25-00039) to determine the failure mechanism.
Corrective action is then implemented to prevent future failures, resulting in continuous improvement
in product reliability.
Copies of the Cypress Semiconductor documents referenced herein are available through your
Cypress Semiconductor sales representative. Questions about product reliability may be addressed to
the undersigned.
____________________
Director of Reliability
___________________
Director of Quality
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134-1599
Cypress Quality Fax: (408) 943-2165
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QUALITY & RELIABILITY
CYPRESS
2.0 EARLY FAILURE RATE SUMMARY
Early Failure Rate Determination: High Temperature Operating Life testing (HTOL), for as long as 96
hours, is used to estimate device early failure rate.
Test:
Conditions:
Duration:
Failure:
Fit Rate:
High Temperature Operating Life Test (HTOL)
Dynamic Operating Conditions, VCC nominal + 15%, 150°C or 125°C.
48 hours HTOL at 150°C or 96 hours at 125°C.
A failure is any device that fails to meet data sheet electrical requirements.
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Early Failure Rate Summary
Technology
# Failed
B53
HYNIX 0.35
HYNIX P26
NEC 0.35
Promos .17
R28
R32
R42
Device
Hours
97951
7200
34573
122700
102068
253172
51200
190826
R52
R6
922456
192061
4
0
25
28
R7
3470434
7
12
R8
S4
TO15
TSMC 0.15
TSMC 0.18
TSMC 0.25
TSMC 0.50
464696
350474
72960
97200
58828
56021
327584
2
1
0
0
0
0
0
25
17
0
0
0
0
0
0
0
0
FIT Rate
21
28
Failure Mode
Insufficient data
Insufficient data
Insufficient data
Insufficient data
Insufficient data
None
Insufficient data
None
(1 unit) Scratched Metal Line
(3 units) Unknown Cause
None
(3 units) Unknown Cause
(2 units) Poly-Si Particles
(2 units) Poly Protrusions
(1 unit) Unknown Cause
(1 unit) Cracked ILD
(1 unit) Unknown Cause
Insufficient data
Insufficient data
Insufficient data
Insufficient data
16
Notes: Data reported is a 4-quarter rolling average.
Insufficient data – interpret as insufficient accumulated life-time hours to project a 60%
confidence bound for a zero-fails sample.
QUALITY & RELIABILITY
CYPRESS
3.0 LONG TERM FAILURE RATE SUMMARY
Long Term Failure Rate Determination A High Temperature Operating Life test (HTOL) is used to
estimate long-term reliability. By operating the devices at accelerated temperature and voltage,
hundreds of thousands of use hours can be compressed into hundreds of test hours.
Test:
High Temperature Operating Life Test (HTOL)
Conditions: Dynamic Operating Conditions, VCC nominal +15% 150°C or 125°C.
Duration: A minimum of 80 hours at 150°C or 168 hours at 125°C
Generally 500 hours at 150°C or 1000 hours at 125°C.
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Fit Rate:
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Long Term Failure Rate Summary
Technology
# Failed
FIT Rate
Failure Mode
B53
HYNIX 0.35
HYNIX P26
NEC 0.35
Promos .17
R28
R32
R42
R52
R6
Device
Hours
@150°c
256292
75000
138576
227316
195000
200000
263840
489655
1492994
525571
0
0
0
0
0
0
0
0
1
0
21
R7
3169505
2
4
R8
S4
TO15
TSMC 0.18
TSMC 0.25
TSMC 0.50
1355360
337212
182460
150086
24194
535500
6
0
0
0
0
0
26
16
30
36
None
Insufficient data
Insufficient data
None
None
None
None
None
(1 unit) Unknown Cause
None
(1 unit) Blocked Contact
(1 unit) Poly Protrusion
(2 units) Poly Protrusion
(4 units) Unknown Cause
None
None
None
Insufficient data
None
24
28
27
20
11
4
10
10
Notes: Data reported is a 4-quarter rolling average.
Insufficient data – interpret as insufficient accumulated life-time hours to project a 60%
confidence bound for a zero-fails sample.
QUALITY & RELIABILITY
CYPRESS
4.0 PRESSURE COOKER TEST (PCT)
The Pressure Cooker Test is a highly accelerated packaging stress test used to ensure environmental
durability of epoxy-packaged parts.
Passivation cracks, ionic contamination, and corrosion
susceptibility are all accelerated by this stress.
Test:
Conditions:
Pre-Conditioning:
Failure:
Pressure Cooker Test (PCT)
15 PSIG, 121°C, No bias, for a minimum of 168 hours.
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
A failure is any device that fails to meet data sheet electrical requirements.
Pressure Cooker Test Failure Rate Summary
Package
TQFP
TQFP (10x10)
VFBGA
FBGA (0.75)
FBGA (1.0)
PBGA (1.27)
PLCC
MLF
PQFP
PQFP (Thermal)
SSOP
PDIP
SOIC
SOJ
TSOP
TSOPI
TSOPII
TSOP (Reverse)
Sample
Size
1242
98
46
468
194
48
608
148
147
48
1258
882
1386
757
1002
138
273
98
# Failed
Defects %
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.1
0
0
0
0
0
0
0
Note: Data reported is a 4-quarter rolling average.
Failure Mode
None
None
None
None
None
None
None
None
None
None
(1 unit) Cut Wedge
None
None
None
None
None
None
None
QUALITY & RELIABILITY
CYPRESS
5.0 HIGHLY ACCELERATED STRESS TEST (HAST)
Cypress uses HAST to accelerate temperature, humidity, bias failure mechanisms. This change was
necessary because our package reliability had improved to the point where the old 85°C/85% R.H.
Temperature-humidity-bias testing would not induce failures. Failures are necessary to judge
progress and compare packaging changes. HAST testing has been shown to be at least twenty times
more accelerated then 85°C/85% R.H. temperature-humidity-bias testing.
Test:
Conditions:
Highly Accelerated Stress Test (HAST)
Present Conditions: 130°C / 85% RH minimum power dissipation, for a
minimum of 128 hours.
Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Highly Accelerated Stress Test (HAST) Failure Rate Summary
Package
TQFP
TQFP (10x10)
VFBGA
FBGA (0.75-0.8)
FBGA (1.0)
PLCC
MLF
PQFP
SSOP
PDIP
SOIC
SOJ
TSOP
TSOPI
TSOP (Reverse)
TSOP II
Sample
Size
831
131
42
468
94
369
100
45
455
50
1172
417
191
136
80
355
# Failed
Defects %
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0.3
Note: Data reported is a 4-quarter rolling average.
Failure Mode
None
(1 unit) Lifted Ball Bond
None
None
None
None
None
None
None
None
None
None
None
None
None
(1 unit) Cut Wedge &
Lifted Ball Bond.
QUALITY & RELIABILITY
CYPRESS
6.0 TEMPERATURE CYCLE TEST (TC)
Differences in thermal expansion coefficients are accentuated by cycling devices through temperature
extremes. If the materials do not expand and contract equally, large stresses can develop. The
Temperature Cycle test stresses mechanical integrity by exposing a device to alternating temperature
extremes. Weakness and thermal expansion mismatches in die interconnections, die attach, and wire
bonds are often detected with this acceleration test.
Test:
Condition:
Pre-Condition:
Duration:
Failure:
Temperature Cycle
MIL-STD -883D, Method 1010, Condition C, -65°C to 150°C.
JEDEC 22-A104 Condition B, -40°C to 125°C
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
300 cycles minimum at Condition C, 1000 cycles minimum at Condition B
A failure is any device that fails to meet data sheet electrical requirements.
Temperature Cycling Failure Rate Summary
Package
TQFP
TQFP (10X10)
VFBGA
FBGA (0.75-0.8)
FBGA (1.0)
PBGA (1.27)
PLCC
MLF
PQFP
PQFP (Thermal)
SSOP
PDIP
SOIC
SOJ
TSOP
TSOPI
TSOPII
TSOP (Reverse)
Sample
Size
1878
96
47
853
392
238
565
300
146
47
1522
908
1879
798
1755
245
591
96
# Failed
Defects %
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: Data reported is a 4-quarter rolling average.
Failure Mode
None
None
None
(4 units) Cut Wedge
None
None
None
None
None
None
None
None
None
None
None
None
None
None