Q3 - 2000

QUALITY & RELIABILITY
CYPRESS
2000 Q3 RELIABILITY REPORT
TABLE OF CONTENTS
1.0 OVERVIEW
OF
CYPRESS
MANAGEMENT SYSTEM
SEMICONDUCTOR
2.0 EARLY FAILURE RATE SUMMARY
2.1 Early Failure Rate Determination
3.0 LONG TERM FAILURE RATE SUMMARY
3.1 Long Term Failure Rate Determination
4.0 PROCESS ENVIRONMENTAL TESTS
4.1 Pressure Cooker Test (PCT)
4.2 Highly Accelerated Stress Test (HAST)
4.3 Temperature Cycle Test (TC)
Note: All the results reported here are for Quarter 3 2000.
TOTAL
QUALITY
CYPRESS
QUALITY & RELIABILITY
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM
This report summarizes Cypress Semiconductor Product Reliability for the 3rd quarter of 2000.
Cypress Semiconductor has established aggressive reliability objectives to assure that all products
exhibit reliability which exceeds customer reliability requirements for purchased components. In
addition, the quality standard at Cypress is zero defects which results in a
culture requiring continuous improvement in quality and reliability. This report includes data from
product fabricated at the San Jose, California; Round Rock, Texas; and Bloomington, Minnesota
facilities. Product reliability is assured by a total quality management system. The quality management
system is described in detail in the Cypress Semiconductor Quality Manual (Cypress Semiconductor
Document Number 90-00001). Key reliability-related programs of the total quality management
system are: (1) design rule review and approval; (2) control of raw materials and vendor quality; (3)
manufacturing statistical process controls; (4) manufacturing identification of "Maverick Lot" yield
limits; (5) formal training and certification of manufacturing personnel; (6) qualification of new products
and manufacturing processes; (7) continuous reliability monitoring; (8) formal failure analysis and
corrective action; and (9) competitive benchmarking. Product Reliability data is accumulated as a
result of new product Qualification Test Plan activities (Cypress Semiconductor Document
Number 25-00040) as well as from the Reliability Monitor Program (Cypress Semiconductor Document
Number 25-00008). All reliability test samples are obtained from standard production material. Sample
selection is based on generic product families. These generic products are designed with very similar
design rules and manufactured from a core set of processes. Reliability strategy requires that every
failure which occurs during reliability testing be subjected to failure analysis (Cypress Semiconductor
Document Number 25-00039) to determine the failure mechanism. Corrective action is then
implemented to prevent future failures. The result is continuous improvement in product reliability.
Copies of the Cypress Semiconductor documents referenced herein are available through your
Cypress Semiconductor sales representative. Questions about product reliability may be addressed to
the undersigned.
Director of Reliability
Director of Quality
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134-1599
Cypress Quality Fax: (408) 943-2165
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QUALITY & RELIABILITY
CYPRESS
2.0 EARLY FAILURE RATE SUMMARY
2.1 Early Failure Rate Determination High Temperature Operating Life testing (HTOL), for as long as
96 hours, is used to estimate device early failure rate.
Test:
High Temperature Operating Life Test (HTOL)
Conditions:
Dynamic Operating Conditions, VCC up to VCC,
nominal + 15%, 150°C or 125°C.
Duration:
Early Failure Rate samples are tested between 48 hours
HTOL at 150°C (EFR) or 96 hours at 125°C (EFR2).
Failure:
A failure is any device that fails to meet data sheet
electrical requirements.
Fit Rate:
Derated to 55 c ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Early Failure Rate Summary
Technology
Device
Hours
91655
343994
692400
# Failed
FIT Rate
0
0
1
58.8
15.7
8.5
Ram 3
Ram 4
246000
3655646
0
5
21.9
8
Ram 5
3896543
10
15.1
0
30.1
HYNIX P26
P26
Ram 2
TSMC L28
178944
Failure
Mode
None
None
Cause not
known
None
Ploy defects,
ISB failure
Poly particle
defect, Single
bit
None
Note: Data reported is a 4 quarter rolling average.
3.0 LONG TERM FAILURE RATE SUMMARY
3.1 Long Term Failure Rate Determination
A High Temperature Operating Life test (HTOL) is used to estimate long term reliability. By operating
the devices at accelerated temperature and voltage, hundreds of thousands of use hours can be
compressed into hundreds of test hours.
Test:
High Temperature Operating Life Test (HTOL)
Conditions: Dynamic Operating Conditions, VCC up to VCC,
nominal +15% 150°C or 125°C
Duration: A minimum of 80 hours at 150°C or 168 hours at 125°C. Tested to
500 hours at 150°C or 1000 hours at 125°C.
Failure:
A failure is any device that fails to meet data sheet
electrical requirements.
Fit Rate:
Derated to 55 c ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Long Term Failure Rate Summary
Technology
CMOS
Device
Hours
@150°C
115000
# Failed
FIT Rate
Failure Mode
0
46.7
None
QUALITY & RELIABILITY
CYPRESS
FL28
HYNIX 0.35
HYNIX P26
P20
P26
Ram 2
Ram 3
Ram 4
Ram 5
231296
59478
258480
154300
128471
1223276
918924
2346062
3001919
0
0
0
0
0
2
2
2
11
23.3
90.6
20.9
34.9
42
10.5
12.8
5.0
13.7
TSMC 0.5
TSMC L28
58320
171420
0
0
92.4
31.5
None
None
None
None
None
Cause not known
Cause not known
Timing
Particle contamination
and poly defects in fab
None
None
Note: Data reported is a 4 quarter rolling average.
4.0 PROCESS ENVIRONMENTAL TESTS
Cypress Semiconductor Reliability qualifies and continuously monitors packaging reliability to ensure
exceptional resistance to environmental stress. Package reliability stress testing and failure
rates are summarized in the following section.
4.1 Pressure Cooker Test (PCT)
Test:
Pressure Cooker Test (PCT)
Conditions:
15 PSIG, 121°C, No bias, for a minimum of 168 hours.
Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
Purpose:
The Pressure Cooker Test is a highly accelerated
packaging stress test used to ensure environmental durability
of epoxy packaged parts. Passivation cracks, ionic
contamination and corrosion susceptibility are all accelerated
by this stress.
Failure:
A failure is any device that fails to meet data sheet
electrical requirements.
Pressure Cooker Test Failure Rate Summary
Package
# Failed
TQFP
PPGA
Sample
Size
2311
848
Defects %
0
0
0
0
PLCC
2345
4
0.17
Corrosion
PQFP
PDIP
SSOP
SOIC
SOJ
TSOP
280
541
613
1598
1648
1146
0
0
0
3
0
0
0
0
0
0.18
0
0
None
None
None
Wedge cut
None
None
Note: Data reported is a 4 quarter rolling average.
Failure
Mode
None
None
QUALITY & RELIABILITY
CYPRESS
4.2 Highly Accelerated Stress Test (HAST)
Cypress uses HAST to accelerate temperature, humidity, bias failure mechanisms. This change was
necessary because our package reliability had improved to the point where the old 85°C/85% R.H.
temperature-humidity-bias testing would not induce failures. Failures are necessary to judge progress
and compare packaging changes. HAST testing has been shown to be at least twenty times more
accelerated then 85°C/85% R.H. temperature-humidity-bias testing.
Test:
Conditions:
Highly Accelerated Stress Test (HAST)
Present Conditions: 130°C / 85% RH minimum power dissipation, for a
minimum of 128 hours.
Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
Purpose:
HAST is an accelerated biased humidity test that provides an acceleration of
at least 20 over 85°C/85% R.H. temperature-humidity bias testing. This test
provides rapid feedback regarding the quality of the epoxy package process.
Failure:
A failure is any device that fails to meet data sheet
electrical requirements.
Highly Accelerated Stress Test (HAST) Failure Rate Summary
Package
TQFP
PPGA
PLCC
PQFP
SSOP
SOIC
SOJ
TSOP
Sample
Size
1380
775
1201
135
526
1195
1383
808
# Failed
Defects %
0
0
0
0
0
3
1
0
0
0
0
0
0
0.25
0.07
0
Failure
Mode
None
None
None
None
None
Lifted balls
Lifted balls
None
Note: Data reported is a 4 quarter rolling average.
4.3 Temperature Cycle Test (TC)
Differences in thermal expansion coefficients are accentuated by cycling devices through temperature
extremes. If the materials do not expand and contract equally, large stresses can develop.
Test:
Condition:
Pre-Condition:
Purpose:
Duration:
Failure:
Temperature Cycle
MIL-STD-883D, Method 1010, Condition C, -65°C to 150°C.
JEDEC 22-A104 Condition B, -40°C to 125°C
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
The Temperature Cycle test stresses mechanical integrity by exposing a
device to alternating temperature extremes. Weakness and thermal
expansion mismatches in die interconnections, die attach, and wire bonds are
often detected with this acceleration test.
300 cycles minimum at Condition C and 1000 cycles minimum at Condition B
A failure is any device that fails to meet data sheet electrical requirements.
Temperature Cycling Failure Rate Summary
Package
TQFP
PPGA
Sample
Size
2927
2099
# Failed
3
0
Defects %
0.10
0
Failure
Mode
Cracks
None
QUALITY & RELIABILITY
CYPRESS
PLCC
PDIP
2072
409
0
1
0
0.24
PQFP
SSOP
SOIC
SOJ
TSOP
374
902
1778
2338
1627
0
0
0
0
0
0
0
0
0
0
Note: Data reported is a 4 quarter rolling average.
None
Top side
crack
None
None
None
None
None