INTEGRATED CIRCUITS DATA SHEET SAA1101 Universal sync generator (USG) Product specification File under Integrated Circuits, IC02 January 1990 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 FEATURES • Programmable to seven standards • Additional outputs to simplify signal processing • Can be synchronized to an external sync. signal • Option to select the 524/624 line mode instead of the 525/625 line mode • Lock from subcarrier to line frequency GENERAL DESCRIPTION The SAA1101 is a Universal Sync Generator (USG) and is designed for application in video sources such as cameras, film scanners, video generators and associated apparatus. The circuit can be considered as a successor to the SAA1043 sync generator and the SAA1044 subcarrier coupling IC. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage range (pin 28) 4.5 5.5 V IDD quiescent supply current − 10 µA fOSC clock oscillator frequency − 24 MHz ORDERING AND PACKAGE INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE SAA1101P 28 DIL plastic SOT117 (1) SAA1101T 28 SO28 plastic SOT136A (2) Notes 1. SOT117-1; 1996 December 02. 2. SOT136-1; 1996 December 02. January 1990 2 January 1990 3 FSO 2 1 27 26 25 6 24 14 VSS VDD SUBCARRIER SUBTRACTION 28 fs ∆f STANDARD PROGRAMMED DIVIDER 160fH fs − ∆f 2fH HRI PH 8 PHASE DETECTION LOCK MODE SELECTION Href fH VERTICAL LOCK ADDITION/ SUPPRESSION LOGIC 23 NORM fH 10 LM1 LM0 9 HORIZONTAL DETECTION VERTICAL DETECTION RESET PULSE SHAPER VERTICAL DIVIDER SAA1101 11 7 12 19 20 21 22 15 16 17 18 MGH191 COMBINING LOGIC 13 SI ECS VLE RR CLP WMP VD HD ID BK CB CS Universal sync generator (USG) Fig.1 Block diagram. SUBCARRIER DIVIDER 40fH LINE DIVIDER k, full pagewidth FSI Z Y X OSCO OSCI 5 3 PRESCALER 4 CS0 CS1 CLO Philips Semiconductors Product specification SAA1101 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 PINNING SYMBOL PIN fpage DESCRIPTION 28 VDD FSI 1 subcarrier oscillator input, where fmax = 5 MHz FSO 2 27 Z FSO 2 subcarrier oscillator output CS1 3 26 Y CS1 3 clock frequency selection - CMOS input CS0 4 clock frequency selection - CMOS input CS0 4 25 X OSCI 5 clock oscillator input, where fmax = 24 MHz 24 CLO OSCO 6 clock oscillator output 23 NORM VLE 7 vertical in-lock enable - CMOS input 22 HD PH 8 phase detector output - 3-state output 21 VD LM1 9 lock mode selection - CMOS input LM1 9 20 WMP LM0 10 lock mode selection - CMOS input LM0 10 19 CLP ECS 11 external composite sync. signal - CMOS Schmitt-trigger input ECS 11 18 CS RR 12 frame reset - CMOS Schmitt-trigger input RR 12 17 CB SI 13 SI 13 16 BK set identification, used to set the correct field sequence in PAL-mode. The correction (inversion of fH2) is done at the left-hand slope of the SI-pulse. Minimum pulse width is 800 ns. CMOS Schmitt-trigger input. VSS 14 ground ID 15 identification - push-pull output BK 16 burst key (PAL/NTSC), chroma-blanking (SECAM) push-pull output FSI 1 OSCI 5 OSCO 6 VLE 7 SAA1101 PH 8 VSS 14 15 ID MGH190 Fig.2 Pinning configuration; SOT117. CB 17 composite blanking - push-pull output FUNCTIONAL DESCRIPTION CS 18 composite sync. - push-pull output Generation of pulses CLP 19 clamp pulse - push-pull output Generation of standard pulses such as sync, blanking and burst for TV systems: PAL B/G, PALN, PALM, SECAM and NTSC. In addition a number of non-standard pulses have been supplied to simplify signal processing. These signals include horizontal drive, vertical drive, clamp pulse, identification etc. It is possible to select the 524/624 line mode instead of the 525/625 line mode for all the above TV systems for applications such as robotics, games and computers. WMP 20 white measurement pulse-3-state output VD 21 vertical drive pulse - push-pull output HD 22 horizontal drive pulse - push-pull output NORM 23 used with X, Y and Z to select TV system; NORM = 0, 625/525 line mode (standard); NORM = 1, 624/524 line mode - CMOS input CLO 24 clock output - push-pull output X 25 TV system selection input - CMOS input Y 26 TV system selection input - CMOS input Z 27 TV system selection input - CMOS input VDD 28 voltage supply January 1990 4 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 subcarrier input is, in this case, used as an external input for the horizontal reference, see Fig.3(d). Lock modes The USG offers four lock modes: • Lock from the subcarrier SELECTION OF LOCK MODE • Slow sync. lock, external Href Lock mode is selected using the inputs LM0 and LM1 as illustrated in the Table below. • Slow sync. lock, internal Href • Fast sync. lock, internal Href LOCK FROM SUBCARRIER LM0 Lock from subcarrier to the line frequency for the above mentioned TV systems is given below; the horizontal frequency (fH) = 15.625 kHz for 625 line systems and 15.734264 kHz for 525 line systems. SECAM (1 and 2) 282fH PALN 229.2516fH NTSC (1 and 2) 227.5fH PALM 227.25fH PAL B/G 283.7516fH These relationships are obtained by the use of a phase locked loop and the internal programmed divider chain, see Fig.3(a). LOCK TO AN EXTERNAL SIGNAL SOURCE The following methods can be used to lock to an external signal source: 1. Sync. lock slow; the line frequency is locked to an external signal. The line and frame information are extracted from the external sync. signal and used separately in the lock system. The line information is used in a phase-locked loop where external and internal line frequencies are compared by the same phase detector as is used for the subcarrier lock. The external frame information is compared with the internal frame in a slow lock system; mismatch of internal and external frames will result in the addition or suppression of one line depending on the direction of the fault. The maximum lock time for frame lock is 6.25 s, see Fig.3(b). 2. Sync. lock fast. A fast lock of frames is possible with a frame reset which is extracted out of the incoming external sync. signal, see Fig.3(c). 3. Sync. lock with external reference. Lock of an external sync. signal to the line frequency with an external line reference to make possible a shifted lock. The January 1990 5 LM1 SELECTION 0 0 lock to subcarrier 0 1 slow sync. lock external Href 1 0 slow sync. lock internal Href 1 1 fast sync. lock internal Href Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 The different lock modes are illustrated by the following figures: n × fH handbook, halfpage OSCO FSI LINE OSCILLATOR OSCI 6 5 8 1 SUBCARRIER OSCILLATOR n × fH handbook, halfpage LINE OSCILLATOR OSCO ECS PH OSCI 6 5 PH 8 11 SAA1101 SAA1101 FSO 2 10 10 9 LM0 9 LM0 LM1 LM1 logic 1 logic 0 logic 1 Fig.3 (a) Lock to subcarrier. handbook, halfpage n × fH LINE OSCILLATOR LINE OSCILLATOR OSCO ECS 5 8 11 HD τ OSCI 6 MGH195 Fig.3 (c) Fast sync lock, internal H ref n × fH handbook, halfpage logic 1 MGH193 FSI PH OSCO 22 6 OSCI 5 8 1 Href PH SAA1101 SAA1101 ECS 11 10 LM0 logic 0 10 9 LM0 LM1 logic 1 logic 0 MGH194 Fig.3 (b) Slow sync lock, internal Href January 1990 9 LM1 logic 1 MGH192 Fig.3 (d) Slow sync lock, external H ref 6 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 LOCK WITH HORIZONTAL AND VERTICAL SIGNALS (slow lock modes only) It is possible to use horizontal and vertical signals instead of composite sync signals. The connections in this situation are: the external horizontal signal is connected to the ECS input (pin 11) and the vertical signal to the RR input (pin 12). The HIGH time of the horizontal pulse must be less than 14.4 µs, otherwise it will be detected as being a vertical pulse and will corrupt the vertical slow lock system. Selection of Clock Frequency The clock frequency is selected using the CS0 and CS1 inputs as illustrated below. CS0 CS1 FREQUENCY 625 LINES 525 LINES UNITS 0 0 160fH 2.5 2.517482 MHz 0 1 160fH 5 5.034964 MHz 1 0 960fH 15 15.104893 MHz 1 1 1440fH 22.5 22.657340 MHz Where the horizontal frequency, fH = 15.625 kHz for 625 lines and 15.734264 kHz for 525 lines. Oscillators The subcarrier oscillator has FSI as its input and FSO as its output. It is always used as a crystal oscillator with a series resonance crystal with parallel load capacitor. The maximum frequency, fmax = 5 MHz and the load capacitor, CL = 10 < CL < 35 pF. The clock oscillator has OSCI as its input and OSCO as its output. It can be used with an LC oscillator or a series resonance crystal with parallel load capacitor (Fig.4). The maximum frequency, fmax = 24 MHz and the load capacitor, CL = 10 < CL < 35 pF. Selection of 625/525 (standard; interlaced mode) or 624/524 lines (non-interlaced mode) Selection is achieved using the NORM input. When NORM = 0, 625/525 (standard) lines are selected; when NORM = 1, 624/524 line are selected. Output Dimensions All push-pull outputs: standard output 2 mA. White measurement pulse, WMP: 3-state output 2 mA. Phase detector, PH: 3-state output 2 mA. January 1990 7 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 handbook, halfpage 39 pF OSCI 5 15 MHz SAA1101 500 kΩ 6 39 pF 1 kΩ OSCO MGH196 Fig.4 Crystal oscillator circuit. Selection of TV System Selection of the required TV system is achieved by the X, Y and Z inputs as illustrated by the following Table. SYSTEM X Y Z SECAM1 0 0 0 PALN 0 0 1 NTSC1 0 1 0 PALM 0 1 1 SECAM2 1 0 0 (with identifier) PAL B/G 1 0 1 NTSC2 1 1 0 (short blanking) LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER MIN. MAX. UNIT supply voltage −0.5 +7 VI input voltage −0.5 VDD + 0.5 II maximum input current − ±10 mA IO maximum output current − ±10 mA IDD maximum supply current in VDD − 25 mA Ptot maximum power dissipation − 400 mW Tstg storage temperature range −55 +150 °C VDD Note 1. Input voltage should not exceed 7 V. January 1990 8 V (1) V Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = −25 to +70 °C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage 4.5 − 5.5 V IDD supply current (quiescent) Tamb = 25 °C − − 10 µA input leakage current Tamb = 25 °C − − 100 nA Inputs ±II CMOS COMPATIBLE; X, Y, Z, NORM, CS0, CS1, LM0, LM1 AND VLE VIH input voltage HIGH 0.7VDD − − V VIL input voltage LOW − − 0.3VDD V SCHMITT TRIGGER INPUTS; ECS, RR AND SI VT+ positive-going threshold − 2.5 4 V VT− negative-going threshold 1 1.5 − V VH hysteresis 0.4 1 − V OSCILLATOR INPUTS; OSCI AND FSI VIH input voltage HIGH 0.7VDD − − V VIL input voltage LOW − − 0.3VDD V Outputs PUSH-PULL OUTPUTS; CB, CS, BK, ID, HD, VD, CLP AND CLO VOH output voltage HIGH −IO = 2 mA; VDD = 5 V 4.5 − − V VOL output voltage LOW IO = 2 mA; VDD = 5 V − − 0.5 V OSCILLATOR OUTPUTS; OSCO AND FSO VOH output voltage HIGH −IO = 0.75 mA; VDD = 5 V 4.5 − − V VOL output voltage LOW IO = 0.75 mA; VDD = 5 V − − 0.5 V 3-STATE OUTPUTS; WMP AND PH VOH output voltage HIGH −IO = 2 mA; VDD = 5V 4.5 − − V VOL output voltage LOW IO = 2 mA; V DD = 5V − − 0.5 V ±IOZ OFF-state current Tamb = 25 °C − − 50 nA January 1990 9 January 1990 10 2nd half picture ID Fig.5 MGH198 Typical output waveforms for PAL/CCIR and SECAM. In the 624-line mode the output waveforms are identical to the first half picture of PAL/CCIR and are not interlaced. 9H(1) 10H 25H + tWCB Universal sync generator (USG) (1) H = 1 horizontal scan. 1st half picture ID 1st half picture BK 2nd half picture 4th half picture BK BK 3rd half picture 2nd half picture BK BK 1st half picture BK VD 2nd half CB picture tWCB start half picture full pagewidth SECAM−1 CCIR/PAL 2nd half picture 1st half CB picture CS 1st half CS picture Philips Semiconductors Product specification SAA1101 OUTPUT WAVEFORMS The output waveforms for the different modes of operation are illustrated by Figs 5 and 6. 1st half picture CS 2nd half picture CB 1st half picture tWCB 21H + tWCB NTSC 1 (2) 2nd half CB picture VD 6H BK 1st half picture BK 2nd half picture BK 1st half picture BK 2nd half picture BK 3rd half picture BK 4th half picture CB 1st half picture CB 2nd half picture NTSC 1 + 2 (2) 9H Philips Semiconductors Universal sync generator (USG) ull pagewidth January 1990 start half picture CS 11H(1) 11 PAL−M NTSC 2 (2) 19H + tWCB MGH197 Typical output waveforms for NTSC and PAL-M. In the 524-line mode the output waveforms are identical to the first half picture of NTSC and are not interlaced. Product specification Fig.6 SAA1101 (1) H = 1 horizontal scan. (2) NTSC mode reset; the fourth half picture is identical to the second half picture for NTSC. Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 WAVEFORM TIMING The waveform timing depends on the frequency of the oscillator input (fOSCI). This is illustrated in the table below as the number (N) of oscillations at OSCI. The timings are derived from N × tOSCI ± 100 ns. One horizontal scan (H) = 320 × tOSCI =1/fH. Where tOSCI = 200 ns for PAL/SECAM and 198.6 ns for NTSC/PAL-M SYMBOL PARAMETER PAL NTSC PAL-M SECAM UNIT N Composite sync (CS) tWSC1 horizontal sync pulse width 4.8 4.77 4.77 4.8 µs 24 tWSC2 equalizing pulse width 2.4 2.38 2.38 2.4 µs 12 tWSC3 serration pulse width 4.8 4.77 4.77 4.8 µs 24 − duration of pre-equalizing pulses 2.5 3 3 2.5 H − − duration of post-equalizing pulses 2.5 3 3 2.5 H − − duration of serration pulses 2.5 3 3.5 2.5 H − Composite blanking (CB) HORIZONTAL BLANKING PULSE WIDTH tWCB PAL/SECAM/PAL-M 12 − 11.12 12 µs 60 tWCB NTSC1 − 11.12 − − µs 56 tWCB NTSC2 − 10.53 (note1) − − µs 53 1.6 1.59 1.59 1.6 µs 8 FRONT PORCH tPCBCS front porch DURATION OF VERTICAL BLANKING − PAL/SECAM/PAL-M 25H + tWCB − 21H + tWCB 25H + tWCB − − − NTSC1 − 21H + tWCB − − − − − NTSC2 − 19H + tWCB − − − − Burst key (BK) (not SECAM) tWBK burst key pulse width 2.4 2.38 2.38 − µs 12 tPCSBK CS to burst key delay 5.6 5.56 5.76 − µs 28 − burst suppression 9 11 − H − H523 to H6 H523 to H8 − − − 9 POSITION OF BURST SUPPRESSION − first half picture − second half picture H310 to H318 H261 to H269 H260 to H270 − − − − third half picture H622 to H5 H523 to H6 H522 to H7 − − − − fourth half picture H311 to H319 H261 to H269 H259 to H269 − − − January 1990 H623 to H6 12 Philips Semiconductors Product specification Universal sync generator (USG) SYMBOL PARAMETER SAA1101 PAL NTSC PAL-M SECAM UNIT N Burst key (BK) (SECAM) tWBK chroma pulse width − − − 7.2 µs 36 tPBKCS CS to chroma delay − − − 1.6 µs 8 DURATION OF VERTICAL BLANKING − SECAM1 − − − note 2 − − − SECAM2 − − − note 3 − − Clamp pulse (CLP) tWCLP clamp pulse width 2.4 2.38 2.38 2.4 µs 12 tPCSCLP CS to CLP delay 1.6 1.59 1.59 1.6 µs 8 Horizontal drive (HD) tWHD pulse width 7.2 7.15 7.15 7.2 µs 36 tPHDCS CS to HD delay 0.8 0.79 0.79 0.8 µs 4 − repetition period 64 63.56 63.56 64 µs − Vertical drive (VD) − VD duration 10 6 6 10 H − tPVDCS CS to VD delay 1.6 1.59 1.59 1.6 µs 8 White measurement pulse (WMP) − pulse width 2.4 2.38 2.38 2.4 µs 12 − CS to WMP delay 34.4 34.16 34.16 34.4 µs 172 − duration of WMP 10 9 9 10 H − POSITION OF WMP − first half picture H163 to H173 H134 to H143 H134 to H143 H163 to H173 − − − second half picture H475 to H485 H396 to H405 H396 to H405 H475 to H485 − − Identification (ID) tWID pulse width 12 11.12 11.12 12 µs 60 tPIDCS CS to ID delay 1.6 1.59 1.59 1.6 µs 8 POSITION OF ID − first half picture H7 to H15 H8 to H22 H8 to H22 H7 to H15 − − − second half picture H320 to H328 H271 to H285 H271 to H285 H320 to H328 − − Notes to the characteristics 1. Horizontal blanking pulse width for NTSC2 can be 11.12 µs maximum 2. SECAM1, first half picture: 25H + tWBK except H320 to H328. Second half picture: 24.5H + tWBK except H7 to H15. 3. SECAM2, first half picture: 25H + tWBK. Second half picture: 24.5H + tWBK. January 1990 13 Philips Semiconductors Product specification Universal sync generator (USG) handbook, full pagewidth composite sync horizontal sync pulse CS CB t WSC1 t WSC2 equalizing pulse serration pulse composite blanking SAA1101 t WSC3 horizontal blanking pulse t WCB t PCBS2 t PCBSK burst key (PAL) burst key/ chrominance BK blanking HD (SECAM) chrominance blanking t WBK t WBK t PBKCS horizontal drive t WHD t PHDCS CLP clamp pulse ID SECAM identification VD start, stop vertical drives t WCPL t PCSCLP t WID t PIDCS t PVDCS MLA029 Fig.7 Waveform timing. January 1990 14 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 PACKAGE OUTLINES seating plane handbook, full pagewidthdual in-line package; 28 leads (600 mil) DIP28: plastic SOT117-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 15 28 pin 1 index E 1 14 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4.0 1.7 1.3 0.53 0.38 0.32 0.23 36.0 35.0 14.1 13.7 2.54 15.24 3.9 3.4 15.80 15.24 17.15 15.90 0.25 1.7 inches 0.20 0.020 0.16 0.066 0.051 0.020 0.014 0.013 0.009 1.41 1.34 0.56 0.54 0.10 0.60 0.15 0.13 0.62 0.60 0.68 0.63 0.01 0.067 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT117-1 051G05 MO-015AH January 1990 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-14 15 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.419 0.043 0.050 0.055 0.394 0.016 inches 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013AE January 1990 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 16 o 8 0o Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. January 1990 17 Philips Semiconductors Product specification Universal sync generator (USG) SAA1101 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1990 18