TOSHIBA TA1270BFG

TA1270BFG
TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA1270BFG
PAL / NTSC VIDEO CHROMA AND
SYNC PROCESSING SYSTEM FOR PIP / POP / PAP
TA1270BFG is a PAL / NTSC color TV signal processor IC
suitable for PIP / POP / PAP. The IC integrates video, chroma and
sync processor circuits. It comes in a 48pin flat package.
The video block uses a chroma trap, the chroma block a PAL /
NTSC automatic identifier circuit, and the sync processor block a
50 / 60 Hz automatic identifier circuit. The PAL demodulator
circuit contains a baseband signal processor, making the circuit
adjustment free.
The TA1270BFG incorporates an I2C bus, enabling control to be
set via the bus line.
FEATURES
Video block
Weight: 0.83 g (Typ.)
Chroma trap
Y delay line
Sub contrast adjustment (±3 dB)
CHROMA block
UV / CbCr demodulation for NTSC ; UV demodulation for PAL
Tint control
PAL demodulation baseband signal processing
PAL / NTSC automatic identification
Sub color adjustment (±3 dB)
Sync processor block
High-performance sync separator circuit
Adjustment-free horizontal and vertical oscillator circuit using count down method
50 / 60 Hz automatic identifier circuit
Switch block
High-speed switcher circuit
YUV or RGB input
Built-in RGB matrix circuit
YUV or RGB output
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TA1270BFG
BLOCK DIAGRAM
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TA1270BFG
PIN FUNCTION
PIN
No.
PIN NAME
FUNCTION
INTERFACE
INPUT / OUTPUT
SIGNAL
1
2
3
X’tal-1
X’tal-2
X’tal-3
Connect crystal. Serial capacitance
can vary oscillator frequency f0 ;
parallel capacitance can vary
oscillator adjustment range.
DC 4.0 V
90 mVp-p
4
APC filter
Connect APC filter for CHROMA
demodulation.
The voltage of this pin determines
the VCXO oscillator frequency.
DC
5
C GND
CHROMA processor GND pin
6
CHROMA input
CHROMA input pin. Input CHROMA
signal after Y / C separation.
―
―
1.8 V
7
V-SEP
Connect vertical sync separation
filter.
DC 6.4 V
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TA1270BFG
PIN
No.
8
PIN NAME
Sync input
FUNCTION
INTERFACE
INPUT / OUTPUT
SIGNAL
Sync separator circuit input pin. Input
via the clamp capacitor.
2.5 V
9
Sync output
Outputs sync signal separated using
the sync separator circuit. Open
collector output.
Connect a pull-up resistor.
10
AFC filter
Connect a horizontal AFC filter.
The voltage of this pin determines
the horizontal output frequency.
11
SYNC GND
Sync processor GND pin
32 fH VCO
Connect a ceramic oscillator for
horizontal oscillation.
Use a CSBLA503KECZF30 oscillator
manufactured by Murata Mfg Co.,
Ltd.
12
DC
―
4
―
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TA1270BFG
PIN
No.
PIN NAME
FUNCTION
INTERFACE
13
VP output
Vertical pulse output pin
14
HD output
Outputs HD pulse processed by the
AFC. HD output phase or pulse width
can be changed by bus setting.
SCP output
Outputs sand castle pulse (SCP).
The output signals are clamp pulse,
horizontal blanking pulse, and
vertical blanking pulse.
The minimum load resistance is
3 kΩ.
15
16
Dig GND
Logic block GND pin
17
CP / HP input
Input pin for CP / HP pulse used to
operate the SW circuit.
CP is used as clamp pulse ; HP as
blanking pulse.
18
19
SYNC VCC
SW VCC
VCC pins for sync processor block
and SW block.
Connect 9 V (Typ.).
INPUT / OUTPUT
SIGNAL
7.9 V
4.3 V
2.5 V
5
―
―
―
―
2005-08-18
TA1270BFG
PIN
No.
PIN NAME
20
21
22
Y / G output
B-Y / B output
R-Y / R output
FUNCTION
INTERFACE
Output Y / B-Y / R-Y or R / G / B.
YUV / RGB output is switched by bus
setting.
Pin used to switch slave addresses.
23
2CH
―― 0.7 V
24H
―― GND
ADRS SW
GND
VCC
―
―
24H,
2CH
24
SW GND
Switch block GND pin
25
26
27
Y2 input
B-Y2 input
R-Y2 input
(YUV2)
Y2 / B-Y2 / R-Y2 (YUV2 input) or R2
/ G2 / B2 input pin. Input via
capacitor used for clamp operation.
28
I C GND
I C block GND pin
29
30
31
Y1 input
B-Y1 input
R-Y1 input
(YUV1)
Y1 / B-Y1 / R-Y1 (YUV1 input) or R1
/ G1 / B1 input pin. Input via
capacitor used for clamp operation.
32
Ys
High-speed switch for switching input
pins 25, 26, and 27 (YUV2) and input
pins 29, 30, and 31 (YUV1).
The threshold is 0.7 V.
2
INPUT / OUTPUT
SIGNAL
2
―
―
―
―
Same as those for pins 25, 26 and 27
6
YUV1
―― 0.7 V
YUV2
―― GND
2005-08-18
TA1270BFG
PIN
No.
PIN NAME
FUNCTION
INTERFACE
2
INPUT / OUTPUT
SIGNAL
33
SCL
I C Bus SCL pin
34
SDA
I C Bus SDA pin
―
35
DAC TEST
DAC monitor pin for IC shipping
inspection.
―
36
GND
GND pin
37
Y output
Outputs Y signal which passed fsc
trap (trap is set on or off by Bus) and
Y delay line circuit.
38
39
DAC2
DAC1
1 bit DAC output pins
―
2
―
―
―
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TA1270BFG
PIN
No.
PIN NAME
FUNCTION
40
Y input
Composite video signal or Y signal
input pin. Input via the clamp
capacitor.
41
42
43
INTERFACE
2.4 V
DAC VCC
C VCC
VCC pins for DAC block and
CHROMA processing block. Connect
5 V (Typ.).
UV / CbCr SW
UV / CbCr demodulation switch.
OPEN ―― UV
GND ―― CbCr
45
―
―
UV
―― 0.7 V
CbCr
―― 0
CbCr demodulation is effective for
NTSC only.
44
INPUT / OUTPUT
SIGNAL
fsc output
Outputs crystal oscillator fsc.
The pin voltage goes high only when
3.58NTSC is received.
1HDL CONT
Outputs PAL / SECAM / NTSC
identification result.
Adjust to DC and connect output to
1H DL IC.
AC ; 0.6 Vp-p
DC ;
3.58NTSC
―――3.2 V
OTHERS
―――1.6 V
4.3 V ; PAL
2.5 V ; SECAM
0 V ; NTSC
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TA1270BFG
PIN
No.
46
47
48
PIN NAME
SECAM CONT
FUNCTION
INTERFACE
I / O pin used to control SECAM
demodulator IC.
If 250 µA or more flows from this pin,
SECAM is determined.
B-Y / Cb output
Outputs B-Y (U) signal or Cb signal.
Incorporates LPF to reject carrier.
R-Y / Cr output
Outputs R-Y (V) signal or Cr signal.
Incorporates LPF to reject carrier.
Pulling up the pin with 10 kΩ
monitors CHROMA signal after ACC
and TOF circuits (before demo
input).
INPUT / OUTPUT
SIGNAL
At PAL /
NTSC : 3.7 V
At SECAM
(Black and white) :
0.7 V
Pedestal level: 2.4 V
R-Y output
Pedestal level: 2.7 V
Cr output
Pedestal level: 2.5 V
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TA1270BFG
BUS CONTROL MAP
Write data
Slave address : 24H (00100100) pin 23-GND or 2CH (00101100) pin 23-VCC
SUB
ADDRESS
D7
MSB
D6
D5
00
D4
D3
D2
D0
LSB
D1
TINT
01
TOF-f0
TOF-Q
02
SUB CONTRAST
03
SUB COLOR
04
C-TRAP
Y BLACK LEVEL ADJ.
SW-OFT
05
R-Y BLACK LEVEL ADJ.
06
B-Y BLACK LEVEL ADJ.
POWER-ON
INITIAL VALUE
MSB
LSB
DAC1
1000
0000
Y-DL
P / N-ID
1000
0000
HD-PHS
DAC2
1000
0000
COLOR SYSTEM
1000
0000
V-FREQ / AFC-G
1000
0000
GP-PHS
1000
0000
1000
0000
Y-OFST
OUTPUT MODE
Read data
Slave address : 25H (00100101) pin 23-GND or 2DH (00101101) pin 23-VCC
D7
D6
D5
D4
D3
D2
D1
D0
0
PORET
COLOR SYSTEM
X’tal
V-FREQ
V-STD
H-LOCK
1
1
COLOR SYSTEM
X’tal
N-DET
U2 / V2-IN
Y2-IN
BUS CONTROL FUNCTION
Write function
PARAMETER
POWER-ON
INITIAL VALUE
DESCRIPTION
TINT
Adjusts hue. −32°~+32°
0°
DAC1 / 2
Controls 1 bit DAC. 0 : LOW, 1 : HIGH
TOF-f0
Switches TOF peak frequency.
(000) : TOF OFF, (001) : 0.8 fsc, (111) : 1.5 fsc
LOW
(100)
CENTER
TOF-Q
Switches TOF Q ; (000) : 0.6~(111) : 1.2
MIN
Y-DL
Switches Y-DL delay time ; (0) : OFF, (1) : ON (+80 ns)
OFF
P / N ID
Switches PAL / NTSC identification sensitivity.
(0) : LOW (Digital comb filter in use), (1) : Normal
LOW
SUB CONTRAST
Adjusts sub contrast ; −3.0 dB~+3.0 dB
0dB
C-TRAP
Switches CHROMA trap ; (0) : OFF, (1) : ON
OFF
HD-PHS
Switches HD output pulse phase
; (0) : PHASE-1, (1) : PHASE-2 (SCP)
SUB COLOR
Sub color ; −5.3 dB~0 dB~+3.0 dB
PHASE-1
0dB
Switches color system.
COLOR SYSTEM
(000) : AUTO
(001) : 3NTSC
(010) : 4NTSC
(011) : PAL
(100) : M-PAL
(101) : N-PAL
(101) : N-PAL
(110) : SECAM
(111) : TRINORMA
Y BLACK LEVEL ADJ.
Adjusts Y black level ; −75 mV~+65 mV
SW-OFT
Switches SW output offset ; Y : −10 IRE & UV : +60 mV
ON / OFF
(0) : OFF, (1) : ON
10
(000)
AUTO
(1000)
OFF
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TA1270BFG
PARAMETER
POWER-ON
INITIAL VALUE
DESCRIPTION
Controls vertical frequency and horizontal free run.
(000)
V-FREQ / AFC-G
V FREQUENCY
AFC-Gain
V pull-in range
AUTO1
(50 / 60 Hz MODE)
Normal
224.5H~353H
(001)
60 Hz MODE
Normal
224.5H~297H
(010)
262.5H forced
Free run
―
(011)
312.5H forced
Free run
―
(100)
AUTO2
(50 / 60 Hz MODE)
Normal
32.5H~353H
(101)
60 Hz mode
Normal
32.5H~297H
(110)
262H forced
Free run
―
(111)
312H forced
Free run
―
B-Y / R-Y
BLACK LEVEL ADJ.
Adjusts B-Y / R-Y black level ; −68 mV~+68 mV
GP-PHS
Switches gate pulse phase ; (0) : Normal , (1) : −200 ns (Ahead)
Y-OFST
Switches Y output offset ; +10 IRE : ON / OFF
(0) : OFF, (1) : ON
OUTPUT MODE
Switches SW output mode.
Switches YUV / RGB (matrix coefficient) output.
(00) : Y / U / V, (01) : RGB / PAL, (10) : RGB / NTSC1,
(11) : RGB / NTSC2
(000)
AUTO1
(100000)
CENTER
Normal
OFF
(00)
Y/U/V
HD-PHS
(0) : PHASE-1
(1) : PHASE-2 (SCP)
Read function
PARAMETER
DESCRIPTION
PORSET
Power-on reset.
(0) : RESISTER PRESET, (1) NORMAL
COLOR SYSTEM
Color system. Received system (ID, no ID)
(00) : B / W, (01) : SECAM, (10) : PAL, (11) : NTSC
X’tal
X’tal mode
(00) : −, (01) : 4.43 (N), (10) : M, (11) : 3.58
V-FREQ
Vertical frequency ; (0) : 50 Hz, (1) : 60 Hz
V-STD
Decides vertical standard ;
(0) : STANDARD, (1) : NON-STANDARD
H-LOCK
Decides horizontal lock ; (0) : LOCK, (1) : UN-LOCK
N-DET
Decides noise level ; (0) : Low, (1) : High
Y2-IN, U2 / V2-IN
Outputs self diagnosis result. ; (0) : NG, (1) : OK
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TA1270BFG
2
I C BUS COMMUNICATION AND RECEPTION METHODS
Slave address : Slave addresses can be changed using the pin 23 voltage.
24H (Pin 23-GND)
2CH (Pin 23-VCC)
A6
A5
A4
A3
A2
A1
A0
W/R
A6
A5
A4
A3
A2
A1
A0
W/R
0
0
1
0
0
1
0
0/1
0
0
1
0
1
1
0
0/1
Start and end conditions
Bit transmission
Acknowledgment
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TA1270BFG
Data transmit format 1
Data transmit format 2
Data receive format
At data reception, the master transmitter changes to the receiver immediately after the first
acknowledgment and the slave receiver changes to the transmitter.
The end condition is always generated by the master.
(* important ) The data read from THIS IC should always be completed in whole two words, not one word,
otherwise the IICBUS may cause error.
Option data transmit format
This transmission method automatically increments sub addresses starting from the specified sub address
and sets data.
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TA1270BFG
I2C BUS Conditions
Characteristics
Symbol
Min
Typ.
Max
Unit
Low level input voltage
VIL
0
⎯
1.5
V
High level input voltage
VIH
3.0
⎯
Vcc
V
VOL1
0
⎯
0.4
V
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Ii
−10
⎯
10
µA
Capacitance for each I/O pin
Ci
⎯
⎯
10
pF
Low level output voltage at 3 mA sink current
fSCL
0
⎯
100
kHz
tHD;STA
4.0
⎯
⎯
µs
Low period of SCL clock
tLOW
4.7
⎯
⎯
µs
High period of SCL clock
tHIGH
4.0
⎯
⎯
µs
SCL clock frequency
Hold time START condition
Set-up time for a repeated START condition
tSU;STA
4.7
⎯
⎯
µs
Data hold time
tHD;DAT
350
⎯
⎯
ns
Data set-up time
tSU;DAT
250
⎯
⎯
ns
Set-up time for STOP condition
tSU;STO
4.0
⎯
⎯
µs
tBUF
4.7
⎯
⎯
µs
Bus free time between a STOP and START condition
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TA1270BFG
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC
SYMBOL
RATING
UNIT
VCCmax
12
V
Input Pin Voltage
Vin
GND − 0.3 to VCC + 0.3
V
Power Dissipation
PD (Note 1)
844
mW
1 / θja
6.75
mW / °C
Operating Temperature
Topr
−20~65
°C
Storage Temperature
Tstg
−55~150
°C
Supply Voltage
Power Dissipation Reduction Rate
Note 1: See figure below.
Note 2: Since the device is susceptible to surge, handle with care.
Note 3: This IC is not proof enough against a strong E-M field by CRT which may cause function errors and / or poor
characteristics.
Keeping the distance from CRT to the IC longer than 20 cm, or if cannot, placing shield metal over the IC, is
recommended in an application.
Fig. Power dissipation temperature reduction curve
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TA1270BFG
OPERATING CONDITION
CHARACTERISTIC
Supply Voltage
Pin 40 Y Input Signal Level
Pin 6 Chroma Input Signal Level
Pin 8 Sync Signal Input level
CONDITION
MIN
TYP.
MAX
Pins 18, 19
8.5
9.0
9.5
Pins 41, 42
4.7
5.0
5.3
UNIT
V
White 100%. Including sync signal
0.9
1.0
1.1
TOF : OFF, burst level
200
300
400
TOF : ON, burst level
100
200
300
0.9
1.0
1.1
Vp-p
―
0.5
1.0
mA
White 100%. Including sync signal
Pin 9 Sink Current
―
Vp-p
mVp-p
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, Ta = 25°C ± 3°C)
Current dissipation
PIN No.
PIN NAME
SYMBOL
TEST
CIRCUIT
18
SYNC VCC
ICC1
―
19
SW VCC
ICC2
―
41
DAC VCC
ICC3
―
42
C VCC
ICC4
―
SYMBOL
MIN
TYP.
MAX
13
19
25
UNIT
mA
24
35
46
TEST
CIRCUIT
MIN
TYP.
MAX
PIN VOLTAGE
PIN No.
PIN NAME
1
4.43 MHz X’tal
V1
―
3.60
4.00
4.40
2
N-X’tal
V2
―
3.60
4.00
4.40
3
3.58 MHz X’tal
V3
―
3.60
4.00
4.40
6
C input
V6
―
1.30
1.75
2.20
7
V-SEP
V7
―
5.10
5.50
5.90
12
32 fH VCO
V12
―
5.30
5.70
6.10
20
Y / G output
V20
―
3.90
4.30
4.70
21
B-Y / B output
V21
―
3.90
4.30
4.70
22
R-Y / R output
V22
―
3.90
4.30
4.70
25
Y2 input
V25
―
5.30
5.70
6.10
26
B-Y2 input
V26
―
5.30
5.70
6.10
27
R-Y2 input
V27
―
5.30
5.70
6.10
29
Y1 input
V29
―
5.30
5.70
6.10
30
B-Y1 input
V30
―
5.30
5.70
6.10
31
R-Y1 input
V31
―
5.30
5.70
6.10
37
Y output
V37
―
1.60
2.00
2.40
40
Y input
V40
―
2.10
2.50
2.90
16
UNIT
V
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TA1270BFG
AC CHARACTERISTICS
Video block
CHARACTERISTIC
SYMBOL
TEST
CIRCUIT
VYI
―
GYs
―
GYt
―
GfY
―
GTC3
MIN
TYP.
MAX
UNIT
2.1
2.4
2.8
V
−0.13
0
0.13
−0.13
0
0.13
−3 dB
8
10
―
―
fO = 3.579545 MHz
―
−25
−13
GTC4
―
fO = 4.433619 MHz
―
−25
−13
Y Input Dynamic Range
VD
―
Sub contrast : min.
1.3
1.6
―
Y Input to Y Output
Transmission Characteristic 1
TYa
―
Black and white, Y-DL : OFF
255
295
335
TYb
―
Black and white, Y-DL : ON
335
375
415
TY3
―
3.58 NTSC, Y-DL : OFF
255
295
335
TY4
―
4.43 PAL, Y-DL : OFF
255
295
335
TYS
―
SECAM, Y-DL : OFF
445
495
535
∆VSU+
―
20 log
(Data max. / data center)
2.5
3.0
3.5
∆VSU−
―
20 log
(Data max. / data center)
−3.5
−3.0
−2.5
VYO
―
60
95
130
Y Input Clamp Voltage
Y Input to Y Output AC Gain
Y Input to Y Output Frequency
Bandwidth
TRAP Filter Characteristic
Y Input to Y Output
Transmission Characteristic 2
Sub Contrast Range
Y Output Offset Amount
TEST CONDITION
Y input-AC GND
(Note V1)
(Note V2)
17
dB
Vp-p
ns
dB
mV
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TA1270BFG
Chroma block
CHARACTERISTIC
ACC Characteristics
Sub Color Control
Characteristic
APC Frequency Control
Sensitivity
APC Pull-In Range
APC Hold Range
fsc Free-Run Frequency
fsc Output Amplitude
fsc Output DC Level
Color Difference Output
Level
Relative Amplitude
SYMBOL
TEST
CIRCUIT
F600
F300
F30
―
F10
―
170
245
290
A
―
0.95
1.00
1.05
es+
―
20 log
(Data max. / data center)
2.0
3.0
4.0
es−
―
20 log
(Data max. / data center)
−7.4
−5.3
−2.4
β3
―
0.5
1.65
2.2
β4
―
0.5
1.65
2.2
βM
―
0.5
1.65
2.2
f3ph
―
At 3.58 NTSC, upper side
250
600
2000
TEST CONDITION
MIN
TYP.
MAX
―
300
360
420
―
300
360
420
300
360
420
(Note C1)
f3pl
―
At 3.58 NTSC, lower side
−2000
−1400
−250
f4ph
―
At 4.43 PAL, upper side
250
600
2000
f4pl
―
At 4.43 PAL, lower side
−2000
−950
−250
fMph
―
At M-PAL, upper side
250
600
2000
fMpl
―
At M-PAL, lower side
−2000
−1100
−250
f3hh
―
At 3.58 NTSC, upper side
250
600
2000
f3hl
―
At 3.58 NTSC, lower side
−2000
−1400
−250
f4hh
―
At 4.43 PAL, upper side
250
600
2000
f4hl
―
At 4.43 PAL, lower side
−2000
−950
−250
fMhh
―
At M-PAL, upper side
250
600
2000
fMhl
―
At M-PAL, lower side
−2000
−1100
−250
fO3
―
fO = 3.579545 MHz
−200
0
200
fO4
―
fO = 4.433619 MHz
−200
0
200
fOM
―
fO = 3.575611 MHz
−200
0
200
f3c
―
At 3.58 NTSC input
0.45
0.75
0.95
f4c
―
At 4.43 PAL input
0.50
0.65
0.80
fMc
―
At M-PAL input
0.45
0.75
0.95
V44a
―
At 3.58 NTSC input
2.9
3.2
3.5
V44b
―
At other than 3.58 NTSC input
1.15
1.55
1.75
vRNUV
―
3.58 NTSC − UV mode,
B:C=1:1
300
360
420
280
340
400
215
272
320
280
340
400
vBNUV
―
vRNCbCr
―
vBNCbCr
―
vRP
―
380
440
―
4.43 PAL,
B:C=1:1
315
vBP
315
380
440
vR / BUV
―
3.58 NTSC − UV mode
0.94
1.00
1.15
vR / BCbCr
―
3.58 N − CbCr mode
0.94
1.00
1.15
vR / BPAL
―
4.43 PAL
0.94
1.00
1.15
18
mVp-p
―
dB
(Note C2)
3.58 N−CbCr mode,
B:C=1:1
UNIT
Hz / mV
Hz
Vp-p
V
mVp-p
―
2005-08-18
TA1270BFG
CHARACTERISTIC
Demodulation Angle
Color Difference Output Tint
Adjustment Characteristic
Residual Carrier Level
Residual Harmonic Level
1HDL CONT Output DC Level
Change
Sand Castle Pulse Wave High
Value
SECAM ID Output DC Level
NTSC Ident Sensitivity
PAL Ident Sensitivity
TOF Characteristic
SYMBOL
TEST
CIRCUIT
θBNUV
―
θRNUV
―
θBNCbCr
―
θRNCbCr
―
θBP
―
TEST CONDITION
3.58 NTSC − UV mode,
TINT ; center
3.58 N−CbCr mode,
TINT ; center
4.43 PAL
MIN
TYP.
MAX
0
3
8
90
93
96
0
3
8
90
93
96
−3.0
0
5.5
θRP
―
87
90
95
θUVMAX
―
UV Mode, TINT ; max.
29
32
35
θUVMIN
―
UV Mode, TINT ; min.
−35
−32
−29
θCbCrMAX
―
CbCr Mode, TINT ; max.
29
32
35
θCbCrMIN
―
CbCr Mode, TINT ; min.
−35
−32
−29
ve
―
fsc level
―
1.9
4.0
vHe
―
(fsc × 2) level
―
1.9
4.0
VDLP
―
PAL signal input
4.0
4.3
4.6
VDLS
―
SECAM signal input
2.2
2.5
2.8
VDLN
―
NTSC signal input
0
0.1
0.2
SCH
―
CP level
7.6
7.9
8.2
SCM
―
HP level
4.05
4.3
4.55
SCL
―
VP level
2.25
2.5
2.75
SEN
―
3.4
3.7
4.0
(Note C3)
SEP
―
3.4
3.7
4.0
SES
―
0.4
0.7
1.0
vNCL
―
2.0
2.9
4.0
vNCH
―
0.5
1.8
4.0
vNBL
―
1.7
2.7
5.8
vNBH
―
0.3
1.6
3.6
vPCL
―
1.5
4.5
6.5
vPCH
―
1.0
2.8
3.1
vPBL
―
1.5
4.1
6.1
vPBH
―
1.0
2.5
4.5
GFH3
―
14.0
16.5
19.0
GFC3
―
12.5
15.0
17.5
GFL3
―
10.5
13.0
15.5
GFH4
―
15.5
18.0
20.5
GFC4
―
14.0
16.5
19.0
GFL4
―
12.0
14.5
17.0
(Note C4)
(Note C5)
(Note C6)
19
UNIT
°
°
mVp-p
V
mVp-p
dB
2005-08-18
TA1270BFG
Switch block
CHARACTERISTIC
Y Gain (Through Mode)
Color Difference Gain
(Through Mode)
Y Gain (Matrix Mode)
Color Difference Gain
(Matrix Mode)
R-Y Relative Phase
R-Y Relative Amplitude
G-Y Relative Phase
G-Y Relative Amplitude
SYMBOL
TEST
CIRCUIT
GY1
―
GY2
―
GBY1
―
GRY1
―
GBY2
―
GRY2
TEST CONDITION
(Note S1)
MIN
TYP.
MAX
−1.0
0
1.0
−1.0
0
1.0
−1.0
0
1.0
−1.0
0
1.0
−1.0
0
1.0
―
−1.0
0
1.0
GY1GP
―
−1.0
0
1.0
GY1GN1
―
−1.0
0
1.0
GY1GN2
―
−1.0
0
1.0
GY1BP
―
−1.0
0
1.0
GY1BN1
―
−1.0
0
1.0
GY1BN2
―
−1.0
0
1.0
GY1RP
―
−1.0
0
1.0
GY1RN1
―
−1.0
0
1.0
GY1RN2
―
−1.0
0
1.0
GGYP
―
−0.6
0.6
1.6
GGYN1
―
−0.6
0.6
1.6
GGYN2
―
−1.0
0
1.0
GBYP
―
8.9
9.9
10.9
GBYN1
―
7.5
8.5
9.5
GBYN2
―
7.5
8.5
9.5
GRYP
―
3.9
4.9
5.9
GRYN1
―
5.6
6.6
7.6
(Note S2)
(Note S3)
(Note S4)
GRNY2
―
4.2
5.2
6.2
θRP
―
RGB / PAL Mode
87
90
93
θRN1
―
RGB / NTSC1 Mode
89
92
95
θRN2
―
RGB / NTSC2 Mode
93
96
99
vPR / B
―
RGB / PAL Mode
0.53
0.56
0.59
vN1R / B
―
RGB / NTSC1 Mode
0.77
0.80
0.83
vN2R / B
―
RGB / NTSC2 Mode
0.65
0.68
0.71
θGP
―
RGB / PAL Mode
234
237
240
θGN1
―
RGB / NTSC1 Mode
237
240
243
θGN2
―
RGB / NTSC2 Mode
237
240
243
vPG / B
―
RGB / PAL Mode
0.31
0.34
0.37
vN1G / B
―
RGB / NTSC1 Mode
0.37
0.40
0.43
vN2G / B
―
RGB / NTSC2 Mode
0.34
0.37
0.40
20
UNIT
dB
°
―
°
―
2005-08-18
TA1270BFG
CHARACTERISTIC
Switch Output Switch Offset
Switch Output Offset Amount
Y / G Output Black Level Range
B-Y / G Output Black Level
Range
R-Y / G Output Black Range
Smoothing Level
Switch Output Dynamic Range
Inter-Input Crosstalk
SYMBOL
TEST
CIRCUIT
TEST CONDITION
MIN
TYP.
MAX
∆VY
―
―
―
0
50
∆VB
―
―
―
0
50
―
∆VR
―
∆VYO
―
∆VBO
―
(Note S5)
―
0
50
−85
−75
−65
61
68
75
∆VRO
―
61
68
75
∆VYB+
―
59
65
71
∆VYB−
―
−82
−75
−68
∆VYO+
―
59
65
71
∆VYO−
―
−82
−75
−68
∆VBB+
―
61
68
75
∆VBB−
―
−75
−68
−61
∆VBO+
―
61
68
75
∆VBO−
―
−75
−68
−61
∆VRB+
―
61
68
75
−75
−68
−61
61
68
75
−75
−68
−61
4.0
4.3
4.6
4.0
4.3
4.6
4.0
4.3
4.6
∆VRB−
―
∆VRO+
―
∆VRO−
―
VYSM
―
(Note S6)
(Note S7)
(Note S8)
Blanking period voltage
VBSM
―
SRSM
―
DTH
―
Through mode
1.5
2.3
―
DMT
―
Matrix mode
0.9
1.2
―
GCR
―
Crosstalk between inputs
―
−50
−40
21
UNIT
mV
V
Vp-p
dB
2005-08-18
TA1270BFG
Sync processor block
CHARACTERISTIC
32 fH VCO Oscillation Start
Voltage
Horizontal Free-Run Frequency
Horizontal Oscillation
Frequency Range
Horizontal Oscillation
Frequency Control Sensitivity
Horizontal Sync Phase
SYMBOL
TEST
CIRCUIT
VVCO
―
Pin 18 voltage
f50HO
―
f60HO
TEST CONDITION
MIN
TYP.
MAX
UNIT
3.7
4.0
4.3
V
AUTO mode
15.455
15.625
15.795
―
60 Hz mode
15.564
15.734
15.904
fHmin
―
Pin 10 ; 10 kΩ−VCC
14.700
15.000
15.300
fHmax
―
Pin 10 ; 10 kΩ−GND
16.500
16.700
16.900
βH
―
2.3
2.8
3.3
Sph1
―
0.30
0.40
0.50
Sph2
―
0.11
0.21
0.31
―
(Note D1)
External Pulse Input Threshold
(Pin 17)
CPV17
―
Clamp pulse
3.2
3.5
3.8
HPV17
―
Horizontal blanking
0.7
1.0
1.3
Horizontal Blanking Start Phase
HPs
―
4.1
4.4
4.7
Horizontal Blanking Width
HPw
―
11.0
11.5
12.0
Gate Pulse Start Phase
GPs
―
2.8
3.0
3.2
Gate Pulse Width
GPw
―
1.8
2.0
2.2
Horizontal Blanking Pulse Start
Phase
HPs
―
3.8
4.0
4.2
Horizontal Blanking Pulse Width
HPw
―
9.5
10.0
10.5
HD Output Start Phase
HDs
―
−0.2
0
0.2
HD Output Pulse Width
HDw
―
1.6
1.8
2.0
HD Amplitude
Vertical Blanking Pulse Start
Phase
Vertical Blanking Pulse Width
Vertical Free-Run Frequency
Vertical Output Voltage
(Note D2)
(Note D3)
(Note D4)
(Note D5)
VHD
―
4.7
5.0
5.3
VP50s1
―
46
48
50
VP60s1
―
46
48
50
VP50s2
―
―
23
―
VP60s2
―
―
21
―
f50vo
―
AUTO mode (353H)
40
45
50
f60vo
―
60 Hz mode (297H)
48
53
58
Vvh
―
Pin 13 high voltage
4.7
5.0
5.3
Vvl
―
Pin 13 low voltage
―
0
0.3
(Note D6)
22
kHz
kHz / V
µs
V
µs
µs
V
µs
H
Hz
V
2005-08-18
TA1270BFG
CHARACTERISTIC
Vertical Output Pulse Width
Vertical Pull-In Range (1)
Vertical Pull-In Range (2)
Vertical Pull-In Range (3)
Vertical Pull-In Range (4)
Address Switch Threshold
Value
SYMBOL
TEST
CIRCUIT
Td
―
Tw
TEST CONDITION
MIN
TYP.
MAX
UNIT
42
44
46
µs
―
―
8
―
(Note D7)
fPL1
―
―
224.5
―
fPH1
―
―
353
―
fPL2
―
―
32.5
―
(Note D8)
fPH2
―
―
353
―
fPL3
―
―
224.5
―
fPH3
―
―
297
―
fPL4
―
―
32.5
―
fPH4
―
―
297
―
Vadd
―
0.5
0.65
0.8
Pin 23 voltage
23
H
V
2005-08-18
TA1270BFG
TEST METHODS (Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25°C ± 3°C)
Video block
NOTE
CHARACTERISTIC
00
TEST CONDITION
SUB ADDRESS & DATA
SW MODE
01
02
03
05
SW1
SW2 SW12
TEST METHOD
(1) Input signal 2 to Y input (Pin 40) and Yin2 input.
(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p)
V1
Y Input to Y Output AC Gain
80
80
80
or
84
80
80
B
A
A
(2) Change the sub address (02) data to TRAP-OFF (80h) and TRAP-ON
(84h) and perform the following :
(3) Measure the picture period amplitude (v37) of the Y output (Pin 37) and
determine the gain from Y input.
GYs, GYt = 20 log (v37 / 0.2)
(GYs ; TRAP-OFF, GYt ; TRAP-ON)
(1) Input signal 2 to Y input (Pin 40) and Yin2 input.
(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p)
V2
Y Output Offset Amount
80
0
80
80
80
or
81
B
A
A
(2) Set the sub address (01) data to 00 and measure the minimum potential
(VYO1) of the Y output (Pin 37) picture period amplitude.
(3) Set the sub address (05) data to Y-OFST-ON (81), measure the minimum
potential (VYO2) of the Y output picture period amplitude, and determine
the difference from VYO1.
VYO = VYO2 − VYO1
24
2005-08-18
TA1270BFG
Chroma block
NOTE
CHARACTERISTIC
00
TEST CONDITION
SUB ADDRESS & DATA
SW MODE
01
02
03
05
SW1
―
―
TEST METHOD
(1) Input 3.58-NTSC signal 1 rainbow signal (Burst : chroma = 1 : 1) to the
chroma input (Pin 6).
C1
ACC Characteristics
80
80
80
80
80
B
―
―
(2) Measure the amplitude, F10, F30, F300, and F600, of the B-Y output (Pin
47) when the amplitude of the chroma input signal is set to 10, 30, 300,
and 600 mVp-p.
(3) Calculate A = F30 / F300.
(1) Connect the chroma input pin (Pin 6) to GND via a capacitor.
80
C2
80
80
APC Frequency
Control Sensitivity
81
or
83
or
84
80
or
81
B
―
―
(2) Change the sub address (03) data to (81h), (83h), and (84h) and perform
the following for each.
(3) Connect external power source (V4) to the APC filter (Pin 4).
(4) Vary the voltage of external power source (V4) and measure the Fsc
output (Pin 44) using a frequency counter.
(5) Measure the free-run sensitivity β for the (V4 + 100 mV) near fsc.
(3.58NTSC ; β3, 4.43 ; PAL ; 4β ; M-PAL ; βM)
80
C3
80
80
SECAM ID Output DC Level
81
or
83
or
84
80
B
―
―
(1) Connect the chroma input pin (Pin 6) to GND via a capacitor.
(2) Change the sub address (03) data to (81h), (83h), and (84h) and
measure the output DC level of the SECAM ID (Pin 46).
3.58 NTSC mode (81h) ; SEN
4.43 PAL mode (83h)
; SEP
SECAM mode (84h)
; SES
(1) Input 3.58-NTSC signal 1 rainbow signal (Burst : chroma = 1 : 1) to the
chroma input (Pin 6).
80
C4
NTSC Ident Sensitivity
80
or
81
80
80
80
A
―
―
(2) While monitoring READ BUS “COLOR“, perform the following with BUS
“P / N-ID“ data = 1 and 0.
(3) Increase the amplitude of the input signal from 0 mVp-p and measure the
amplitude at mode change to 3.58 NTSC mode.(Normal (1) ; vNCL, High
(0) ; vNCH)
(4) Decrease the amplitude of the input signal from 100 mVp-p and measure
the amplitude at mode change to 3.58 NTSC mode.
(Normal (1) ; vNBL, High (0) ; vNBH)
25
2005-08-18
TA1270BFG
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25°C ± 3°C)
NOTE
CHARACTERISTIC
00
TEST CONDITION
SUB ADDRESS & DATA
SW MODE
01
02
03
05
SW1
―
―
TEST METHOD
(1) Input 4.43 PAL signal 1 rainbow signal (Burst : chroma = 1 : 1) to the
CHROMA input (Pin 6).
80
C5
PAL Ident Sensitivity
80
or
81
80
80
80
A
―
―
(2) While monitoring the READ BUS “COLOR“, perform the following with
BUS “P / N-ID“ data = 1 and 0.
(3) Increase the amplitude of the input signal from 0 mVp-p and measure the
amplitude at mode change to 4.43 PAL mode.
(Normal (1) ; vPCL, High (0) ; vPCH)
(4) Decrease the amplitude of the input signal from 100 mVp-p and measure
the amplitude at mode change to 4.43 PAL mode.
(Normal (1) ; vPBL, High (0) ; vPBH)
(1) Input fsc signal to the chroma input (Pin 6).(signal amplitude = 10 mVp-p,
f01 = 3.579545 MHz,f02 = 4.433619 MHz)
80
C6
TOF Characteristics
83
80
81
or
83
80
A
―
―
(2) Set sub address (01) data to (38h). With f01, set sub address (03) data to
(81h) ; with f01, to (83h). Insert a 1.5 kΩ resistor between R-Y output (Pin
48) and VCC (5 V). Monitor R-Y output (Pin 48) and perform the following.
(3) Measure the output amplitude with f0 and calculate the gain from the
input.
(f01 ; GFC3, f02 ; GFC4)
(4) Measure the output amplitude with f0 ± 500 kHz and calculate the gain
from the input.
(f01 + 500 kHz ; GFH3, f01 − 500 kHz ; GFL3,
f02 + 500 kHz ; GFH4, f02 − 500 kHz ; GFL4)
26
2005-08-18
TA1270BFG
Switching block (Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25°C ± 3°C)
NOTE
S1
CHARACTERISTIC
Y Gain
(Through Mode)
TEST CONDITION
SUB ADDRESS & DATA
SW MODE
00
01
02
80
80
S2
80
Color Difference Gain
(Through Mode)
80
S3
80
Y Gain
(Matrix Mode)
80
80
81
or
82
or
83
81
or
82
or
83
TEST METHOD
SW2
SW6
SW8
SW9
A
B
or
A
―
A
or
B
SW10
SW11
SW14
SW16
B
B
A
―
SW2
SW6
SW8
SW9
A
A
or
B
B
or
A
B
or
A
SW10
SW11
SW14
SW16
A
or
B
A
or
B
A
―
SW2
SW6
SW8
SW9
A
B
or
A
―
A
or
B
SW10
SW11
SW14
SW16
B
B
A
―
27
(1) Input signal 2 to Yin2 input.
(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p)
(2) Apply DC = 5 V to Ys input (Pin 32).
(3) Input signal 2 to Y1 input (Pin 29).
(4) Measure the output amplitude of Y / G output (Pin 20) and calculate the
gain from the input.
(5) Input signal 2 to Y2 input (Pin 25), set Ys input (Pin 32)
DC = 0 V, and repeat (3) and (4) above.
(Y1~Y / G ; GY1, Y2~Y / G ; GY2)
(1) Same as (1) and (2) for S1 above.
(2) Input signal 2 to B-Y1 input (Pin 30) and input +90° phase signal of signal
2 to R-Y1 input (Pin 30).
(3) Measure the amplitude of the B-Y / B output and the R-Y / R output and
calculate the gain from the input.
(4) Input signal 2 to B-Y2 input (Pin 26) and input +90° phase signal of signal
2 to the R-Y2 input (Pin 27).
(5) Set the Ys input pin DC = 0 V and repeat (4) above.
(B-Y1~B-Y / B ; GBY1, R-Y1~R-Y / R ; GRY1
B-Y2~B-Y / B ; GBY2, R-Y2~R-Y / R ; GRY2)
(1) Same as (1) and (2) for S1 above.
(2) Change the sub address (06) data to PAL (81h), NTSC1 (82h), and
NTSC2 (83h), perform the following.
(3) Input signal 2 to Y1 input (Pin 29), measure the amplitude of Y / G output,
B-Y / B output, R-Y / R output, and calculate the gain from the input.
(Y1~Y / G : PAL ; GY1GP, NTSC1 ; GY1GN1, NTSC2 ; GY1GN2
Y1~B-Y / B : PAL ; GY1BP, NTSC1 ; GY1BN1, NTSC2 ; GY1BN2
Y1~R-Y / B : PAL ; GY1RP, NTSC1 ; GY1RN1, NTSC2 ; GY1RN2)
2005-08-18
TA1270BFG
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25°C ± 3°C)
NOTE
CHARACTERISTIC
TEST CONDITION
SUB ADDRESS & DATA
SW MODE
00
01
02
80
S4
S5
S6
S7
S8
83
Color Difference Gain
(Matrix Mode)
Switch Output
Offset Amount
Y / G Output
Black Level Range
B-Y / B Output
Black Level Range
R-Y / R Output
Black Level Range
80
Variable
80
80
80
80
80
Variable
81
or
82
or
83
80
80
Variable
80
TEST METHOD
SW2
SW6
SW8
SW9
A
A
or
B
B
or
A
B
or
A
SW10
SW11
SW14
SW16
A
or
B
A
or
B
A
―
SW2
SW6
SW7
SW8
A
B
B
B
(2) Apply DC = 5 V to Ys input (Pin 32).
SW14
―
―
―
A
―
―
―
(3) Change the sub address (04) data from (80h) to (88h) and measure DC
variation ∆VYO, ∆VBO, and ∆VRO of Y / G output, B-Y / B output, and
R-Y / R output picture period.
SW2
SW6
SW7
SW8
A
B
B
B
SW14
―
―
―
(2) Change the sub address (04) data from (80h) to (F0h) and measure the
DC variation ∆VYB+ of the Y / G output (Pin 20) picture period. Also
change the data from (80h) to (00h) and measure the DC variation
∆VYB−.
A
―
―
―
(3) Change the sub address (04) data from (88h) to (F8h) and from (88h) to
(08h), then measure ∆VYO+ and ∆VYO−.
SW2
SW6
SW7
SW8
A
B
B
B
SW14
―
―
―
(2) Change the sub address (06) data from (80h) to (00h) and measure the
DC variation ∆VBB+ of the B-Y / B output (Pin 21) picture period. Also
change the data from (80h) to (F8h) and measure the DC variation
∆VBB−.
A
―
―
―
(3) Change the sub address (04) data to (88h) and measure ∆VBO+ and
∆VBO− same as (2) above.
SW2
SW6
SW7
SW8
A
B
B
B
SW14
―
―
―
(2) Change the sub address (05) data from (80h) to (00h) and measure the
DC variation ∆VRB+ of the R-Y / R output (Pin 22) picture period. Also
change the data from (80h) to (F8h) and measure the DC variation
∆VRB−.
A
―
―
―
(3) Change the sub address (04) data to (88h) and measure ∆VRO+ and
∆VRO− same as (2) above.
28
(1) Same as (1) and (2) for S2 above.
(2) Change the sub address (05) data to PAL (81h), NTSC1 (82h), and
NTSC2 (83h), perform the following.
(3) Measure the amplitude of Y / G output, B-Y / B output, R-Y / R output,
then calculate the gain from the input.
(Y1~Y / G : PAL ; GGYP, NTSC1 ; GGYN1, NTSC2 ; GGYN2
Y1~B-Y / B : PAL ; GBYP, NTSC1 ; GBYN1, NTSC2 ; GBYN2
Y1~R-Y / R : PAL ; GRYP, NTSC1 ; GRYN1, NTSC2 ; GRYN2)
(1) Input signal 2 to Yin2.
(1) Same as (1) and (2) for S1 above.
(1) Same as (1) and (2) for S1 above.
(1) Same as (1) and (2) for S1 above.
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(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25°C ± 3°C)
TEST CONDITION
NOTE
CHARACTERISTIC
SW2
A
D1
SW MODE
SW4
SW5
B
A
TEST METHOD
TP32
5V
(1) Input signal in the figure below from TG7 to Y2in.
(2) Measure the pin 10 waveform phase difference Sph1 in relation to the
TP8 waveform.
Horizontal Sync Phase
(3) Set the sub address (05) D1 as 1 and measure Sph2 same as (1) above.
Horizontal Blanking Start Phase
A
B
A
5V
D2
(2) Measure phase differences HPs and HPw for pin 10 and pin 21,
respectively
Horizontal Blanking Pulse Width
Gate Pulse Start Phase
A
B
A
5V
D3
Horizontal Blanking Pulse Start Phase
A
B
A
5V
A
B
A
5V
HD Output Pulse Width
(1) Same as (1) for D1.
(2) Measure the pin 14 waveform phase difference HDs in relation to the pin
10 waveform and measure pulse width HDw and amplitude VHD.
HD Output Amplitude
Vertical Blanking Pulse
Start Phase
(1) Same as (1) for D1.
(2) Measure HPs and HPw same as (2) for D3.
Horizontal Blanking Pulse Width
HD Output Start Phase
D5
(1) Same as (1) for D1.
(2) Measure the pin 15 waveform phase difference GPs in relation to the pin
10 waveform and measure pulse width GPw.
Gate Pulse Width
D4
(1) Same as (1) for D1.
A
B
A
5V
(1) Input 50Hz CVBS signal to Y2in.
(2) Measure the pin 15 waveform phase difference VP50s1 in relation to the
pin 8 waveform and measure pulse width VP50s2.
D6
(3) Input 60Hz CVBS signal to Y2Yin.
Vertical Blanking Pulse Width
(4) Measure VP60s1 and VP60s2 same as (2) above.
A
D7
Vertical Pulse Width
B
A
5V
(1) Input 60Hz CVBS signal to Y2in.
(2) Measure the delay Td of the pin 13 vertical pulse in relation to the pin 8
vertical signal and measure the pulse width Tw.
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(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25°C ± 3°C)
TEST CONDITION
NOTE
CHARACTERISTIC
SW2
A
Vertical Pull-In Range (1)
Vertical Pull-In Range (2)
D8
Vertical Pull-In Range (3)
SW MODE
SW4
SW5
B
A
TEST METHOD
TP32
5V
(1) Input 50 Hz CVBS signal to Y2in.
(2) Change the input signal vertical frequency in 0.5 H steps and measure
the pull-in ranges fPL1 and fPH1.
(3) Set the sub address (04) D2 / D1 / D0 to (100) and measure fPL2 and
fPH2 same as in (2).
(4) Input 60 Hz CVBS signal to Y2in and set the sub address (04) D2 / D1 /
D0 to (001).
(5) Change the input signal vertical frequency in 0.5 H steps and measure
the pull-in ranges fPL3 and fPH3.
Vertical Pull-In Range (4)
(6) Set the sub address (04) D2 / D1 / D0 to (101) and measure fPL4 and
fPH4 same as (5).
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TEST SIGNALS
1)
Signal 1 (Rainbow signal)
2)
Signal 2
3)
Signal 3
4)
Signal 4
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(Note D6)
VERTICAL BLANKING PULSE
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(Note D6)
VERTICAL OUTPUT PULSE WIDTH
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TEST CIRCUIT
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APPLICATION CIRCUIT 1 (NTSC)
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APPLICATION CIRCUIT 2 (MULTI)
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APPLICATION CIRCUIT 3 (South America)
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PACKAGE DIMENSIONS
QFP48-P-1014-0.80
Unit: mm
Weight: 0.83g (Typ.)
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