19-2541; Rev 0; 7/02 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs The MAX9310 is a fast, low-skew 1:5 differential driver with selectable LVPECL/HSTL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 345ps with 45.5mA of supply current. The MAX9310 operates from a 2.375V to 2.625V power supply for use in 2.5V systems. A 2:1 input multiplexer is used to select one of two differential inputs. The input selection is controlled through the CLKSEL pin. This device also features a synchronous enable function. The MAX9310 is offered in a space-saving 20-pin TSSOP package and operates over the extended temperature range from -40°C to +85°C. Applications Features ♦ Guaranteed 1.0GHz Operating Frequency ♦ 8ps Output-to-Output Skew ♦ 345ps Propagation Delay ♦ Accepts LVPECL and Differential HSTL Inputs ♦ Synchronous Output Enable/Disable ♦ Two Selectable Differential Inputs ♦ 2.375V to 2.625V Supply Voltage ♦ ESD Protection: ±2kV (Human Body Model) ♦ Input Bias Resistors Drive Output Low for Open Inputs Data and Clock Drivers and Buffers Central-Office Backplane Clock Distribution DSLAM Base Stations Ordering Information ATE PART MAX9310EUP TEMP RANGE PIN-PACKAGE -40°C to +85°C 20 TSSOP Functional diagram appears at end of data sheet. Pin Configuration TOP VIEW Typical Application Circuit RECEIVER MAX9310 ZO = 50Ω Q0 1 20 VCC QO 2 19 EN Q1 3 18 VCC Q1 4 17 CLK1 Q2 5 MAX9310 16 CLK1 Q2 6 15 I.C. Q3 7 14 CLK0 Q3 8 13 CLK0 Q4 9 12 CLKSEL Q4 10 11 GND Q_ ZO = 50Ω Q_ 100Ω TSSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9310 General Description MAX9310 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.1V EN, CLKSEL, CLK_, CLK_, to GND............-0.3V to (VCC + 0.3V) CLK_ to CLK_ ...........................................................|VCC - GND| Continuous Output Current .................................................24mA Surge Output Current..........................................................50mA Continuous Power Dissipation (TA = +70°C) Single-Layer PC Board 20-Pin TSSOP (derate 7.69mW/°C above +70°C) ......615mW Multilayer PC Board 20-Pin TSSOP (derate 11mW/°C above +70°C) .........879mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin TSSOP .........................................................+130°C/W Multilayer PC Board 20-Pin TSSOP ...........................................................+91°C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC board 20-Pin TSSOP ...........................................................+96°C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ...........................................................+20°C/W Operating Temperature Range .......................... -40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (inputs and outputs) .......................±2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - GND = 2.375V to 2.625V, outputs terminated with 100Ω ±1%, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS SINGLE-ENDED INPUTS (CLKSEL, EN) Input High Voltage VIH VCC 1.165 VCC 0.88 VCC 1.165 VCC 0.88 VCC 1.165 VCC 0.88 V Input Low Voltage VIL VCC 1.81 VCC 1.475 VCC 1.81 VCC 1.475 VCC 1.81 VCC 1.475 V Input Current IIN -150 +50 -150 +50 -150 +50 µA VIH(MAX), VIL(MAX) DIFFERENTIAL INPUTS (CLK_, CLK_) Differential Input High Voltage VIHD Figure 1 1.2 VCC 1.2 VCC 1.2 VCC V Differential Input Low Voltage VILD Figure 1 GND VCC 0.095 GND VCC 0.095 GND VCC 0.095 V Differential Input Voltage VID VIHD - VILD 0.095 VCC 0.095 VCC 0.095 VCC V -60 +50 -60 +50 -60 +60 µA 1.6 V Input Current IIH, IIL CLK_, or CLK_ = VIHD or VILD OUTPUTS (Q_, Q_) Output High Voltage VOH Figure 1 Output Low Voltage VOL Figure 1 0.9 Differential Output Voltage VOD VOH - VOL, Figure 1 250 2 1.6 1.6 0.9 350 450 250 0.9 350 450 250 V 350 _______________________________________________________________________________________ 450 mV 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs (VCC - GND = 2.375V to 2.625V, outputs terminated with 100Ω ±1%, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL Change in VOD Between Complementary Output States ∆VOD Output Offset Voltage Change in VOS Between Complementary Output States Output ShortCircuit Current CONDITIONS -40°C MIN TYP MIN TYP 40 1.125 VOS 1.25 ∆VOCM IOSC +25°C MAX 1.375 +85°C MAX MIN TYP 40 1.125 1.25 1.375 1.125 1.25 MAX UNITS 40 mV 1.375 mV mV 25 25 25 Q_ shorted to Q_ 12 12 12 Q_ or Q_ shorted to GND 28 28 28 mA POWER SUPPLY Power-Supply Current ICC (Note 4) 42 75 45.5 75 48.5 75 mA AC ELECTRICAL CHARACTERISTICS (VCC - GND = 2.375V to 2.625V, outputs terminated with 100Ω ±1%, fIN ≤ 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 5) PARAMETER SYMBOL CONDITIONS Propagation Delay CLK_, CLK_ to Q_, Q_ tPHL, tPLH Figure 1 Output-toOutput Skew tSKOO (Note 6) Part-to-Part Skew tSKPP (Note 7) -40°C +25°C +85°C UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX 250 335 600 250 345 600 250 345 600 ps 10 25 8 25 5 25 ps 145 ps 145 145 Added Random Jitter tRJ fIN = 1.0GHz, clock pattern (Note 8) 0.4 1.0 0.4 1.0 0.4 1.0 ps (RMS) Added Deterministic Jitter tDJ fIN = 1.0Gsps, 223 - 1 PRBS pattern (Note 8) 41 52 41 52 41 52 ps (P-P) _______________________________________________________________________________________ 3 MAX9310 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VCC - GND = 2.375V to 2.625V, outputs terminated with 100Ω ±1%, fIN ≤ 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC - GND = 2.5V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 5) PARAMETER SYMBOL -40°C CONDITIONS MIN Operating Frequency fMAX VOD ≥ 250mV 1.0 Differential Output Rise/Fall Time tR/tF 20% to 80%, Figure 1 140 TYP +25°C MAX MIN +85°C TYP MAX MIN 1.0 205 300 140 TYP MAX 1.0 205 300 UNITS GHz 140 205 300 ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterized over the full operating temperature range. Note 4: All pins are open except VCC and GND, all outputs are loaded with 100Ω differentially. Note 5: Guaranteed by design and characterization. Limits are set to ±6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 8: Device jitter added to the input signal. Typical Operating Characteristics (VCC - GND = 2.5V, outputs terminated with 100Ω ±1%, fIN = 1.0GHz, input transition time = 125ps (20% to 80%),VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY 47 46 45 44 43 42 41 -40 -15 10 35 TEMPERATURE (°C) 60 85 300 250 200 150 MAX9310 toc03 fIN = 500MHz 350 215 210 tF tR 205 100 50 40 4 400 RISE/FALL TIME (ps) 48 OUTPUT RISE/FALL vs. TEMPERATURE 220 MAX9310 toc02 ALL PINS ARE OPEN EXCEPT VCC AND GND OUTPUTS LOADED WITH 100Ω DIFFERENTIAL 49 450 DIFFERENTIAL OUTPUT VOLTAGE (mV) 50 MAX9310 toc01 SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) MAX9310 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs 200 0 0.25 0.50 0.75 1.00 1.25 FREQUENCY (GHz) 1.50 1.75 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD) PROPAGATION DELAY vs. TEMPERATURE 370 350 330 310 MAX9310 toc05 MAX9310 toc04 400 PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 390 380 360 340 320 290 300 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 -40 VIHD (V) -15 10 35 60 85 TEMPERATURE (°C) Pin Description PIN NAME 1 Q0 Noninverting Differential Output 0. Typically terminated with 100Ω to Q0. FUNCTION 2 Q0 Inverting Differential Output 0. Typically terminated with 100Ω to Q0. 3 Q1 Noninverting Differential Output 1. Typically terminated with 100Ω to Q1. 4 Q1 Inverting Differential Output 1. Typically terminated with 100Ω to Q1. 5 Q2 Noninverting Differential Output 2. Typically terminated with 100Ω to Q2. 6 Q2 Inverting Differential Output 2. Typically terminated with 100Ω to Q2. 7 Q3 Noninverting Differential Output 3. Typically terminated with 100Ω to Q3. 8 Q3 Inverting Differential Output 3. Typically terminated with 100Ω to Q3. 9 Q4 Noninverting Differential Output 4. Typically terminated with 100Ω to Q4. 10 Q4 Inverting Differential Output 4. Typically terminated with 100Ω to Q4. 11 GND 12 CLKSEL 13 CLK0 Noninverting Differential Clock Input 0. Internal 75kΩ pulldown to GND. 14 CLK0 Inverting Differential Clock Input 0. Internal 75kΩ pullup to VCC and 75kΩ pulldown to GND. Ground Clock Select Input. Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1, CLK1 input. Internal 60kΩ pulldown to GND. 15 I.C. 16 CLK1 Internally Connect. Do not connect externally. Noninverting Differential Input 1. Internal 75kΩ pulldown to GND. 17 CLK1 Inverting Differential Input 1. Internal 75kΩ pullup to VCC and 75kΩ pulldown to GND. _______________________________________________________________________________________ 5 MAX9310 Typical Operating Characteristics (continued) (VCC - GND = 2.5V, outputs terminated with 100Ω ±1%, fIN = 1.0GHz, input transition time = 125ps (20% to 80%),VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs MAX9310 Pin Description (continued) PIN NAME FUNCTION 18, 20 VCC Positive Supply Voltage. Bypass each VCC to GND with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. EN Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected clock input when EN is low. Outputs are synchronously driven to a differential low state on the falling edge of the selected clock input when EN is high. Internal 60kΩ pulldown to GND (Figure 2). 19 CLK VIHD VIHD - VILD CLK VILD tPLHD tPHLD Q_ VOH VOH - VOL Q_ VOL 80% 80% 0V (DIFFERENTIAL) 0V (DIFFERENTIAL) 20% 20% Q_ - Q_ tR tF Figure 1. MAX9310 Timing Diagram EN tS CLK CLK tH tS tH tPLHD Q_ Q_ OUTPUTS ARE LOW OUTPUTS STAY LOW tS = SETUP TIME tH = HOLD TIME Figure 2. MAX9310 EN Timing Diagram 6 _______________________________________________________________________________________ 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs The MAX9310 is a low-skew 1:5 differential driver with two selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. The selected clock accepts a differential input signal and reproduces it on five separate differential LVDS outputs. The inputs are biased with internal resistors such that the output is differential low when inputs are open. The output drivers are guaranteed to operate at frequencies up to 1.0GHz with LVDS output levels conforming to the EIA/TIA-644 standard. The MAX9310 is designed for 2.375V to 2.625V operation in systems with a nominal 2.5V supply. Differential LVPECL Input The MAX9310 has two input differential pairs that accept differential LVPECL/HSTL inputs. Each differential input pair has to be independently terminated. A select pin (CLKSEL) is used to activate the desired input. The maximum magnitude of the differential signal applied to the input is VCC. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (V IHD - VILD) apply simultaneously. Synchronous Enable The MAX9310 is synchronously enabled and disabled with outputs in a differential low state to eliminate shortened clock pulses. EN is connected to the input of an edge-triggered D flip-flop. After power-up, drive EN low and toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are set to a differential low state on the falling edge of the selected clock input after EN goes high (Figure 2). Differential LVDS Output The LVDS outputs must be terminated with 100Ω across Q_ and Q_, as shown in the Typical Application Circuit. The outputs are short-circuit protected. Applications Information Supply Bypassing Bypass each VCC to GND with high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance and reduce power-supply bounce with high-current transients. Controlled-Impedance Traces Input and output trace characteristics affect the performance of the MAX9310. Connect high-frequency input and output signals to 50Ω characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate the outputs with 100Ω across Q_ and Q_, as shown in the Typical Application Circuit. Chip Information TRANSISTOR COUNT: 716 PROCESS: Bipolar Input Bias Resistors Internal biasing resistors ensure a (differential) output low condition in the event that the inputs are not connected. The inverting input (CLK_) is biased with a 75kΩ pulldown to GND and a 75kΩ pullup to VCC. The noninverting input (CLK_) is biased with a 75kΩ pulldown to GND. _______________________________________________________________________________________ 7 MAX9310 Detailed Description 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs MAX9310 Functional Diagram VCC Q0 75kΩ Q0 CLK0 Q1 CLK0 Q1 75kΩ GND 75kΩ Q2 GND 0 VCC Q2 Q3 1 75kΩ CLK1 Q3 CLK1 Q4 75kΩ 75kΩ Q4 GND GND CLKSEL Q EN D I.C. 60kΩ 60kΩ GND GND MAX9310 8 _______________________________________________________________________________________ 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs TSSOP,NO PADS.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9310 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)