VISHAY SIC403BCD-T1-GE3

SiC403A, SiC403BCD
Vishay Siliconix
6 A microBUCK® SiC403A/B
Integrated Buck Regulator with Programmable LDO
DESCRIPTION
FEATURES
The Vishay Siliconix SiC403A/B an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving PowerPAK MLP55-32L pin packages.
The SiC403A/B is capable of operating with all ceramic
solutions and switching frequencies up to 1 MHz. The
programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency.
Additional features include cycle-by-cycle current limit,
voltage soft-start, under-voltage protection, programmable
over-current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC403A/B also provides
an enable input and a power good output.
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High efficiency > 93 %
6 A continuous output current capability
Integrated bootstrap switch
Programmable 200 mA LDO with bypass logic
Temperature compensated current limit
All ceramic solution enabled
Pseudo fixed-frequency adaptive on-time control
Programmable input UVLO threshold
Independent enable pin for switcher and LDO
Selectable ultra-sonic power-save mode (SiC403A)
Selectable power-save mode (SiC403B)
Programmable soft-start
1 % internal reference voltage
Power good output
Over-voltage and under-voltage protections
Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
PRODUCT SUMMARY
Input Voltage Range
3 V to 28 V
APPLICATIONS
Output Voltage Range
0.6 V to 5.5 V
Operating Frequency
200 kHz to 1 MHz
Continuous Output Current
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6A
Peak Efficiency
93 %
Package
PowerPAK MLP55-32L
Notebook, desktop and server computers
Digital HDTV and digital consumer applications
Networking and telecommunication equipment
Printers, DSL, and STB applications
Embedded applications
Point of load power supplies
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
EN/PSV (Tri-State)
PGOOD
LX
ILIM
PGOOD
LX
AGND
TON
ENL
EN\PSV
LDO_EN
VOUT
32 31 30 29 28 27 26 25
FB
VOUT
VDD
AGND
FBL
VIN
VIN
24
1
2
AGND
3
22
PAD 3
4
5
SS 7
BST
21
LX
PAD 2
6
20
19
PGND
PGND
PGND
16
PGND
15
PGND
13
NC 14
11
NC 12
LX
VIN
9
10
8
VIN
VOUT
PGND
18
P
17 GND
VIN
VIN
LX
LX
23
PGND
PAD 1
Typical Application Circuit for SiC403A/B (PowerPAK MLP5x5-32L)
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: [email protected]
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
PGOOD
EN/PSV
VIN
29
A
26
VIN
VDD
VDD
Bootstrap
Switch
AGND
D
Control & Status
Reference
8
BST
12
NC
B
LX
13
LXBST
28
LXS
C
PGND
27
ILIM
14
NC
VDD
DL
SS
7
FB
1
Hi-side
MOSFET
Soft Start
Gate Drive
Control
On-- time
Generator
VDD
FB Comparator
TON
31
VOUT
2
DL
Lo-side
MOSFET
Zero Cross Detector
Bypass Comparator
Valley Current Limit
VDD
VDD
3
A
VIN
Y
B
LDO
VLDO Switchover MUX
FBL
5
32
A = connected to pins 6, 9-11, PAD 2
B = connected to pins 23-25, PAD 3
C = connected to pins 15-22
D = connect to pins 4, 30, PAD 1
ENL
SiC403A/B Functional Block Diagram
LX
ILIM
PGOOD
EN\PSV
LX
tON
AGND
ENL
PIN CONFIGURATION
32 31 30 29 28 27 26 25
1
6
7
BST
8
LX
23
LX
22
PGND
21
PGND
20
PGND
19
PGND
18
PGND
17
PGND
PAD 2
VIN
VIN
9
SS
LX
24
PGND 16
5
NC 14
FBL
VIN
PAD 3
PGND 15
4
LX 13
AGND
AGND
NC 12
3
VIN 11
2
VDD
PAD 1
VIN 10
FB
VOUT
SiC403A/B Pin Configuration (Top View)
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For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
PIN DESCRIPTION
Pin Number
Symbol
Description
1
FB
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from VOUT to AGND.
2
VOUT
Switcher output voltage sense pin - also the input to the internal switch-over between VOUT and
VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin.
3
VDD
Bias supply for the IC - when using the internal LDO as a bias power supply, VDD is the LDO output.
When using an external power supply as the bias for the IC, the LDO output should be disabled.
4, 30, PAD 1
AGND
Analog ground
5
FBL
Feedback input for the internal LDO - used to program the LDO output. Connect to an external
resistor divider from VDD to AGND.
6, 9 to 11, PAD 2
VIN
Input supply voltage
7
SS
The soft start ramp will be programmed by an internal current source charging a capacitor on this pin.
8
BST
Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply
for the high-side gate drive.
12, 14
NC
13
LXBST
23 to 25, PAD3
LX
15 to 22
PGND
26
PGOOD
No connection
LX Boost - connect to the BST capacitor.
Switching (phase) node
Power ground
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required.
27
ILIM
Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS.
28
LXS
LX sense - connects to RILIM
29
EN/PSV
31
tON
On-time programming input - set the on-time by connecting through a resistor to AGND
32
ENL
Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic signal for logic
control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
Enable/power save input for the switching regulator - connect to AGND to disable the switching
regulator, connect to VDD to operate with power-save mode and float to operate in forced continuous
mode.
ORDERING INFORMATION
Part Number
SiC403ACD-T1-GE3
Package
PowerPAK MLP55-32L
Marking (Line 1: P/N)
SiC403A
SiC403BCD-T1-GE3
PowerPAK MLP55-32L
SiC403B
SiC403DB
Reference board
Format:
LINE 1: P/N
LINE 2: Siliconix logo + Lot code + ESD symbol
LINE 3: Factory code + Year code + Work week code
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: [email protected]
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Electrical Parameter
VIN
Conditions
Limits
to PGND
- 0.3 to + 30
VIN
to VDD
- 0.4 max.
LX
to PGND
- 0.3 to + 30
LX (Transient < 100 ns)
to PGND
- 2 to + 30
VDD
to PGND
- 0.3 to + 6
Reference to PGND
- 0.3 to + (VDD + 0.3)
to PGND
- 0.3 to + (VDD - 1.5)
EN/PSV, PGOOD, ILIM
tON
BST
to LX
- 0.3 to + 6
to PGND
- 0.3 to + 35
ENL
Unit
V
- 0.3 to VIN
AGND to PGND
- 0.3 to + 0.3
Temperature
Maximum Junction Temperature
150
Storage Temperature
°C
- 65 to 150
Power Dissipation
Junction to Ambient Thermal Impedance (RthJA)(b)
Maximum Power Dissipation
IC Section
50
Ambient Temperature = 25 °C
3.4
Ambient Temperature = 100 °C
1.3
HBM
2
°C/W
W
ESD Protection
kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)
Parameter
Input Voltage
Symbol
Min.
VIN
3
28
3
5.5
0.6
5.5
VDD to PGND
Output Voltage
VOUT
Typ.
Max.
Unit
V
Temperature
Ambient Temperature
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4
- 40 to 85
For technical questions, contact: [email protected]
°C
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C, typical application circuit
Min.
Typ.
Max.
Unit
Input Power Supplies
Input Supply Voltage
VIN
VDD
VDD
VIN UVLO Threshold (a)
VUVLO
VIN UVLO Hysteresis
VUVLO, HYS
VDD UVLO Threshold
VUVLO
VDD UVLO Hysteresis
VUVLO, HYS
VIN Supply Current
IIN
IDD
VDD Supply Current
FB On-Time Threshold
3
3
Sensed at ENL pin, rising
2.4
Sensed at ENL pin, falling
2.23
Frequency Range
5.5
2.6
2.95
2.4
2.57
0.25
Measured at VDD pin, rising
2.5
3
Measured at VDD pin, falling
2.4
2.9
V
0.2
ENL, EN/PSV = 0 V , VIN = 28 V
12
Standby mode; ENL = VDD, EN/PSV = 0 V
160
ENL, EN/PSV = 0 V
190
SiC403A, EN/PSV = VDD, no load
(fSW = 25 kHz), VFB > 0.6 V (b)
0.3
SiC403B, EN/PSV = VDD, no load,
VFB > 0.6 V (b)
0.7
VDD = 5 V, fSW = 250 kHz,
EN/PSV = floating, no load (b)
8
VDD = 3 V, fSW = 250 kHz,
EN/PSV = floating, no load (b)
5
Static VIN and load
fSW
28
20
µA
300
mA
0.594
0.600
Continuous mode operation
0.606
1000
Minimum fSW, (SiC403A only)
25
Bootstrap Switch Resistance
V
kHz

10
Timing
On-Time
tON
Minimum On-Time (b)
Minimum Off-Time
Continuous mode operation VIN = 12 V,
VOUT = 5 V, fSW = 300 kHz, Rton = 133 k
999
tON, min.
(b)
tOFF, min.
1110
1220
80
ns
VDD = 5 V
250
VDD = 3 V
370
3
µA
When VOUT reaches regulation
1.5
V
500
k
Soft Start
Soft Start Current (b)
ISS
Soft Start Voltage (b)
VSS
Analog Inputs/Outputs
VOUT Input Resistance
RO-IN
Current Sense
Zero-Crossing Detector Threshold Voltage
VSense-th
LX-PGND
-3
+3
PG_VTH_UPPER
Upper limit, VFB > internal 600 mV reference
+ 20
PG_VTH_LOWER
Lower limit, VFB < internal 600 mV reference
- 10
VDD = 5 V, CSS = 10 nF
12
VDD = 3 V, CSS = 10 nF
7
mV
Power Good
Power Good Threshold
Start-Up Delay Time
(between PWM enable and PGOOD high)
Fault (noise-immunity) Delay Time
Leakage Current
Power Good On-Resistance
(b)
PG_Td
PG_ICC
%
ms
5
µs
1
PG_ILK

10
PG_RDS_ON
µA
Fault Protection
Valley Current Limit
ILIM
VDD = 5 V, RILIM = 4750, TJ = 0 °C to +125 °C
VDD = 3.3 V, RILIM = 4750
ILIM Source Current
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
4.8
6
5.1
10
For technical questions, contact: [email protected]
7.2
A
µA
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
VIN = 12 V, VDD = 5 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C, typical application circuit
Min.
Typ.
Max.
Unit
- 10
0
+ 10
mV
Parameter
Symbol
ILIM Comparator Offset Voltage
VILM-LK
With respect to AGND
Output Under-Voltage Fault
VOUV_Fault
VFB with respect to Internal 600 mV
reference, 8 consecutive clocks
- 25
Smart Power-Save Protection
Threshold Voltage (b)
PSave_VTH
VFB with respect to internal 600 mV
+ 10
VFB with respect to internal 600 mV
+ 20
5
µs
10 °C hysteresis
150
°C
Over-Voltage Protection Threshold
Over-Voltage Fault Delay (b)
tOV-Delay
Over Temperature Shutdown (b)
TShut
%
Logic Inputs/Outputs
Logic Input High Voltage
VIH
Logic Input Low Volatge
VIL
EN/PSV Input for P-Save Operation (b)
1
0.4
VDD = 5 V
EN/PSV Input for Forced Continuous
Operation (b)
EN/PSV Input for Disabling Switcher
EN/PSV Input Bias Current
IEN
ENL Input Bias Current
FBL, FB Input Bias Current
EN/PSV = VDD or GND
IENL
ENL = VIN = 28 V
FBL_ILK
FBL, FB = VDD or GND
2.2
5
1
2
0
0.4
- 10
+ 10
11
-1
18
V
µA
+1
Linear Dropout Regulator
FBL (b)
VLDO ACC
LDO Current Limit
LDO_ILIM
0.75
Short-circuit protection,
VIN = 12 V, VDD < 0.75 V
65
Start-up and foldback, VIN = 12 V,
0.75 < VDD < 90 % of final VDD value
115
Operating current limit, VIN = 12 V,
VDD > 90 % of final VDD value
VLDO to VOUT Switch-over Threshold
(d)
VLDO to VOUT Non-switch-over Threshold (d)
VLDO to VOUT Switch-over Resistance
LDO Drop Out Voltage (e)
135
V
mA
200
VLDO-BPS
- 130
+ 130
VLDO-NBPS
- 500
+ 500
RLDO
mV
VOUT = 5 V
2

From VIN to VDD,
VDD = + 5 V, IVLDO = 100 mA
1.2
V
Notes:
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
b. Typical value measured on standard evaluation board.
c. SiC403A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout
d. The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT.
e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
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For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
2.5
100
1.26
0.14
1.24
2
VIN=20V
V IN=6V
REGULATION
1
VOUT(VDC)
PLOSS(W)
Efficiency(%)
1.5
40
0.06
0.04
1.16
VIN=6V
0
0.1
1
0
1.14
10
0.001
Vin=20V
Vin=12V
0
0.01
0.1
1
10
IOUT(A)
Effiency vs. Load-Forced Continuous Mode
VOUT vs. Load-Forced Continuous Mode
VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403B
100
VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403B
0.12
1.26
2.5
Vin=6V
0.02
Vin=6V
Vpeak
IOUT(A)
Efficiency
0.08
0.5
VIN=20V
0.01
Vin=6V
1.2
1.18
VIN=12V
20
0.001
0.1
1.22
VIN=12V
60
0.12
Vin=12V
Vin=20V
VPEAK(Vrms)
80
Vin=12V
1.24
Vin=20V
80
0.1
Vin=12V
2
Vin=20
Regula o
VOUT(VDC)
1.5
PLOSS(W)
Efficiency(%)
60
40
1
Vin=6
1.2
0.06
VPEAK(Vrms)
0.08
1.22
0.04
1.18
Vin=12
Vin=20V
20
0.5
1.16
Vin=12V
Vpeak
Vin=6
Vin=6V
0
0.01
0.1
1
0
1.14
0
0.001
0.02
Vin=20
PLOSS
0.001
10
0.01
0.1
1
10
IOUT(A)
IOUT(A)
Effiency vs. Load-PSAVE Mode
VOUT vs. Load-PSAVE Mode
VOUT = 1.2 V, VDD = EN/PSV = 5 V, External Bias, SiC403B
VOUT = 1.2 V, VDD = EN/PSV = 5 V, External Bias, SiC403B
100
2.5
1.26
0.12
1.24
0.1
VDD=3.3V
VDD=5V
2
VDD=5V
40
1
VDD=5V
20
Regula on
1.2
0.06
1.18
0.04
0.5
1.16
VDD=3.3V
0
0.01
0.1
0.02
VDD=5V
VPEAK
VDD =3.3V
0
0.001
0.08
VDD=3.3V
VPEAK(Vrms)
1.5
VOUT(VDC)
1.22
60
PLOSS(W)
Efficiency(%)
80
1
10
0
1.14
0.001
0.01
0.1
1
10
OUT(A)
Effiency vs. Load-PSAVE Mode
IOUT(A)
VOUT vs. Load-PSAVE Mode
VOUT = 1.2 V, VIN = 12 V, VDD = EN/PSV = 5 V, External Bias, SiC403B
VOUT = 1.2 V, VIN = 12 V, VDD = EN/PSV = 5 V, External Bias, SiC403B
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: [email protected]
www.vishay.com
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
400
400
350
350
VIN=12V
300
VIN=6V
Frequency(KHz)
Frequency(KHz)
300
250
VIN=20V
200
150
VIN=6V
250
VIN=20V
VIN=12V
200
150
100
100
50
50
0
0
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT(ADC)
IOUT(ADC)
Frequency vs. Load-Forced Continuous Mode
Frequency vs. Load-PSAVE Mode
VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403B
VOUT = 1.2 V, VDD = EN/PSV = 5 V, External Bias, SiC403B
1.575
0.150
1.55
0.125
1.525
0.100
400
350
1.5
0.075
1.475
0.050
Vpeak
1.45
Frequency(KHz)
VOUT
VPEAK(Vrms)
VOUT(VDC)
300
0.025
1.425
250
200
150
100
50
0
0.000
6
8.8
11.6
14.4
17.2
20
22.8
25.6
6
VIN(VDC)
8
10
12
14
16
18
20
22
24
26
28
VIN(VDC)
VOUT vs. Line-Forced Continuous Mode
Frequency vs. Line-FCM Mode
VOUT = 1.5 V, VLDO = VDD = ENL = 5 V, EN/PSV is Floating, SiC403B
VOUT = 1.5 V, VLDO = VDD = ENL = 5 V, EN/PSV is Floating, SiC403B
1200
2.5
100
1000
80
2
VIN=20V
VIN=6V
600
3.3V
400
60
1.5
VIN=12V
1
40
PLOSS(W)
Efficiency(%)
On-Time(nS)
800
VIN=20V
20
5V
200
0.5
VIN=12V
VIN=6V
0
0
0
6
8
10
12
14
16
18
20
22
24
26
28
0.001
0.01
0.1
IOUT(ADC)
1
10
Input Voltage(V)
On Time vs. Line
Efficiency vs. Load-Forced Continuous Mode
VOUT = 1.5 V, VLDO = VDD = ENL = 5 V, IOUT = 0 A, SiC403B
VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403A
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For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
100
90
100
2
80
2.5
VIN=20V
1.5
Efficiency
50
1
40
VIN=20V
30
20
0.5
VIN=12V
10
Efficiency
60
1.5
VDD=5V
1
40
0.5
20
VDD=5V
Ploss
PLOSS
VIN=6V
0
0.001
2
VDD3.3V
0.01
0.1
1
VDD=3.3V
0
0
0
PLOSS(W)
VIN=12V
60
PLOSS(W)
70
Efficiency(%)
VIN=6V
80
Efficiency(%)
2.5
0.001
0.01
10
0.1
1
10
IOUT(ADC)
IOUT(ADC)
Efficiency vs. Load-PSAVE Mode
Efficiency vs. Load-PSAVE Mode
VOUT = 1.2 V, VDD = 5 V = EN/PSV, External Bias, SiC403A
VOUT = 1.2 V, VIN = 12 V, VDD = EN/PSV = 5 V, External Bias, SiC403A
Vout
Vout
(50mV/div)
(20mV/div)
LX
LX
(5V/div)
(5V/div)
Time(20µs/div)
Time(2µs/div)
Powersave Mode - No Load
Forced Continuous Mode - No Load
VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V, SiC403A
VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V
LX
(10V/div)
(10V/div)
Vout
Vout
(500mV/div)
(500mV/div)
VDD
VDD
(5V/div)
(5V/div)
LX
(5V/div)
Pgood
Pgood
(5V/div)
Time(1ms/div)
Time(1ms/div)
Self-Biased Start-Up - Power Good True
Enable Start-Up - Power Good True
VIN = 12 V step, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V
VIN = 12 V, VOUT = 1.2 V, IOUT = 1 A, VDD = EN/PSV= 5 V
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: [email protected]
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SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Vout
(20mV/div)
LX
(5V/div)
Time(10ms/div)
Powersave Mode - No Load
VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V, SiC403B
Vout
Vout
(500mV/div)
(200mV/div)
IOUT
(5A/div)
LX
LX
(10V/div)
(10V/div)
Pgood
(5V/div)
(5V/div)
Pgood
Time(200µs/div)
Time(500µs/div)
Output Under-Voltage Response
Output Over-Current Response
VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = ENL = 3.3 V, EN/PSV is floating
VIN = 12 V, VOUT = 1.2 V, VDD = ENL = 3.3 V, EN/PSV is floating
(500mV/div)
VOUT
Vout
(200mV/div)
IOUT
IOUT
(5A/div)
(5A/div)
LX
LX
(10V/div)
(10V/div)
Pgood
(5V/div)
Pgood
(5V/div)
Time(50µs/div)
Time(500µs/div)
Short Output Response
Shorted Output Response at Soft-Start Operation
VIN = 12 V, VOUT = 1.2 V, VDD = ENL = 3.3 V, EN/PSV is floating
VIN = 12 V, VOUT = 1.2 V, VDD = ENL = 3.3 V, EN/PSV is floating
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For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Vout
Vout
(100mV/div)
(100mV/div)
LX
LX
(10V/div)
(2A/div)
(10V/div)
IOUT
(2A/div)
Iout
Time(10µs/div)
Time(10µs/div)
Transient Response in Power Saving Mode
Transient Response in Forced Continuous Mode
VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A to 6 A, VDD = EN/PSV = 5 V
VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A to 6 A, VDD = EN/PSV = 5 V
OPERATIONAL DESCRIPTION
Device Overview
The SiC403A/B is a step down synchronous DC/DC
buck converter with integrated power MOSFETs and a
200 mA capable programmable LDO. The device is capable
of 6 A operation at very high efficiency. A space saving
5 x 5 (mm) 32-pin package is used. The programmable
operating frequency of up to 1 MHz enables optimizing the
configuration for PCB area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive
on-time control. This control method allows fast transient
igponse which permits the use of smaller output capacitors.
logic low, the output voltage discharges into the VOUT pin
through an internal FET.
Pseudo-Fixed Frequency Adaptive On-Time Control
The PWM control method used by the SiC403A/B is
pseudo- fixed frequency, adaptive on-time, as shown in
figure 1. The ripple voltage generated at the output capacitor
ESR is used as a PWM ramp signal. This ripple is used to
trigger the on-time of the controller.
tON
VIN
VLX
Input Voltage Requirements
The SiC403A/B requires two input supplies for normal
operation: VIN and VDD. VIN operates over a wide range from
3 V to 28 V. VDD requires a 3 V to 5.5 V supply input that can
be an external source or the internal LDO configured to
supply 3 V to 5.5 V from VIN.
CIN
VFB
Q1
VLX
VOUT
L
Q2
Power Up Sequence
When the SiC403A/B uses an external power source at the
VDD pin, the switching regulator initiates the start up when
VIN, VDD, and EN/PSV are above their respective thresholds.
When EN/PSV is at logic high, VDD needs to be applied after
VIN rises. It is also recommended to use a 10  resistor
between an external power source and the VDD pin. To start
up by using the EN/PSV pin when both VDD and VIN are
above their respective thresholds, apply EN/PSV to enable
the start-up process. For SiC403A/B in self-biased mode,
refer to the LDO section for a full description.
Shutdown
The SiC403A/B can be shut-down by pulling either VDD or
EN/PSV below its threshold. When using an external power
source, it is recommended that the VDD voltage ramps down
before the VIN voltage. When VDD is active and EN/PSV at
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
FB threshold
ESR
FB
+
COUT
Figure 1 - Output Ripple and PWM Control Method
The adaptive on-time is determined by an internal one- shot
timer. When the one-shot is triggered by the output ripple, the
device sends a single on-time pulse to the high- side
MOSFET. The pulse period is determined by VOUT and VIN;
the period is proportional to output voltage and inversely
proportional to input voltage. With this adaptive on-time
arrangement, the device automatically anticipates the
on-time needed to regulate VOUT for the present VIN
condition and at the selected frequency.
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SiC403A, SiC403BCD
Vishay Siliconix
The advantages of adaptive on-time control are:
• Predictable operating frequency compared to other
variable frequency methods.
• Reduced component count by eliminating the error
amplifier and compensation components.
• Reduced component count by removing the need to sense
and control inductor current.
• Fast transient response - the response time is controlled
by a fast comparator instead of a typically slow error
amplifier.
• Reduced output capacitance due to fast transient
response.
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in figure 2. The FB
Comparator output goes high when VFB is less than the
internal 600 mV reference. This feeds into the gate drive and
turns on the high-side MOSFET, and also starts the one-shot
timer. The one-shot timer uses an internal comparator and a
capacitor. One comparator input is connected to VOUT, the
other input is connected to the capacitor. When the on-time
begins, the internal capacitor charges from zero volts
through a current which is proportional to VIN. When the
capacitor voltage reaches VOUT, the on-time is completed
and the high-side MOSFET turns off.
Gate
drives
FB comparator
FB
VREF
+
DH
VOUT
VIN
Rton
Q1
VLX
DL
Q2
COUT
Rton =
On-time = K x Rton x (VOUT/VIN)
(ton - 10 ns) x VIN
25 pF x VOUT
Immediately after the on-time, the DL (drive signal for the low
side FET) output drives high to turn on the low-side
MOSFET. DL has a minimum high time of ~ 320 ns, after
which DL continues to stay high until one of the following
occurs:
• VFB falls below the reference
• The zero cross detector senses that the voltage on the LX
node is below ground. Power save is activated eight
switching cycles after a zero crossing is detected.
tON Limitations and VDD Supply Voltage
For VDD below 4.5 V, the tON accuracy may be limited by the
input voltage.
The original RtON equation is accurate if VIN satisfies the
relationship over the entire VIN range, as follows.
VIN < (VDD - 1.6 V) x 10
If VIN exceeds (VDD - 1.6 V) x 10, for all or part of the VIN
range, the RtON equation is not accurate. In all cases where
VIN > (VDD - 1.6 V) x 10, the RtON equation must be modified,
as follows.
Rton =
FB
+
(VDD - 1.75) x 10
VIN
The maximum RtON value allowed is shown by the following
equation.
VOUT
L
ESR
One-shot
timer
k=
(ton - 10 ns) x (VDD - 1.6 V) x 10
25 pF x VOUT
Note that when VIN > (VDD - 1.6 V) x 10 , the actual on-time
is fixed and does not vary with VIN. When operating in this
condition, the switching frequency will vary inversely with VIN
rather than approximating a fixed frequency.
Figure 2 - On-Time Generation
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN. Under
steady-state conditions, the switching frequency can be
determined from the on-time by the following equation.
VOUT
fSW =
tON x VIN
VOUT Voltage Selection
The switcher output voltage is regulated by comparing VOUT
as seen through a resistor divider at the FB pin to the internal
600 mV reference voltage, see figure 3.
To FB pin
VOUT
R1
R2
The SiC403A/B uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide an operating frequency from
200 kHz to 1 MHz using a resistor between the TON pin and
ground. The resistor value is selected by the following
equation.
Rton =
k
25 pF x fSW
The constant, k, equals 1, when VDD is greater than 3.6 V. If
VDD is less than 3.6 V and VIN is greater than (VDD -1.75) x 10,
k is shown by the following equation.
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Figure 3 - Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
VOUT = 0.6 x 1 +
For technical questions, contact: [email protected]
R1
R2
+
VRIPPLE
2
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
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SiC403A, SiC403BCD
Vishay Siliconix
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
VOUT = 0.6 x 1 +
R1
R2
+
VRIPPLE
2
x
1 + (R1ωCTOP)2
1+
R2 x R1
ωC
R2 + R1 TOP
2
Enable and Power-Save Inputs
The EN/PSV input is used to enable or disable the switching
regulator. When EN/PSV is low (grounded), the switching
regulator is off and in its lowest power state. When off, the
output of the switching regulator soft-discharges the output
into a 15  internal resistor via the VOUT pin. When EN/PSV
is allowed to float, the pin voltage will float to 33 % of the
voltage at VDD. The switching regulator turns on with
power-save disabled and all switching is in forced continuous
mode.
When EN/PSV is high (above 44 % of the voltage at VDD),
the switching regulator turns on with power-save enabled.
The SiC403A/B P-Save operation reduces the switching
frequency according to the load for increased efficiency at
light load conditions.
Forced Continuous Mode Operation
The SiC403A/B operates the switcher in FCM (Forced
Continuous Mode) by floating the EN/PSV pin (see figure 4).
In this mode one of the power MOSFETs is always on, with
no intentional dead time other than to avoid crossconduction. This feature results in uniform frequency across
the full load range with the trade-off being poor efficiency at
light loads due to the high-frequency switching of the
MOSFETs. DH is gate signal to drive upper MOSFET. DL is
lower gate signal to drive lower MOSFET
FB ripple
voltage (VFB)
FB threshold
(600 mV)
DC load current
Inductor
current
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
DH
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 4 - Forced Continuous Mode Operation
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
Ultrasonic Power-Save Operation (SiC403A)
The SiC403A provides ultrasonic power-save operation at
light loads, with the minimum operating frequency fixed at
slightly under 25 kHz. This is accomplished by using an
internal timer that monitors the time between consecutive
high-side gate pulses. If the time exceeds 40 µs, DL drives
high to turn the low-side MOSFET on. This draws current
from VOUT through the inductor, forcing both VOUT and VFB
to fall. When VFB drops to the 600 mV threshold, the next DH
(the drive signal for the high side FET) on-time is triggered.
After the on-time is completed the high-side MOSFET is
turned off and the low-side MOSFET turns on. The low-side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low-side MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40 µs, the frequency will not fall far below
25 kHz. Figure 5 shows ultrasonic power-save operation.
minimum fSW ~ 25 kHz
FB ripple
voltage (VFB)
FB threshold
(600 mV)
(0A)
Inductor
current
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
DH
40 µs time-out
DL
After the 40 µs time-out, DL drives high if VFB
has not reached the FB threshold.
Figure 5 - Ultrasonic Power-Save Operation
Power-Save Operation (SiC403B)
The SiC403B provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors the
inductor current via the voltage across the low-side MOSFET
during the off-time. If the inductor current falls to zero
for 8 consecutive switching cycles, the controller enters
MOSFET on each subsequent cycle provided that the
power-save operation. It will turn off the low-side MOSFET
on each subsequent cycle provided that the current crosses
zero. At this time both MOSFETs remain off until VFB drops
to the 600 mV threshold. Because the MOSFETs are off, the
load is supplied by the output capacitor.
If the inductor current does not reach zero on any switching
cycle, the controller immediately exits power-save and
returns to forced continuous mode.
Figure 6 shows power-save operation at light loads.
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SiC403A, SiC403BCD
Vishay Siliconix
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers for the power MOSFETs.
Current Limit Protection
Smart Power-Save Protection
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with power-save
enabled, this can force VOUT to slowly rise and reach the
over-voltage threshold, resulting in a hard shut-down. Smart
power-save prevents this condition. When the FB voltage
exceeds 10 % above nominal, the device immediately
disables power-save, and DL drives high to turn on the
low-side MOSFET. This draws current from VOUT through
the inductor and causes VOUT to fall. When VFB drops back
to the 600 mV trip point, a normal tON switching cycle begins.
This method prevents a hard OVP shut-down and also
cycles energy from VOUT back to VIN. It also minimizes
operating power by avoiding forced conduction mode
operation. Figure 7 shows typical waveforms for the Smart
Power Save feature.
VOUT drifts up to due to leakage
current flowing into COUT
Smart power save
threshold (825 mV)
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
FB
threshold
DH and DL off
High-side
drive (DH)
Low-side
drive (DL)
Normal DL pulse after DH
on-time pulse
Figure 7 - Smart Power-Save
SmartDriveTM
For each DH pulse, the DH driver initially turns on the high
side MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low-side diode. Once the diode is off and the
LX voltage has risen 0.5 V above PGND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
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14
ILOAD
ILIM
Time
Figure 8 - Valley Current Limit
Setting the valley current limit to 6 A results in a peak
inductor current of 6 A plus peak ripple current. In this
situation, the average (load) current through the inductor is
6 A plus one-half the peak-to-peak ripple current.
The internal 10 µA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the RDS-ON.
The RILIM value is calculated by the following equation.
RILIM = 792 x ILIM x [0.101 x (5 V - VDD) + 1]
Single DH on-time pulse
after DL turn-off
DL turns on when smart
PSAVE threshold is reached
DL turns off FB
threshold is reached
IPEAK
Inductor Current
Figure 6 - Power-Save Mode
The device features programmable current limiting, which is
accomplished by using the RDS-ON of the lower MOSFET for
current sensing. The current limit is set by RILIM resistor. The
RILIM resistor connects from the ILIM pin to the LXS pin which
is also the drain of the low-side MOSFET. When the low-side
MOSFET is on, an internal ~ 10 µA current flows from the
ILIM pin and through the RILIM resistor, creating a voltage
drop across the resistor. While the low-side MOSFET is on,
the inductor current flows through it and creates a voltage
across the RDS-ON. The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage drop
exceeds the voltage across RILIM, the voltage at the ILIM pin
will be negative and current limit will activate. The current
limit then keeps the low-side MOSFET on and will not allow
another high-side on-time, until the current in the low-side
MOSFET reduces enough to bring the ILIM voltage back up
to zero. This method regulates the inductor valley current at
the level shown by ILIM in figure 8.
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note that
because the low-side MOSFET with low RDS-ON is used for
current sensing, the PCB layout, solder connections, and
PCB connection to the LX node must be done carefully to
obtain good results. RILIM should be connected directly to
LXS (pin 28).
Soft-Start of PWM Regulator
SiC403A/B has a programmable soft-start time that is
controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 3 µA flowing
For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
through the SS pin to charge the capacitor. During the start
up process (figure 9), 50 % of the voltage at the SS pin is
used as the reference for the FB comparator. The PWM
comparator issues an on-time pulse when the voltage at the
FB pin is less than 40 % of the SS pin. As a result, the output
voltage follows the SS voltage. The output voltage reaches
and maintains regulation when the soft start voltage
is  1.5 V. The time between the first LX pulse and VOUT
reaching regulation is the soft-start time (tSS). The
calculation for the soft-start time is shown by the following
equation.
tSS = CSS x 1.5 V
3 µA
The voltage at the SS pin continues to ramp up and
eventually equals 64 % of VDD. After the soft start completes,
the FB pin voltage is compared to an internal reference of
0.6 V. The delay time between the VOUT regulation point and
PGOOD going high is shown by the following equation.
tPGOOD-DELAY =
CSS x (0.64 x VDD - 1.5 V)
3 µA
PGOOD will transition low if the VFB pin exceeds + 20 % of
nominal, which is also the over-voltage shutdown threshold.
PGOOD also pulls low if the EN/PSV pin is low when VDD is
present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 600 mV + 20 %
(720 mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input is
toggled or VDD is cycled. There is a 5 µs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
Output Under-Voltage Protection
When VFB falls 25 % below its nominal voltage (falls to
450 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate
the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3 V. An
internal POR (Power-On Reset) occurs when VDD exceeds
3 V, which resets the fault latch and a soft-start counter cycle
begins which prepares for soft-start. The SiC403A/B then
begins a soft-start cycle. The PWM will shut off if VDD falls
below 2.4 V.
LDO Regulator
SiC403A/B has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND (see figure 10).
The feedback pin (FBL) for the LDO is regulated to 750 mV.
Figure 9 - Soft-start Timing Diagram
Pre-Bias Start-Up
The SiC403A/B can start up normally even when there is an
existing output voltage present. The soft start time is still the
same as normal start up (when the output voltage starts from
zero). The output voltage starts to ramp up when 40 % of the
voltage at SS pin meets the existing FB voltage level.
Pre-bias startup is achieved by turning off the lower gate
when the inductor current falls below zero. This method
prevents the output voltage from discharging.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the FB
pin is 10 % below the nominal voltage, PGOOD is pulled low.
It is held low until the output voltage returns above - 8 % of
nominal.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
Figure 10 - LDO Output Voltage Selection
The LDO output voltage is set by the following equation.
VLDO = 750 mV x 1 +
RLDO1
RLDO2
A minimum capacitance of 1 µF referenced to AGND is
normally required at the output of the LDO for stability.
Note that if the LDO voltage is set lower than 4.5 V, the
minimum output capacitance for the LDO is 10 µF.
For technical questions, contact: [email protected]
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LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV and VDD are above
their threshold. The table below summarizes the function of
ENL and EN/PSV pins.
EN/PSV
ENL
LDO
Switcher
Disabled
Low, < 0.4 V
Off
Off
Enabled
Low, < 0.4 V
Off
On
Disabled
1 V < High < 2.6 V
On
Off
Enabled
1 V < High < 2.6 V
On
Off
Disabled
High, > 2.6 V
On
Off
Enabled
High, > 2.6 V
On
On
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SiC403A/B is self-biased from the
LDO and runs from the VIN power source only, the VIN UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN, ENL
and AGND pins. When SiC403A/B has an external bias
voltage at VDD and the ENL pin is used to program the VIN
UVLO feature, the voltage at FBL needs to be higher than
750 mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM output
turning off. If ENL goes below the VIN UVLO threshold and
stays above 1 V, then the switcher will turn off but the LDO
will remain on.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
2. VLDO output
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when the
VDD voltage (which is the LDO output voltage) is less than
0.75 V, the LDO initiates a current-limited start-up (typically
65 mA) to charge the output capacitors while protecting from
a short circuit event. When VDD is greater than 0.75 V but still
less than 90 % of its final value (as sensed at the FBL pin),
the LDO current limit is increased to ~115 mA. When VDD
has reached 90 % of the final value (as sensed at the FBL
pin), the LDO current limit is increased to ~ 200 mA and the
LDO output is quickly driven to the nominal value by the
internal LDO regulator. It is recommended that during LDO
start-up to hold the PWM switching off until the LDO has
reached 90 % of the final value. This prevents overloading
the current-limited LDO output during the LDO start-up.
Due to the initial current limitations on the LDO during power
up (figure 11), any external load attached to the VDD pin must
be limited to less than the start up current before the LDO
has reached 90 % of its final regulation value.
Figure 11 - LDO Start-Up
LDO Switch-Over Poeration
The SiC403A/B includes a switch-over function for the LDO.
The switch-over function is designed to increase efficiency
by using the more efficient DC/DC converter to power the
LDO output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the VDD pin
directly to the VOUT pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
in a power savings and maximizes efficiency. If the LDO
output is used to bias the SiC403A/B, then after switch-over
the device is self-powered from the switching regulator with
the LDO turned off.
The switch-over starts 32 switching cycles after PGOOD
output goes high. The voltages at the VDD and VOUT pins are
then compared; if the two voltages are within ± 300 mV of
each other, the VDD pin connects to the VOUT pin using an
internal switch, and the LDO is turned off. To avoid unwanted
switch-over, the minimum difference between the voltages
for VOUT and VDD should be ± 500 mV.
It is not recommended to use the switch-over feature for an
output voltage less than VDD UVLO threshold since the
SiC403A/B is not operational below that threshold.
Switch-Over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in figure 12. If the
voltage at the VOUT pin is higher than VDD, then the
respective diode will turn on and the current will flow through
this diode. This has the potential of damaging the device.
Therefore, VOUT must be less than VDD to prevent damaging
the device.
Switchover
control
Switchover
MOSFET
VOUT
LDO
Parastic diode
VDD
Figure 12 - Switch-over MOSFET Parasitic Diodes
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16
For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor ripple
current must be specified.
The maximum input voltage (VIN max.) is the highest specified
input voltage. The minimum input voltage (VIN min.) is
determined by the lowest input voltage after evaluating the
voltage drops due to connectors, fuses, switches, and PCB
traces.
The following parameters define the design:
• Nominal output voltage (VOUT)
• Static or DC output tolerance
• Transient response
• Maximum load current (IOUT)
There are two values of load current to evaluate - continuous
load current and peak load current. Continuous load current
relates to thermal stresses which drive the selection of
the inductor and input capacitors. Peak load current
determines instantaneous component stresses and filtering
requirements such as inductor saturation, output capacitors,
and design of the current limit circuit.
The following values are used in this design:
• VIN = 12 V ± 10 %
• VOUT = 1.5 V ± 4 %
• fSW = 300 kHz
• Load = 6 A max.
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency.
The desired switching frequency is 300 kHz which results
from using component selected for optimum size and cost.
A resistor (RtON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
Rton =
(ton - 10 ns) x VIN
25 pF x VOUT
To select RtON, use the maximum value for VIN, and for tON
use the value associated with maximum VIN.
tON =
VOUT
VINmax. x fSW
Substituting for RtON results in the following solution.
RtON = 129.9 k, use RtON = 130 k.
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values result in smaller size but
create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current/voltage
and for a given DC resistance are more efficient. However,
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
larger inductance translates directly into larger packages and
higher cost. Cost, size, output ripple, and efficiency are all
used in the selection process.
The ripple current will also set the boundary for PSave
operation. The switching will typically enter PSave mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 4 A then PSave operation will
typically start for loads less than 2 A. If ripple current is set at
40 % of maximum load current, then PSave will start for loads
less than 20 % of maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25 % to 50 % of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
L=
(VIN - VOUT) x tON
IRIPPLE
Example
In this example, the inductor ripple current is set equal to
50 % of the maximum load current. Thus ripple current will be
50 % x 6 A or 3 A. To find the minimum inductance needed,
use the VIN and tON values that correspond to VINmax.
L=
(13.2 - 1.5) x 379 ns
= 1.48 µH
3A
A slightly larger value of 1.5 µH is selected. This will
decrease the maximum IRIPPLE to 2.7 A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
tON_VINmin. =
IRIPPLE =
25 pF x RtON x VOUT
VINmin.
+ 10 ns = 461 ns
(VIN - VOUT) x tON
L
IRIPPLE_min. =
(10.8 V - 1.5 V) x 461 ns
= 2.38 A
1.5 µH x (1 + 0.2)
IRIPPLE_max. =
(10.8 V - 1.5 V) x 379 ns
= 3.7 A
1.5 µH x (1 - 0.2)
Capacitor Selection
The output capacitors are chosen based upon required
ESR and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple.
A change in the output ripple voltage will lead to a change in
DC voltage at the output.
The design goal for output voltage ripple is 4 % of 1.5 V or
60 mV. The maximum ESR value allowed is shown by the
following equations.
For technical questions, contact: [email protected]
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17
This document is subject to change without notice.
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SiC403A, SiC403BCD
Vishay Siliconix
VRIPPLE
ESRmax. =
IRIPPLEmax.
=
60 mV
3.7 A
ESRmax. = 16.2 mΩ
1
xI
)2
2 RIPPLEmax.
(VPEAK)2 - (VOUT)2
L (IOUT +
Assuming a peak voltage VPEAK of 1.6 V (150 mV rise upon
load release), and a 6 A load release, the required
capacitance is shown by the next equation.
1
x 3.7)2
2
2
(1.6) - (1.5)2
1.5 µH x (6 +
COUT_min. =
COUT = 7.9 x
COUT = 194 µF
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current is
at the peak, determines the required capacitance. If the load
release is instantaneous (load changes from maximum to
zero in < 1 µs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
COUT_min. =
7.9
6
x 1 µs
1.5
2
2 (1.6 - 1.5)
1.5 µH x
COUT_min. = 298 µF
During the load release time, the voltage cross the inductor
is approximately - VOUT. This causes a down-slope or falling
di/dt in the inductor. If the load dI/dt is not much faster than
the dI/dt of the inductor, then the inductor current will tend to
track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor; therefore a smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dILOAD/dt.
Peak inductor current is shown by the next equation.
Note that COUT is much smaller in this example, 194 µF
compared to 298 µF based on a worst case load release. To
meet the two design criteria of minimum 298 µF and
maximum 16 m ESR, select one capacitor of 330 µF and
9 m ESR.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the FB
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the 250 ns
minimum off-time has expired. In extreme cases the noise
can cause three or more successive on-times. Doublepulsing will result in higher ripple voltage at the output, but in
most applications it will not affect operation. This form of
instability can usually be avoided by providing the FB pin with
a smooth, clean ripple signal that is at least 10 mVp-p, which
may dictate the need to increase the ESR of the output
capacitors. It is also imperative to provide a proper PCB
layout as discussed in the Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 13. This capacitor should be left unpopulated
until it can be confirmed that double-pulsing exists. Adding
the CTOP capacitor will couple more ripple into FB to help
eliminate the problem. An optional connection on the PCB
should be available for this capacitor.
CTOP
ILPK = Imax. + 1/2 x IRIPPLEmax.
ILPK = 6 + 1/2 x 3.7 = 7.9 A
VOUT
Rate of change of load current =
dILOAD
dt
R1
To FB pin
R2
Imax. = maximum load release = 6 A
COUT = ILPK x
I
I
L x LPK - max. x dt
VOUT dlLOAD
2 (VPK - VOUT)
Example
2A
dlLOAD
=
1 µs
dt
This would cause the output current to move from 6 A to
0 A in 3 µs, giving the minimum output capacitance
requirement shown in the following equation.
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18
Figure 13 - Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10 mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability the
ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
formula for minimum ESR is shown by the following
equation.
ESRmin. =
Figure 15 shows the magnitude of the ripple contribution due
to CL at the FB pin.
Figure 15 - FB Voltage by CL Voltage
It is shown by the following equation.
3
2 x π x COUT x fSW
Using Ceramic Output Capacitors
When the system is using high ESR value capacitors, the
feedback voltage ripple lags the phase node voltage by 90°.
Therefore, the converter is easily stabilized. When the
system is using ceramic output capacitors, the ESR value is
normally too small to meet the above ESR criteria. As a
result, the feedback voltage ripple is 180° from the phase
node and behaves in an unstable manner. In this application
it is necessary to add a small virtual ESR network that is
composed of two capacitors and one resistor, as shown in
figure 14.
VFBCL = VCL x
(R1//R2) x S x CC
(R1//R2) x S x CC + 1
Figure 16 shows the magnitude of the ripple contribution due
to the output voltage ripple at the FB pin.
Figure 16 - FB Voltage by Output Voltage
It is shown by the following equation.
VFBΔVOUT = ΔVOUT x
Figure 14 - Virtual ESR Ramp Current
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across CL and output ripple voltage.
They are defined in the following equations.
VCL =
R2
R1// 1
+ R2
S x CC
The purpose of this network is to couple the inductor current
ripple information into the feedback voltage such that the
feedback voltage has 90° phase lag to the switching node
similar to the case of using standard high ESR capacitors.
This is illustrated in figure 17.
IL x DCR (s x L/DCR + 1)
S x RL x CL + 1
ΔVOUT =
ΔIL
8C x fSW
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: [email protected]
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19
This document is subject to change without notice.
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SiC403A, SiC403BCD
Vishay Siliconix
Figure 17 - FB Voltage in Phasor Diagram
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from CL, is controlled by the
value of R1, R2 and CC. If the corner frequency of (R1//R2) x
CC is too high, the ripple magnitude at the FB pin will be
smaller, which can lead to double-pulsing. Conversely, if the
corner frequency of (R1//R2) x CC is too low, the ripple
magnitude at FB pin will be higher. Since the SiC403A/B
regulates to the valley of the ripple voltage at the FB pin, a
high ripple magnitude is undesirable as it significantly
impacts the output voltage regulation. As a result, it is
desirable to select a corner frequency for (R1//R2) x CC to
achieve enough, but not excessive, ripple magnitude and
phase margin. The component values for R1, R2, and CC
should be calculated using the following procedure.
Select CL (typical 10 nF) and RL to match with L and DCR
time constant using the following equation.
RL =
L
DCR x CL
Select CC by using the following equation.
CC ≈
1
3
x
R1//R2 2 x π x fSW
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is from
10 pF to 1 nF.
Dropout Performance
The output voltage adjustment range for continuous
conduction operation is limited by the fixed 250 ns (typical)
minimum off-time of the one-shot. When working with low
input voltages, the duty-factor limit must be calculated using
worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
DUTY =
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line and
load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions
it trips when the feedback pin is 600 mV, 1 %.
The on-time pulse from the SiC403A/B in the design
example is calculated to give a pseudo-fixed frequency of
300 kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple voltage.
Because adaptive on-time converters regulate to the valley
of the output ripple, ½ of the output ripple appears as a DC
regulation error. For example, if the output ripple is 50 mV
with VIN = 6 V, then the measured DC output will be 25 mV
above the comparator trip point.
If the ripple increases to 80 mV with VIN = 28 V, then the
measured DC output will be 40 mV above the comparator
trip. The best way to minimize this effect is to minimize the
output ripple.
The use of 1 % feedback resistors may result in up to 1 %
error. If tighter DC accuracy is required, 0.1 % resistors
should be used.
The output inductor value may change with current. This will
change the output ripple and therefore will have a minor
effect on the DC output voltage. The output ESR also affects
the output ripple and thus has a minor effect on the DC
output voltage.
Switching Frequency Variation
The switching frequency varies with load current as a result
of the power losses in the MOSFETs and DCR of the
inductor. For a conventional PWM constant-frequency
converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. An adaptive on-time converter must
also compensate for the same losses by increasing the
effective duty cycle (more time is spent drawing energy from
VIN as losses increase). The on-time is essentially constant
for a given VOUT/VIN combination, to offset the losses the offtime will tend to reduce slightly as load increases. The net
effect is that switching frequency increases slightly with
increasing load.
tON(min.)
tON(min.) x tOFF(max.)
The inductor resistance and MOSFET on-state voltage drops
must be included when performing worst-case dropout
duty-factor calculations.
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20
For technical questions, contact: [email protected]
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P1
VDD
B2
VIN_GND
B1
VIN
1
M1
1
1
1
1
1
P8 P9
VIN VIN_GND
+
1
M2
C26
1uF
C12
150uF
1
1
C27
1uF
+
C10
68uF
+
1
M3
1
+
C22
68uF
C28
0.1uF
C20
68uF
EN_PSV
1
M4
C11
0.1uF
VIN
1
6
9
10
11
34
C29
3.3nF
FBL5
SOFT 7
VDD 3
C13
0.01uF
0
R52
FBL
SOFT
VDD
VIN
VIN
VIN
VIN
VIN
P6
ENL
1
32
ENL
29 EN_PSV
EN/PSV
14
Vo
SiC403
U1
NC
12
NC
BST
8
R39 0R
lxbst
0
C6
1uF
R14
R30
26 PGD C30
31
68pF
27 ILIM
1 FB
P7
PGOOD
VDD
33 LX
25
24
23
R8 4.64K
28
130K
PGD
TON
ILIM
FB
LXS
LX
LX
LX
LX
13
R7 0R
LXBST
BST
2
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
AGND
AGND
AGND
15
16
17
18
19
20
21
22
4
30
35
R15
10K
1.5 µH
R13 100
L1
+ C16
330uF
330µF
C15
10µF
VOUT
330uF
330µF
+ C18
C25
68pF
R23
5.11k
R10
5.11k
P11
VO_GND
P10
VOUT
1
P2
TON
1
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
1
1
B4
1
1
B3
VO_GND
Vo
SiC403A, SiC403BCD
Vishay Siliconix
SIC403 EVALUATION REF BOARD (External 5 V bias)
Evaluation Board Schematic
For technical questions, contact: [email protected]
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21
This document is subject to change without notice.
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SiC403A, SiC403BCD
Vishay Siliconix
BILL OF MATERIALS
Qty.
Ref. Designator
PCB Footprint
Value
Voltage
Description
Part Number
2
C11, C14
SM0603
0.1 µF
50 V
CAP, 0.1 µF, 50 V, 0603
Generic Component
3
C10, C20, C22
593D
68 µF
20 V
68 µF TAN, 20 V, 593D, 20 %
593D686X0020D2TE3
1
C12
Radial
150 µF
35 V
CAP, Radial, 150 µF, 35 V
EU-FM1V151
1
C13
SM0402
0.01 µF
50 V
CAP, 0.01 µF, 50 V, 0402
Generic Component
1
C6
SM0603
1 µF
50 V
1 µF, 50 V.X7R.B, 0603
Generic Component
2
C16, C18
SM593D
330 µF
6.3 V
330 µF, 6.3 V, D
593D337X06R3E2
2
C25, C30
SM0402
68 pF
50 V
CAP, 68 pF, 50 V, 0402
Generic Component
2
C26, C27
SM0805
1 µF
10 V
1 µF, 10 V, 0805
Generic Component
1
C28
SM0402
0.1 µF
10 V
CAP, 0.1 µF, 10 V, 0402
Generic Component
1
C15
SM1210
10 µF
35 V
CAP, 10 µF, 35 V, 1210
Generic Component
1
C29
SM0603
3.3 nF
25 V
CAP, CER, 22 nF, 25 V
Generic Component
1
L1
IHLP4040
1.5 µH
0
1.5 µH
IHLP4040DZER1R5M01
4
M1, M2, M3, M4
0
0
0
Nylonon Standoff
8834
8
P1, P2, P6, P7, P8,
P9, P10, P11
Terminal
0
0
Test Points
1573-3
1
R7
SM0603
0
50 V
Res, 0 
Generic Component
1
R8
SM0603
4.64K
50 V
Res, 4.64K, 0603
Generic Component
1
R10
SM0603
5.11K
50 V
Res, 5.11K, 0603
Generic Component
1
R13
SM0402
100 
50 V
100 R, 50 V, 0402
Generic Component
1
R15
SM0603
10K
50 V
Res, 10K, 50 V, 0603
Generic Component
1
R23
SM0603
5.11K
50 V
Res, 5.11K, 0603
Generic Component
1
R30
SM0603
130K
50 V
Res, 130K, 0603
Generic Component
1
R39
SM0402
0
50 V
0 R, 50 V, 0402
Generic Component
1
R52
SM0603
0
50 V
RES, 31.6K, 50 V, 0603
Generic Component
1
U1
PowerPAK
MLP55-32L
0
0
6 A micro BUCK integrated Buck
Regulator with Programmable
LDO
SiC403ACD-T1-GE3/
SiC403BCD-T1GE3
4
B1, B2, B3, B4
0
0
0
BANANA JACK
575-4
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22
For technical questions, contact: [email protected]
Manufacturer
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
PACKAGE DIMENSIONS
Top View
Dim.
Millimeters
Min.
Nom.
A
0.70
A1
0.00
A2
b
Inches
Max.
Min.
Nom.
Max.
0.75
0.80
0.027
0.029
0.031
-
0.05
0.00
-
0.002
0.20 ref.
0.20
Side View
0.25
Note
8
0.008 ref.
0.30
0.078
0.098
0.110
4
Bottom View
Dim.
Millimeters
Inches
Min.
Nom.
Max.
Min.
Nom.
Max.
D2-1
3.43
3.48
3.53
0.135
0.137
0.139
D2-2
1.00
1.05
1.10
0.039
0.041
0.043
D2-3
1.00
1.05
1.10
0.039
0.041
0.043
D2-4
1.92
1.97
2.02
0.075
0.077
0.079
D
5.00 BSC
0.196 BSC
D2-5
e
0.50 BSC
0.019 BSC
E2-1
3.43
3.48
3.53
0.135
0.137
0.139
E
5.00 BSC
0.196 BSC
E2-2
1.61
1.66
1.71
0.063
0.065
0.067
E2-3
1.43
1.48
1.53
0.056
0.058
0.060
L
0.35
0.40
0.45
0.013
0.015
0.017
N
32
32
3
Nd
8
8
3
Ne
8
8
3
E2-4
0.36
0.45
0.014
0.018
Note:
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y1 4.5M - 1994.
3. N is the number of terminals
Nd is the number of terminals in X-direction and
Ne is the number of terminals in Y-direction.
4. Dimensions applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62768.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: [email protected]
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23
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
PowerPAK® MLP55-32L CASE OUTLINE
0.08 C
A
A1
D
A2
25
1
4
(5 mm x 5 mm)
Pin #1 identification
R0.200
E2 - 3
0.10
E
32L T/SLP
D2 - 2
32
24
E2 - 1
CAB
e
0.10 CB
D2 - 1
0.360
8
17
B
b
16
L
C
0.36
Top View
(Nd-1) Xe
Ref.
0.10 CA
A
E2 - 2
2x
0.45
5 6
Pin 1 dot
by marking
2x
Side View
D2 - 3
D2 - 4
(Nd-1) Xe
Ref.
D4
9
Bottom View
MILLIMETERS
INCHES
DIM
MIN.
NOM.
MAX.
MIN.
NOM.
A
0.80
0.85
0.90
0.031
0.033
0.035
A1(8)
0.00
-
0.05
0.000
-
0.002
0.30
0.078
A2
b(4)
0.20 REF.
0.20
0.25
0.008 REF.
0.098
D
5.00 BSC
0.196 BSC
e
0.50 BSC
0.019 BSC
E
5.00 BSC
L
0.35
0.40
MAX.
0.011
0.196 BSC
0.45
0.013
0.015
N(3)
32
32
Nd(3)
8
8
Ne(3)
8
0.017
8
D2 - 1
3.43
3.48
3.53
0.135
0.137
0.139
D2 - 2
1.00
1.05
1.10
0.039
0.041
0.043
D2 - 3
1.00
1.05
1.10
0.039
0.041
0.043
D2 - 4
1.92
1.97
2.02
0.075
0.077
0.079
E2 - 1
3.43
3.48
3.53
0.135
0.137
0.139
E2 - 2
1.61
1.66
1.71
0.063
0.065
0.067
E2 - 3
1.43
1.48
1.53
0.056
0.058
0.060
ECN: T-08957-Rev. A, 29-Dec-08
DWG: 5983
Notes
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Document Number: 64714
Revision: 29-Dec-08
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1
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Revision: 02-Oct-12
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Document Number: 91000