74VHC74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74VHC74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUTS during the positive going transition of the clock pulse. SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74VHC74MTR 74VHC74TTR CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 4 1/14 74VHC74 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL 1, 13 1CLR, 2CLR 2, 12 3, 11 1D, 2D 1CK, 2CK 4, 10 1PR, 2PR 5, 9 6, 8 1Q, 2Q 1Q, 2Q 7 14 GND VCC NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OUTPUTS FUNCTION CLR PR D CK Q Q L H L H L L X X X X X X L H H H L H H H L L H H H H H L H H X Qn Qn X : Don’t Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/14 CLEAR PRESET NO CHANGE 74VHC74 Table 4: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA ± 20 mA ± 25 mA ± 50 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage Value Unit 2 to 5.5 V VI Input Voltage 0 to 5.5 V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C 0 to 100 0 to 20 ns/V dt/dv Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) 1) VIN from 30% to 70% of VCC 3/14 74VHC74 Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL II ICC 4/14 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 3.0 to 5.5 2.0 3.0 to 5.5 Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 1.5 1.5 0.7VCC 0.7VCC 0.7VCC Max. V 0.5 0.5 0.5 0.3VCC 0.3VCC 0.3VCC 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 4.5 IO=-50 µA 4.4 4.5 3.0 IO=-4 mA 2.58 3.94 4.4 4.4 2.48 2.4 Unit V V 4.5 IO=-8 mA 2.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 0.1 4.5 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 4.5 IO=8 mA 0.36 0.44 0.55 0 to 5.5 VI = 5.5V or GND ± 0.1 ±1 ±1 µA 5.5 VI = VCC or GND 2 20 20 µA 3.8 3.7 V 74VHC74 Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) CL (pF) tPLH tPHL Propagation Delay Time CK to Q or Q 3.3(*) (*) (**) tW tW ts th tREM fMAX Propagation Delay Time PR or CLR to Q or Q CK Pulse Width HIGH or LOW TA = 25°C -55 to 125°C Max. Min. Max. Min. Max. 15 6.7 11.9 1.0 14.0 1.0 14.0 50 9.2 15.4 1.0 17.5 1.0 17.5 15 4.6 7.3 1.0 8.5 1.0 8.5 5.0(**) 50 6.1 9.3 1.0 10.5 1.0 10.5 3.3(*) 15 7.6 12.3 1.0 14.5 1.0 14.5 3.3(*) 50 10.1 15.8 1.0 18.0 1.0 18.0 5.0(**) 15 4.8 7.7 1.0 9.0 1.0 9.0 5.0(**) 50 6.3 9.7 1.0 11.0 1.0 11.0 3.3 Min. -40 to 85°C Typ. 5.0 tPLH tPHL Value (*) 6.0 7.0 7.0 (**) 5.0 5.0 5.0 3.3(*) 6.0 7.0 7.0 5.0(**) 5.0 5.0 5.0 Setup Time D to CK 3.3(*) HIGH or LOW 5.0(**) Hold Time D to CK 3.3(*) HIGH or LOW 5.0(**) Removal Time 3.3(*) PR or CLR to CK 5.0(**) Maximum Clock 3.3(*) Frequency 3.3(*) 6.0 7.0 7.0 5.0 5.0 5.0 0.5 0.5 0.5 0.5 0.5 0.5 5.0 5.0 5.0 3.0 3.0 3.0 PR or CLR Pulse Width LOW 3.3 5.0 15 80 125 70 70 50 50 75 45 45 5.0(**) 15 130 170 110 110 5.0(**) 50 90 115 75 75 Unit ns ns ns ns ns ns ns MHz (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V Table 8: Capacitive Characteristics Test Condition Symbol Parameter TA = 25°C VCC (V) CIN Input Capacitance 5.0 CPD Power Dissipation Capacitance (note 1) 5.0 Value Min. fIN = 10MHz Typ. Max. 7 10 25 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per flip-flop) 5/14 74VHC74 Figure 4: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) 6/14 74VHC74 Figure 6: WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) Figure 7: Waveform - Recovery Times (f=1MHz; 50% duty cycle) 7/14 74VHC74 Figure 8: Waveform - Pulse Width 8/14 74VHC74 SO-14 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.1 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 3.8 4.0 0.150 0.157 e 1.27 0.050 H 5.8 6.2 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0016019D 9/14 74VHC74 TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 10/14 74VHC74 Tape & Reel SO-14 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.4 6.6 0.252 0.260 Bo 9 9.2 0.354 0.362 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 11/14 74VHC74 Tape & Reel TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 12/14 TYP 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 74VHC74 Table 9: Revision History Date Revision 12-Nov-2004 4 Description of Changes Order Codes Revision - pag. 1. 13/14 74VHC74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. 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