Revised January 1999 MM74C165 Parallel-Load 8-Bit Shift Register General Description The MM74C165 functions as an 8-bit parallel-load, serial shift register. Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary outputs, Q7 and Q7, highest-order bit (P7) first. New serial data may be entered via the SERIAL DATA (Ds) input. Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2. Clock inputs may be used separately or together for combined clocking from independent sources. Either clock input may be used also as an active-low clock enable. To prevent double-clocking when a clock input is used as an enable, the enable must be changed to a high level (disabled) only while the clock is HIGH. Features ■ Wide supply voltage range: ■ Guaranteed noise margin: ■ High noise immunity: 3V to 15V 1V 0.45 VCC (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L ■ Parallel loading independent of clock ■ Dual clock inputs ■ Fully static operation Ordering Code: Order Number MM74165N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Connection Diagram Pin Assignments for DIP Top View © 1999 Fairchild Semiconductor Corporation DS005897.prf www.fairchildsemi.com MM74C165 Parallel-Load 8-Bit Shift Register October 1987 MM74C165 Block Diagrams *Please look into Section 8, Appendix D for availability of various package types. Truth Table State Inputs PL Clock1 Clock2 Internal Outputs Ds P0 thru P7 Q0 Q1 Q7 Q7 P7 (as enable) Parallel Load L X X X P0…P7 P0 P1 P7 Enable H L L X X P0 P1 P7 P7 Shift (with Ds) H ↑ L H X H P0 P6 P6 Shift (with Ds) H ↑ L L X L H P5 P5 Hold (Disable) H ↑ H X X L H P5 P5 X = Don’t Care H = VIN(1) L = VIN(0) ↑ = Clock transition from VIN(0) to VIN(1) P0 thru P7 = Data present (and loaded into) parallel inputs Q0 thru Q6 = Internal flip-flop outputs www.fairchildsemi.com 2 Operating VCC Range −0.3V to VCC + 0.3V Voltage at Any Pin Operating Temperature Range Storage Temperature Range (Soldering, 10 seconds) −40°C to +85°C −65°C to +150°C Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW 260°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. 18V Absolute Maximum VCC 3V to 15V Lead Temperature DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V 3.5 V VCC = 10V 8.0 V VCC = 5V 1.5 V VCC = 10V 2.0 V VCC = 5V, IO = −10 µA 4.5 V VCC = 10V, IO = −10 µA 9.0 V VCC = 5V, IO = +10 µA 0.5 V VCC = 10V, IO = +10 µA 1.0 V 1.0 µA IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V ICC Supply Current VCC = 15V 0.005 −1.0 −0.005 0.05 µA 300 µA 0.8 V CMOS TO LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VCC − 1.5 VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA V 2.4 V 0.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current VCC = 5V (P-Channel) TA = 25°C, VOUT = 0V Output Source Current VCC = 10V (P-Channel) TA = 25°C, VOUT = 0V Output Sink Current VCC = 5V (N-Channel) TA = 25°C, VOUT = VCC Output Sink Current VCC = 10V (N-Channel) TA = 25°C, VOUT = VCC 3 −1.75 −3.3 mA −8.0 −15 mA 1.75 3.6 mA 8.0 16 mA www.fairchildsemi.com MM74C165 Absolute Maximum Ratings(Note 1) MM74C165 AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol tpd0, tpd1 tpd0, tpd1 tS Typ Max Propagation Delay Time to a Logical “0” or Parameter VCC = 5V 200 400 ns Logical “1” from Clock or Load to Q or Q VCC = 10V 80 200 ns Propagation Delay Time to a Logical “0” or VCC = 5V 200 400 ns Logical “1” from H to Q or Q VCC = 10V 80 200 ns Clock Inhibit Set-up Time tS Serial Input Set-up Time tH Serial Input Hold Time tS Parallel Input Set-Up Time Conditions Min Units VCC = 5V 150 75 VCC = 10V 60 30 ns VCC = 5V 50 25 ns VCC = 10V 30 15 ns VCC = 5V 50 0 ns ns VCC = 10V 30 0 ns VCC = 5V 150 75 ns VCC = 10V 60 30 ns 0 ns tH Parallel Input Hold Time VCC = 5V 50 VCC = 10V 30 tW Minimum Clock Pulse Width VCC = 5V 70 200 ns VCC = 10V 30 100 ns VCC = 5V 85 180 ns VCC = 10V 30 90 tW Minimum Load Pulse Width fMAX Maximum Clock Frequency tr, tf Maximum Clock Rise and Fall Time VCC = 5V 0 ns ns 2.5 6 MHz VCC = 10V 5 12 MHz VCC = 5V 10 VCC = 10V 5 µs µs CIN Input Capacitance (Note 3) 5 pF CPD Power Dissipation Capacitance (Note 4) 65 pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. Switching Time Waveform Note A: The remaining six data and the serial input are LOW. Note B: Prior to test, HIGH level data is loaded into the P7 input. www.fairchildsemi.com 4 MM74C165 Logic Waveform 5 www.fairchildsemi.com MM74C165 Parallel-Load 8-Bit Shift Register Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.