Revised January 1999 CD4014BC 8-Stage Static Shift Register General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive. When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/ serial control input is in the logical “1” state, data is jammed into each stage of the register synchronously with the positive transition of the clock. All inputs are protected against static discharge with diodes to VDD and VSS. Features ■ Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 VDD (typ.) ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ 5V–10V–15V parametric ratings ■ Symmetrical output characteristics ■ Maximum input leakage: 1 µA at 15V over full temperature range Ordering Code: Order Number Package Number Package Description CD4014BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4014BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “x” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP CL Serial (Note 1) Input Parallel/ Serial PI 1 Control PI n Q1 (Internal) Qn X 1 0 0 0 0 X 1 1 0 1 0 X 1 0 1 0 1 X 1 1 1 1 1 0 0 X X 0 Qn−1 1 0 X X 1 Qn−1 X X X X Q1 Qn X = Don't care case No Change Note 1: Level change Top View © 1999 Fairchild Semiconductor Corporation DS005947.prf www.fairchildsemi.com CD4014BC 8-Stage Static Shift Register October 1987 CD4014BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) −0.5V to +18V Supply Voltage (VDD) Supply Voltage (VDD) −0.5 to VDD + 0.5V Input Voltage (VIN) −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW Symbol IDD VOL Note 3: VSS = 0V unless otherwise specified. 260°C DC Electrical Characteristics Parameter (Note 3) −40°C Conditions Min IOH IIN Max Min Max Units VDD = 5V, VIN = VDD or VSS 20 0.1 20 150 µA 40 0.2 40 300 µA VDD = 15V, VIN = VDD or VSS 80 0.3 80 600 µA 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V LOW Level VDD = 5V Output Voltage VDD = 10V HIGH Level VDD = 5V Output Voltage VDD = 10V LOW Level HIGH Level |IO| < 1 µA |IO| < 1 µA 4.95 4.95 5 4.95 V 9.95 9.95 10 9.95 V 14.95 14.95 15 14.95 V VDD = 5V, VO = 0.5V or 4.5V 1.5 2 1.5 1.5 V VDD = 10V, VO = 1.0V or 9.0V 3.0 4 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 6 4.0 4.0 VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3 3.5 V V VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 6 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 9 11.0 V LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Current (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.2 0.9 mA VDD = 15V, VO = 1.5V 3.6 3.0 8 2.4 mA HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA Current (Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.2 −0.90 mA VDD = 15V, VO = 13.5V −3.6 −3.0 −8 −2.4 mA Input Voltage IOL +85°C Typ VDD = 10V, VIN = VDD or VSS Input Voltage VIH Min Quiescent Device VDD = 15V VIL +25°C Max Current VDD = 15V VOH −40°C to +85°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 0 to VDD Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3.0V to 15V Input Voltage (VIN) Input Current VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 10−5 0.3 1.0 µA Note 4: IOL and IOH are tested one output at a time. 3 www.fairchildsemi.com CD4014BC Absolute Maximum Ratings(Note 2) (Note 3) CD4014BC AC Electrical Characteristics (Note 5) TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ Symbol tPHL, tPLH tTHL, tTLH fCL tW trCL, tfCL tS tH Parameter Propagation Delay Time Transition Time Typ Max Units VDD = 5V Conditions Min 200 320 ns VDD = 10V 80 160 ns VDD = 15V 60 120 ns VDD = 5V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns Maximum Clock VDD = 5V 2.8 4 MHz Input Frequency VDD = 10V 6 12 MHz VDD = 15V 8 16 VDD = 5V 90 180 ns Pulse Width VDD = 10V 40 80 ns VDD = 15V 25 50 ns Clock Rise and VDD = 5V 15 µs Fall Time (Note 6) VDD = 10V 15 µs VDD = 15V 15 µs Minimum Set-Up Time VDD = 5V 60 120 ns (Note 7) Serial Input VDD = 10V 40 80 ns tH ≥ 200 ns VDD = 15V 30 60 ns Parallel Inputs VDD = 5V 80 160 ns tH ≥ 200 ns VDD = 10V 40 80 ns VDD = 15V 30 60 ns Parallel/Serial Control VDD = 5V 100 200 ns tH ≥ 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns Minimum Hold Time VDD = 5V Serial In, Parallel In, tS ≥ 400 ns VDD = 10V CI MHz Minimum Clock Parallel/Serial Control VDD = 15V Average Input Capacitance Any Input 5 0 ns 10 ns 15 ns 7.5 pF (Note 8) CPD Power Dissipation Capacitance 110 pF (Note 8) Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the estimated capacitive load. Note 7: Setup times are measured with reference to clock and a fixed hold time (tH) as specified. Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note AN-90. www.fairchildsemi.com 4 CD4014BC Typical Performance Characteristics 5 www.fairchildsemi.com CD4014BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4014BC 8-Stage Static Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued)