Revised March 2002 CD4015BC Dual 4-Bit Static Shift Register General Description Features The CD4015BC contains two identical, 4-stage, serialinput/parallel-output registers with independent “Data”, “Clock,” and “Reset” inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the “Reset” input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS. ■ Wide supply voltage range: 3.0V to 18V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL: Fan out of 2 driving 74L compatibility: or 1 driving 74LS ■ Medium speed operation: 8 MHz (typ.) clock rate ■ Fully static design: @VDD − VSS = 10V Applications • Serial-input/parallel-output data queueing • Serial to parallel data conversion • General purpose register Ordering Code: Order Number Package Number Package Description CD4015BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4015BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table CL (Note 1) X D R Q1 Qn 0 0 0 Qn−1 1 0 1 Qn−1 X 0 Q1 Qn X 1 0 0 (No change) X = Don't Care Case Note 1: Level Change © 2002 Fairchild Semiconductor Corporation DS005948 www.fairchildsemi.com CD4015BC Dual 4-Bit Static Shift Register October 1987 CD4015BC Logic Diagrams Terminal No. 16 = VDD Terminal No. 8 = GND www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) −0.5 to +18 VDC DC Supply Voltage (VDD) Storage Temperature Range (TS) Input Voltage (VIN) −65°C to +150°C 700 mW Small Outline 500 mW −55°C to +125°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (TL) Note 3: VSS = 0V unless otherwise specified. 260°C (Soldering, 10 seconds) 0 to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line +3 to +15 VDC DC Supply Voltage (VDD) −0.5 to VDD +0.5 VDC Input Voltage (VIN) DC Electrical Characteristics (Note 3) Symbol IDD VOL Parameter −55°C Conditions Min VIH IOL IOH IIN Typ +125°C Max Min Max Quiescent Device VDD = 5V, VIN = VDD or VSS 5 0.005 5 150 VDD = 10V, VIN = VDD or VSS 10 0.010 10 300 VDD = 15V, VIN = VDD or VSS 20 0.015 20 600 0.05 0 0.05 0.05 0.05 0 0.05 0.05 0.05 0 0.05 0.05 LOW Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 µA HIGH Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 µA VDD = 15V VIL Min Current VDD = 15V VOH +25°C Max 4.95 4.95 5 9.95 9.95 10 9.95 14.95 14.95 15 14.95 µA V 4.95 V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 Input Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 Current (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current Units V V mA mA VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0 µA Note 4: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4015BC Absolute Maximum Ratings(Note 2) CD4015BC AC Electrical Characteristics (Note 5) TA= 25°C, CL= 50 pF, RL= 200k, tr = tf = 20 ns, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CLOCK OPERATION tPHL, tPLH tTHL, tTLH tWL, tWM trCL, tfCL tSU fCL CIN VDD = 5V 230 350 VDD = 10V 80 160 VDD = 15V 60 120 VDD = 5V 100 200 VDD = 10V 50 100 VDD = 15V 40 80 Minimum Clock VDD = 5V 160 250 Pulse-Width VDD = 10V 60 110 VDD = 15V 50 85 Propagation Delay Time Transition Time Clock Rise and VDD = 5V 15 Fall Time VDD = 10V 15 VDD = 15V 15 Minimum Data VDD = 5V 50 100 Set-Up Time VDD = 10V 20 40 VDD = 15V 15 30 Maximum Clock VDD = 5V 2 Frequency VDD = 10V 4.5 8 VDD = 15V 6 11 Input Capacitance ns ns ns µs µs 3.5 MHz Clock Input 7.5 10 Other Inputs 5 7.5 pF RESET OPERATION tPHL(R) tWH(R) VDD = 5V 200 400 VDD = 10V 100 200 VDD = 15V 80 160 Minimum Reset VDD = 5V 135 250 Pulse Width VDD = 10V 40 80 VDD = 15V 30 60 Propagation Delay Time Note 5: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com 4 ns ns CD4015BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com CD4015BC Dual 4-Bit Static Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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