Revised March 2002 CD4021BC 8-Stage Static Shift Register General Description Features The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive. ■ Wide supply voltage range: When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/ serial control is in the logical “1” state, data is jammed into each stage of the register asynchronously with the clock. 3.0V to 15V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ 5V–10V–15V parametric ratings ■ Symmetrical output characteristics ■ Maximum input leakage 1 µA at 15V over full temperature range All inputs are protected against static discharge with diodes to VDD and VSS. Ordering Code: Order Number Order Code Package Description CD4021BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4021BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Qn Parallel/ PI 1 PI n CL Q1 Serial (Note 1) Input Serial (Internal) (Note 2) Control X X 1 0 0 0 0 X X 1 0 1 0 1 X X 1 1 0 1 0 X 1 1 1 1 1 0 0 X X 0 Qn−1 1 0 X X 1 Qn−1 X 0 X X Q1 Qn X X = Don't care case Note 1: Level change Note 2: No change Top View © 2002 Fairchild Semiconductor Corporation DS005954 www.fairchildsemi.com CD4021BC 8-Stage Static Shift Register October 1987 CD4021BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 4) (Note 4) −0.5V to +18V Supply Voltage (VDD) Input Voltage (VIN) Supply Voltage (VDD) −0.5V to VDD +0.5V −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW Note 3: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. 260°C (Soldering, 10 seconds) DC Electrical Characteristics Parameter Quiescent Device Current VOL Note 4: VSS = 0V unless otherwise specified. (Note 4) −55°C Conditions Min VIH IOL IOH IIN Min +125°C Typ Max Min Max 5 0.1 5 150 VDD = 10V, VIN = V DD or VSS 10 0.2 10 300 VDD = 15V, VIN = V DD or VSS 20 0.3 20 600 0.05 0 0.05 0.05 0.05 0 0.05 0.05 0.05 0 0.05 0.05 LOW Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 µA HIGH Level VDD = 5V Output Voltage VDD = 10V |IO|< 1 µA VDD = 15V VIL +25°C Max VDD = 5V, VIN = VDD or VSS VDD = 15V VOH −55°C to +125°C CD4021BCN Dual-In-Line Lead Temperature (TL) IDD 0 to VDD Operating Temperature Range (TA) Power Dissipation (PD) Symbol 3V to 15V Input Voltage (VIN) 4.95 4.95 5 9.95 9.95 10 9.95 14.95 14.95 15 14.95 µA V 4.95 V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2 1.5 1.5 Input Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 6 4.0 4.0 HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3 3.5 Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 6 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 9 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 Current (Note 5) VDD = 10V, VO = 0.5V 1.6 1.3 2.2 0.90 VDD = 15V, VO = 1.5V 4.2 3.4 8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current (Note 5) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.2 −0.90 VDD = 15V, VO = 13.5V −4.2 −3.4 −8 −2.4 Input Current Units V V mA mA VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0 µA Note 5: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4021BC Absolute Maximum Ratings(Note 3) CD4021BC AC Electrical Characteristics (Note 6) TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ Symbol tPLH, tPHL tTHL, tTLH fCL tW trCL, tfCL ts tH Parameter Propagation Delay Time Transition Time tREM Conditions Min Max 240 350 VDD = 10V 100 175 VDD = 15V 70 140 VDD = 5V 100 200 VDD = 10V 50 100 VDD = 15V 40 80 Maximum Clock VDD = 5V 2.5 3.5 Input Frequency VDD = 10V 5 10 VDD = 15V 8 16 Units ns ns MHz Minimum Clock VDD = 5V 100 200 Pulse Width VDD = 10V 50 100 VDD = 15V 40 80 Clock Rise and VDD = 5V 15 Fall Time (Note 6) VDD = 10V 15 VDD = 15V 15 ns µs Minimum Set-Up Time Serial Input VDD = 5V 60 120 tH ≥ 200 ns VDD = 10V 40 80 (Ref. to CL) VDD = 15V 30 60 Parallel Inputs VDD = 5V 25 50 tH ≥ 200 ns VDD = 10V 15 30 (Ref. to P/S) VDD = 15V 10 20 Minimum Hold Time VDD = 5V 10 VDD = 15V 15 Minimum P/S VDD = 5V 150 250 Pulse Width VDD = 10V 75 125 VDD = 15V 50 100 Minimum P/S Removal VDD = 5V 100 200 Time (Ref. to CL) VDD = 10V 50 100 VDD = 15V 40 80 5 7.5 CI Average Input Capacitance CPD Power Dissipation ns ns 0 Serial In, Parallel In, ts ≥ 400 ns VDD = 10V Parallel/Serial Control tWH Typ VDD = 5V Any Input 100 ns ns ns pF pF Capacitance (Note 8) Note 6: AC Parameters are guaranteed by DC correlated testing. Note 7: If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the estimated capacitive load. Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note AN-90. www.fairchildsemi.com 4 CD4021BC Typical Performance Characteristics 5 www.fairchildsemi.com CD4021BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 6 CD4021BC 8-Stage Static Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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