Preliminary Revised August 2001 74LVT32373 • 74LVTH32373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary) General Description Features The LVT32373 and LVTH32373 contain thirty-two noninverting latches with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. ■ Input and output interface capability to systems at 5V VCC The LVTH32373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32373 and LVTH32373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH32373), also available without bushold feature (74LVT32373) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number Package Number Package Description 74LVT32373GX (Note 1) BGA96A (Preliminary) 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVTH32373GX (Note 1) BGA96A (Preliminary) 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 1: BGA package available in Tape and Reel only. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500548 www.fairchildsemi.com 74LVT32373 • 74LVTH32373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary) August 2001 74LVT32373 • 74LVTH32373 Preliminary Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input I0–I31 Inputs O0–O31 3-STATE Outputs FBGA Pin Assignments (Top Thru View) 1 2 3 4 5 6 A O1 O0 OE1 LE1 I0 I1 B O3 O2 GND GND I2 I3 C O5 O4 VCC1 VCC1 I4 I5 D O7 O6 GND GND I6 I7 E O9 O8 GND GND I8 I9 F O11 O10 VCC1 VCC1 I10 I11 G O13 O12 GND GND I12 I13 H O14 O15 OE2 LE2 I15 I14 J O17 O16 OE3 LE3 I16 I17 K O19 O18 GND GND I18 I19 L O21 O20 VCC2 VCC2 I20 I21 M O23 O22 GND GND I22 I23 N O25 O24 GND GND I24 I25 P O27 O26 VCC2 VCC2 I26 I27 R O29 O28 GND GND I28 I29 T O30 O31 OE4 LE4 I31 I30 Truth Table Inputs Outputs Inputs Outputs CP1 OE1 I0–I7 O0–O7 CP2 OE2 I8–I15 O8–O15 X H X Z X H X Z H L L L H L L L H L H H H L H H L X O0 L L X L Inputs Outputs Inputs O0 Outputs CP3 OE3 I16–I23 O16–O23 CP4 OE4 I24–I31 O24–O31 X H X Z X H X Z H L L L H L L L H L H H H L H H L L X L X O0 H = HIGH Voltage Level L = LOW Voltage Level O0 X = Immaterial L Z = HIGH Impedance Oo = Previous Oo prior to HIGH-to-LOW transition of LE Functional Description The LVT32373 and LVTH32373 contain thirty-two D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 32-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. www.fairchildsemi.com 2 Preliminary 74LVT32373 • 74LVTH32373 Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Byte 3 (16:23) Byte 4 (24:31) VCC1 is associated with Bytes 1 and 2. VCC2 is associated with Bytes 3 and 4. Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVT32373 • 74LVTH32373 Preliminary Absolute Maximum Ratings(Note 2) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH Level Output Current IOL LOW Level Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Units 2.7 3.6 V 0 5.5 V −32 mA 64 mA −40 85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC Parameter (V) T A = −40°C to +85°C Min Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 Output LOW Voltage Bushold Input Minimum Drive II(OD) Bushold Input Over-Drive (Note 4) Current to Change State II Input Current Data Pins IOFF Power Off Leakage Current IPU/PD Power up/down 3-STATE 0.8 II = −18 mA V VO ≤ 0.1V or V VO ≥ VCC − 0.1V IOH = −8 mA IOH = −32 mA 0.5 3.0 0.4 3.0 0.5 3.0 0.55 75 IOL = 100 µA IOL = 24 mA V 500 IOL = 64 mA µA −500 10 3.6 ±1 −5 VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V µA VI = 0V or VCC VI = 0V VI = VCC 1 ±100 IOL = 16 mA IOL = 32 mA µA −75 3.6 0 Conditions V IOH = −100 µA 2.7 3.6 Units V 0.2 3.0 Control Pins 2.0 2.7 3.0 (Note 4) Max −1.2 VIK µA 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V 0–1.5V ±100 µA IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V Output Current www.fairchildsemi.com 4 VI = GND or VCC Preliminary Symbol (Continued) VCC Parameter T A = −40°C to +85°C (V) Min Units Conditions Max ICCH Power Supply Current (VCC1 or VCC2) 3.6 0.19 mA ICCL Power Supply Current (VCC1 or VCC2) 3.6 5 mA Outputs HIGH Outputs LOW ICCZ Power Supply Current (VCC1 or VCC2) 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current (VCC1 or VCC2) 3.6 0.19 mA VCC ≤ VO ≤ 5.5V, Outputs Disabled ∆ICC Increase in Power Supply Current (VCC1 or VCC2) 3.6 0.2 One Input at V CC − 0.6V mA Other Inputs at VCC or GND (Note 7) Note 4: Applies to bushold versions only (74LVTH32373). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 8) TA = 25°C VCC (V) Min Typ Conditions Units Max CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 9) Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = −40°C to +85°C, CL= 50pF, RL= 500Ω Symbol Parameter VCC = 3.3V ± 0.3V Min Max VCC = 2.7V Min Units Max tPHL Propagation Delay 1.5 3.9 1.5 4.3 tPLH Dn to On 1.5 3.8 1.5 4.2 tPHL Propagation Delay 1.9 4.2 1.9 4.4 tPLH LE to On 1.6 4.3 1.6 4.8 tPZL Output Enable Time tPZH tPLZ Output Disable Time tPHZ 1.3 4.3 1.3 4.9 1.0 4.3 1.0 5.1 1.5 4.7 1.5 4.8 2.0 5.0 2.0 5.4 ns ns ns ns tS Setup Time, Dn to LE 1.0 0.8 ns tH Hold Time, Dn to LE 1.0 1.1 ns tW LE Pulse Width 3.0 3.0 ns Capacitance (Note 10) Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC Conditions 4 pF COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVT32373 • 74LVTH32373 DC Electrical Characteristics 74LVT32373 • 74LVTH32373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary) Preliminary Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Preliminary Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6