Revised February 2005
74ACTQ00
Quiet Series¥ Quad 2-Input NAND Gate
General Description
Features
The ACTQ00 contains four 2-input NAND gates and utilizes Fairchild FACT Quiet Series¥ technology to guarantee quiet output switching and improve dynamic threshold
performance FACT Quiet Series features GTO¥ output
control and undershoot corrector in addition to a split
ground bus for superior ACMOS performance.
■ ICC reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
■ Has TTL-compatible inputs
Ordering Code:
Order Number
Package Number
74ACTQ00SC
74ACTQ00MTC
74ACTQ00PC
M14A
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
An, Bn
Inputs
On
Outputs
FACT¥, Quiet Series¥, FACT Quiet Series¥, and GTO¥ are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010888
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74ACTQ00 Quiet Series¥ Quad 2-Input NAND Gate
August 1990
74ACTQ00
Absolute Maximum Ratings(Note 1)
0.5V to 7.0V
Supply Voltage (VCC)
VI
0.5V
VCC 0.5V
20 mA
20 mA
0.5V to VCC 0.5V
DC Input Voltage (VI)
Recommended Operating
Conditions
Supply Voltage (VCC)
DC Output Diode Current (IOK)
VO
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
140qC
PDIP
DC Input Diode Current (IIK)
VI
r300 mA
or Sink Current
Junction Temperature (TJ)
20 mA
20 mA
0.5V to VCC 0.5V
per Output Pin (ICC or IGND)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
r50 mA
VIN from 0.8V to 2.0V
125 mV/ns
VCC @ 4.5V, 5.5V
DC VCC or Ground Current
Storage Temperature (TSTG)
0V to VCC
Output Voltage (VO)
Minimum Input Edge Rate ('V/'t)
DC Output Source
or Sink Current (IO)
4.5V to 5.5V
Input Voltage (VI)
r50 mA
65qC to 150qC
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation outside databook specifications.
DC Latch-up Source
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
VCC
TA
(V)
Typ
25qC
40qC to 85qC
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
3.86
3.76
4.5
5.5
VOL
TA
Units
Conditions
Guaranteed Limits
V
V
VOUT
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
50 PA
V
IOUT
VIN
VIL or VIH
V
IOH
24 mA
24 mA (Note 2)
4.86
4.76
IOH
Maximum LOW Level
4.5
0.001
0.1
0.1
IOUT
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r0.1
r1.0
PA
VI
VCC, GND
VCC 2.1V
V
V
50 PA
VIN
VIL or VIH
IOL
24 mA
IOL
24 mA (Note 2)
IIN
Maximum Input Leakage Current
ICCT
Maximum ICC/Input
5.5
1.5
mA
VI
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 3)
5.5
75
mA
VOHD
ICC
Maximum Quiescent Supply Current
5.5
20.0
PA
VIN
VOLP
Quiet Output Maximum Dynamic
5.0
0.6
2.0
1.1
1.5
V
VOL
VOLV
Quiet Output Minimum Dynamic
VOL
VIHD
Minimum HIGH Level
1.65V Max
3.85V Min
VCC or GND
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
5.0
0.6
1.2
V
5.0
1.9
2.2
V
(Note 4)(Note 6)
5.0
1.2
0.8
V
(Note 4)(Note 6)
(Note 4)(Note 5)
Dynamic Input Voltage
VILD
Maximum LOW Level
Dynamic Input Voltage
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f 1 MHz.
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2
Symbol
tPLH
Parameter
Propagation Delay
Data to Output
Propagation Delay
tPHL
Data to Output
tOSHL
Output to Output
tOSLH
Skew (Note 8)
VCC
TA
25qC
(V)
CL
50 pF
(Note 7)
Min
5.0
5.0
40qC to 85qC
CL
50 pF
Units
Max
Min
Max
2.0
7.5
2.0
8.0
ns
2.0
7.5
2.0
8.0
ns
1.0
ns
5.0
Typ
TA
0.5
1.0
Note 7: Voltage Range 5.0 is 5.0V r 0.5V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC
OPEN
CPD
Power Dissipation Capacitance
74
pF
VCC
5.0V
3
Conditions
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74ACTQ00
AC Electrical Characteristics
74ACTQ00
FACT¥ Noise Characteristics
VOLP/VOLV and VOHP/VOHV:
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50: coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
VILD and VIHD:
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500:.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the word generator channels
before testing. This will ensure that the outputs switch
simultaneously.
• Monitor one of the switching outputs using a 50: coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope
• Next decrease the input HIGH voltage level.VIH until the
output begins to oscillate or steps out a mine of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
Note 9: VOHV and VOLP are measured with respect to ground reference.
Note 10: Input pulses have the following characteristics: f
3 ns, tf 3 ns, skew 150 ps.
1 MHz, tr
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
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4
74ACTQ00
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
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74ACTQ00
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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6
74ACTQ00 Quiet Series¥ Quad 2-Input NAND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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