Si4906DY Vishay Siliconix Dual N-Channel 40-V (D-S) MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) ID (A)a 0.039 at VGS = 10 V 6.6 0.050 at VGS = 4.5 V 5.8 VDS (V) N-Channel 40 Qg (Typ.) 6.6 • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg and UIS Tested • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • CCFL Inverter D1 SO-8 S1 1 8 D1 G1 2 7 D1 S2 3 6 D2 G2 4 5 D2 D2 G1 G2 Top View Ordering Information: Si4906DY-T1-E3 (Lead (Pb)-free) Si4906DY-T1-GE3 (Lead (Pb)-free and Halogen-free) S1 S2 N-Channel MOSFET N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C) Symbol VDS VGS TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C ID IDM Pulsed Drain Current (10 µs Pulse Width) Source-Drain Current Diode Current Limit 40 ± 16 6.6 5.3 5.3b, c 4.2b, c 30 2.5 1.7b, c 30 13 8.5 3.1 2 TC = 25 °C TA = 25 °C Pulsed Sorce-Drain Current Single Pulse Avalanche Current Single-Pulse Avalanche Energy L = 0.1 mH Maximum Power Dissipation TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C IS ISM IAS EAS PD 2b, c 1.28b, c - 55 to 150 TJ, Tstg Operating Junction and Storage Temperature Range Unit V A mJ W °C THERMAL RESISTANCE RATINGS Limit Parameter Maximum Junction-to-Ambientb, d Maximum Junction-to-Foot (Drain) t ≤ 10 s Steady State Symbol RthJA RthJF Typical 52 32 Maximum 62.5 40 Unit °C/W Notes: a. Based on TC = 25 °C. b. Surface Mounted on 1" x 1" FR4 board. c. t = 10 s. d. Maximum under Steady State conditions is 110 °C/W. Document Number: 73867 S09-2432-Rev. C, 16-Nov-09 www.vishay.com 1 Si4906DY Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VGS(th) Temperature Coefficient Symbol Test Conditions Min. VDS VGS = 0 V, ID = 250 µA 40 ΔVDS/TJ ΔVGS(th)/TJ VGS(th) VDS = VGS, ID = 250 µA IGSS VDS = 0 V, VGS = ± 16 V Zero Gate Voltage Drain Current IDSS On-State Drain Currentb ID(on) Gate Threshold Voltage Drain-Source On-State Resistanceb RDS(on) Forward Transconductanceb Dynamica Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time gfs tr mV/°C - 4.6 0.8 2.2 V 100 nA VDS = 40 V, VGS = 0 V 1 10 VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 5 A 20 0.039 VGS = 4.5 V, ID = 4 A 0.041 0.050 VDS = 15 V, ID = 5 A 15 Ω S 625 VDS = 20 V, VGS = 0 V, f = 1 MHz 88 pF 50 VDS = 20 V, VGS = 10 V, ID = 5 A 14.4 22 6.6 10 VDS = 20 V, VGS = 4.5 V, ID = 5 A 1.6 f = 1 MHz 2.3 3.5 9 15 nC 2.3 VDD = 20 V, RL = 4 Ω ID ≅ 5 A, VGEN = 10 V, Rg = 1 Ω 51 77 21 32 tf 6 10 13 20 tr µA A 0.032 td(on) td(off) Unit V VDS = 40 V, VGS = 0 V, TJ = 55 °C td(on) td(off) Max. 40 ID = 250 µA Gate-Body Leakage Typ.a VDD = 20 V, RL = 4 Ω ID ≅ 5 A, VGEN = 4.5 V, Rg = 1 Ω tf 85 128 17 26 7 11 Ω ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulse Diode Forward Currenta Body Diode Voltage IS TC = 25 °C 2.5 ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb 30 IS = 1.7 A IF = 1.7 A, dI/dt = 100 A/µs, TJ = 25 °C A 0.79 1.2 V 30 45 ns 30 45 nC 17 13 ns Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 73867 S09-2432-Rev. C, 16-Nov-09 Si4906DY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 30 2.0 VGS = 10 V thru 4 V 1.6 I D - Drain Current (A) I D - Drain Current (A) 24 18 12 3V 1.2 0.8 TC = 125 °C 6 0.4 25 °C - 55 °C 0 0.0 0.5 1.0 1.5 2.0 0.0 0.0 2.5 0.8 VDS - Drain-to-Source Voltage (V) 2.4 3.2 4.0 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.060 900 0.052 720 Ciss C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 1.6 VGS = 4.5 V 0.044 0.036 VGS = 10 V 540 360 Coss 0.028 180 0.020 0 Crss 0 4 8 12 16 20 0 6 ID - Drain Current (A) 12 24 30 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 10 1.8 ID = 5 A ID = 5 A 8 VDS = 30 V 6 VDS = 20 V 4 1.5 VGS = 10 V (Normalized) VDS = 10 V R DS(on) - On-Resistance VG S - Gate-to-Source Voltage (V) 18 VGS = 4.5 V 1.2 0.9 2 0 0 3 6 9 Qg - Total Gate Charge (nC) Gate Charge Document Number: 73867 S09-2432-Rev. C, 16-Nov-09 12 15 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature www.vishay.com 3 Si4906DY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.30 RDS(on) - Drain-to-Source On-Resistance (Ω) I S - Source Current (A) 100 10 TJ = 150 °C 25 °C 1 0.24 0.18 0.12 125 °C 0.06 25 °C 0.00 0.1 0.0 0.2 0.6 0.4 0.8 1.0 0 1.2 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) VSD - Source-to-Drain Voltage (V) On-Resistance vs. Gate-to-Source Voltage Source-Drain Diode Forward Voltage 0.4 100 ID = 250 µA 0.0 80 Power (W) VGS(th) Variance (V) 0.2 ID = 5 mA - 0.2 - 0.4 - 0.6 - 50 60 40 20 - 25 0 25 50 75 100 125 150 0 0.001 0.01 0.1 1 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 10 100 Limited by RDS(on)* I D - Drain Current (A) 10 1 ms 1 10 ms 100 ms 0.1 0.01 0.1 TA = 25 °C Single Pulse 1s 10 s DC 1 100 10 VDS - Drain-to-Source Voltage (V) minimum VGS at which RDS(on) is specified * VGS Safe Operating Area, Junction-to-Ambient www.vishay.com 4 Document Number: 73867 S09-2432-Rev. C, 16-Nov-09 Si4906DY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 8 I D - Drain Current (A) 6 5 3 2 0 0 25 50 75 100 125 150 TC - Case Temperature (°C) 4.0 1.5 3.2 1.2 2.4 0.9 Power (W) Power (W) Current Derating* 1.6 0.8 0.6 0.3 0.0 0.0 0 25 50 75 100 125 150 0 25 50 75 100 125 TC - Case Temperature (°C) TA - Ambient Temperature (°C) Power Derating, Junction-to-Foot Power Derating, Junction-to-Ambient 150 * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 73867 S09-2432-Rev. C, 16-Nov-09 www.vishay.com 5 Si4906DY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 PDM 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 120 °C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10-3 10-1 10-2 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73867. www.vishay.com 6 Document Number: 73867 S09-2432-Rev. C, 16-Nov-09 Package Information Vishay Siliconix SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 6 7 5 E 1 3 2 H 4 S h x 45 D C 0.25 mm (Gage Plane) A e B All Leads q A1 L 0.004" MILLIMETERS INCHES DIM Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.20 0.004 0.008 B 0.35 0.51 0.014 0.020 C 0.19 0.25 0.0075 0.010 D 4.80 5.00 0.189 0.196 E 3.80 4.00 0.150 e 0.101 mm 1.27 BSC 0.157 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.50 0.93 0.020 0.037 q 0° 8° 0° 8° S 0.44 0.64 0.018 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Document Number: 71192 11-Sep-06 www.vishay.com 1 VISHAY SILICONIX TrenchFET® Power MOSFETs Application Note 808 Mounting LITTLE FOOT®, SO-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.288 7.3 0.050 1.27 0.196 5.0 0.027 0.69 0.078 1.98 0.2 5.07 Figure 1. Single MOSFET SO-8 Pad Pattern With Copper Spreading Document Number: 70740 Revision: 18-Jun-07 0.050 1.27 0.088 2.25 0.088 2.25 0.027 0.69 0.078 1.98 0.2 5.07 Figure 2. Dual MOSFET SO-8 Pad Pattern With Copper Spreading The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. www.vishay.com 1 APPLICATION NOTE In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. 0.288 7.3 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-8 0.172 (4.369) 0.028 0.022 0.050 (0.559) (1.270) 0.152 (3.861) 0.047 (1.194) 0.246 (6.248) (0.711) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 22 Document Number: 72606 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000