SI4812BDY-T1-E3

Si4812BDY
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET with Schottky Diode
FEATURES
MOSFET PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
30
ID (A)
0.016 at VGS = 10 V
9.5
0.021 at VGS = 4.5 V
7.7
• Halogen-free According to IEC 61249-2-21
Available
• LITTLE FOOT® Plus Power MOSFET
• 100 % Rg Tested
SCHOTTKY PRODUCT SUMMARY
VDS (V)
30
VSD (V)
Diode Forward Voltage
IF (A)
0.50 V at 1.0 A
1.4
SO-8
D
S
1
8
D
S
2
7
D
S
3
6
D
G
4
5
D
Schottky Diode
G
N-channel MOSFET
Top View
Ordering Information: Si4812BDY-T1-E3 (Lead (Pb)-free)
Si4812BDY-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Limit
Parameter
Symbol
Drain-Source Voltage (MOSFET)
Reverse Voltage (Schottky)
Gate-Source Voltage (MOSFET)
10 s
VDS
VGS
Continuous Drain Current (TJ = 150 °C) (MOSFET)a, b
TA = 25 °C
TA = 70 °C
Pulsed Drain Current (MOSFET)
Continuous Source Current (MOSFET Diode
Average Forward Current (Schottky)
Pulsed Forward Current (Schottky)
Single Pulse Avalanche Current
Avalanche Energy
Conduction)a, b
Maximum Power Dissipation (MOSFET)a, b
Maximum Power Dissipation (Schottky)a, b
L = 0.1 mH
TA = 25 °C
TA = 70 °C
TA = 25 °C
TA = 70 °C
ID
IDM
IS
IF
IFM
IAS
EAS
PD
9.5
7.7
Unit
V
7.3
5.9
50
2.1
1.4
1.2
0.8
30
5
1.25
2.5
1.6
2.0
1.3
TJ, Tstg
Operating Junction and Storage Temperature Range
Steady State
30
30
± 20
A
mJ
1.4
0.9
1.2
0.8
- 55 to 150
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient (t ≤ 10 s)a
Maximum Junction-to-Ambient (t = Steady
State)a
Maximum Junction-to-Foot (t = Steady State)a
Device
MOSFET
Schottky
MOSFET
Schottky
MOSFET
Schottky
Symbol
RthJA
RthJF
Typical
40
50
72
85
18
24
Maximum
50
60
90
100
23
30
Unit
°C/W
Notes:
a. Surface Mounted on FR4 board.
b. t ≤ 10 s.
Document Number: 73038
S-83039-Rev. D, 29-Dec-08
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1
Si4812BDY
Vishay Siliconix
MOSFET AND SCHOTTKY SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VGS(th)
VDS = VGS, ID = 250 µA
1
IGSS
VDS = 0 V, VGS = ± 20 V
Typ.
Max.
Unit
3
V
± 100
nA
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
(MOSFET and Schottky)
On-State Drain Currenta
Drain-Source On-State Resistancea
Forward Transconductancea
Schottky Diode Forward Voltagea
IDSS
VDS = 30 V, VGS = 0 V
0.004
0.100
VDS = 30 V, VGS = 0 V, TJ = 100 °C
0.7
10
VDS = 30 V, VGS = 0 V, TJ = 125 °C
3.0
20
VDS ≥ 5 V, VGS = 10 V
ID(on)
RDS(on)
gfs
VSD
20
mA
A
VGS = 10 V, ID = 9.5 A
0.013
0.016
VGS = 4.5 V, ID = 7.7 A
0.0165
0.021
VDS = 15 V, ID = 9.5 A
45
IS = 1.0 A, VGS = 0 V
0.45
0.50
IS = 1.0 A, VGS = 0 V, TJ = 125 °C
0.33
0.42
8.5
13
Ω
S
V
Dynamicb
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
VDS = 15 V, VGS = 5 V, ID = 9.5 A
0.3
td(on)
tr
td(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
nC
3
2.6
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
IF = 1.0 A, dI/dt = 100 A/µs
0.7
1.1
15
25
13
20
20
30
8
15
22
35
Ω
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 73038
S-83039-Rev. D, 29-Dec-08
Si4812BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
50
VGS = 10 thru 4 V
40
I D - Drain Current (A)
I D - Drain Current (A)
40
30
20
10
30
20
TC = 125 °C
10
25 °C
3V
- 55 °C
0
0
1
2
3
4
0
0.0
5
0.5
VDS - Drain-to-Source Voltage (V)
1.0
2.5
3.0
3.5
4.0
Transfer Characteristics
1300
0.030
Ciss
0.025
C - Capacitance (pF)
1040
0.020
VGS = 4.5 V
VGS = 10 V
0.015
0.010
780
520
Coss
260
0.005
Crss
0
0.000
0
10
20
30
40
50
0
60
5
10
15
20
25
30
VDS - Drain-to-Source Voltage (V)
ID - Drain Current (A)
On-Resistance vs. Drain Current
Capacitance
1.6
6
VDS = 15 V
ID = 9.5 A
5
1.4
R DS(on) - On-Resistance
(Normalized)
V GS - Gate-to-Source Voltage (V)
2.0
VGS - Gate-to-Source Voltage (V)
Output Characteristics
RDS(on) - On-Resistance (Ω)
1.5
4
3
2
VGS = 10 V
ID = 9.5 A
1.2
1.0
0.8
1
0
0
2
4
6
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 73038
S-83039-Rev. D, 29-Dec-08
8
10
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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Si4812BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
0.05
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
TJ = 150 °C
10
TJ = 25 °C
1
0.04
ID = 9.5 A
0.03
0.02
0.01
0.00
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
2
1
40
30 V
Power (W)
I R - Reverse Current (mA)
50
0.01
10
30
20
20 V
10
10 V
0.0001
0.00001
8
On-Resistance vs. Gate-to-Source Voltage
10
0.001
6
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
0.1
4
0
0
25
50
75
100
125
150
0.01
0.1
1
10
100
TJ - Junction Temperature (°C)
Time (s)
Reverse Current (Schottky)
Single Pulse Power (MOSFET)
600
100
Limited by
RDS(on)*
I D - Drain Current (A)
10
1 ms
10 ms
1
100 ms
0.1
0.01
0.1
1s
10 s
TC = 25 °C
Single Pulse
1
DC
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Case
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Document Number: 73038
S-83039-Rev. D, 29-Dec-08
Si4812BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = R thJA = 72 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse
0.01
10-4
4. Surface Mounted
10-3
10-2
10-1
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient (MOSFET)
2
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = R thJA = 85 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse
0.01
10-4
10-3
4. Surface Mounted
10-2
10-1
1
10
30
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient (Schottky)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73038.
Document Number: 73038
S-83039-Rev. D, 29-Dec-08
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Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72606
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000