TA4500F TOSHIBA Bipolar Linear Integrated Circuit SiGe Monolithic TA4500F 1.9 GHz Band RX Front-End IC PHS, Digital Cordless Telecommunication Applications Features • Low-noise amplifier / down-conversion mixer • Integrated local buffer amplifier • Single positive power supply: VCC = 3.0 V • Large conversion gain: GLNA = 17.5 dB (typ.) • High input IP3: GMIX = 5.0 dB (typ.) IIP3LNA = -7.5 dBmW (typ.) QS16 IIP3MIX = 7.0 dBmW (typ.) • High 1/2 IF reduction ratio: 1/2IFRMIX = 45 dB (typ.) • Small package: Weight: 0.0065 g (typ.) QS16 (2.5 mm × 2.5 mm × 0.55 mm) Absolute Maximum Ratings (Ta = 25°C) Characteristic Symbol Rating Unit VCC (Note 1) 4.5 V PIN (RF_IN) 10 dBmW PIN (LO_IN) 0 dBmW PIN (MIX_IN) 0 dBmW Pd (Note 2) 500 mW Operating temperature range Topr −40 to +85 °C Storage temperature range Tstg −55 to +150 °C Supply voltage Input power Power dissipation Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: VCC = VCC1 = VCC2 = VCC3 Note 2: When mounted on a 30 mm × 35 mm × 0.6 mm FR4 substrate at Ta = 25°C (double-sided substrate: the reverse side is ground connection) Caution This device is sensitive to electrostatic discharge. When handling this product, ensure that the environment is protected against electrostatic discharge by using an earth strap, a conductive mat and an ionizer. 1 2007-11-01 TA4500F Electrical Characteristics VCC = 3.0 V, Ta = 25°C, Zg = Zl = 50 Ω Characteristic Symbol Test Condition Min Typ Max Unit f ⎯ 1.884 ⎯ 1.920 GHz Operating supply voltage VCC ⎯ 2.7 3.0 3.3 V Supply current ICC ⎯ 15.0 22.0 mA 15.0 17.5 22.0 dB Total Operating frequency pRF_IN = pLO_IN = pMIX_IN = 0 mW (no signal) Low Noise Amplifier (LNA) Block Power gain GLNA fRF_IN = 1.9 GHz, pRF_IN = -35 dBmW Noise figure NFLNA Measured at 1.9 GHz Input IP3 IIP3LNA (Note 3) ⎯ 2.2 3.0 dB -13.5 -7.5 ⎯ dBmW Down Conversion Mixer (MIX) Block Conversion gain GMIX fMIX_IN = 1.9 GHz, pMIX_IN = -25 dBmW, fLO_IN = 1.66 GHz, pLO_IN = -15 dBmW, measured at IF_OUT1, IF_OUT2 terminated via 50 Ω and vice versa 2.8 5.0 7.0 dB Noise figure NFMIX fLO_IN = 1.66 GHz, pLO_IN = -15 dBmW, measured at IF_OUT1, IF_OUT2 terminated via 50 Ω and vice versa, fIF_OUT = 240 MHz, DSB (Note 4) ⎯ 13.0 17.5 dB Input IP3 IIP3MIX fLO_IN = 1.66 GHz, pLO_IN = -15 dBmW, measured at IF_OUT1, IF_OUT2 terminated via 50 Ω and vice versa (Note 5) -1.0 7.0 ⎯ dBmW 1/2IFRMIX fMIX_IN = 1.9 GHz, 1.78 GHz, pMIX_IN = -25 dBmW, fLO_IN = 1.66 GHz, pLO_IN = -15 dBmW, measured at IF_OUT1, IF_OUT2 terminated via 50 Ω and vice versa, fIF_OUT = 240 MHz ⎯ 45.0 ⎯ dB PLK fLO_IN = 1.66 GHz, pLO_IN = -15 dBmW, measured at MIX_IN, IF_OUT1, 2 terminated via 50 Ω ⎯ -40.0 ⎯ dBmW 1/2 IF reduction ratio Local leak power Note 3: IIP3 of the LNA block is converted from IM3 when RF1 = 1.900 GHz / −35 dBmW, RF2 = 1.9006 GHz / −35 dBmW are input to RF_IN. Note 4: Measured with the high pass filter shown below connected to MIX_IN. -0.8 dB 2.4 pF 12 nH 4.7 nH |S21| 2 2.4 pF 12 nH 10 dB / 100 MHz 850 MHz Frequency Note 5: IIP3 of the MIX block is converted from IM3 when RF1 = 1.900 GHz / −25 dBmW, RF2 = 1.9006 GHz / −25 dBmW are input to MIX_IN. Note 6: All tests for electrical characteristics are performed using the test board shown on page 4. 2 2007-11-01 TA4500F Block Diagram and Marking (Top View) 12 9 12 9 Product marking 13 8 8 13 MD 16 5 16 5 Monthly dot marking 1 4 1 4 Year dot marking Pin 1 marking Pin Configuration Pin number Pin name Description 1 N.C. 2 LO_term 3 LO_IN MIX local input 4 GND1 Ground. 5 GND2 Ground. 6 VCC2 7 IF_OUT2 MIX IF output. Biasing circuit is necessary. 8 IF_OUT1 MIX IF output. Biasing circuit is necessary. 9 MIX_IN 10 VCC1 11 LNA_ind 12 LNA_OUT 13 GND3 Ground. 14 RF_IN LNA input. 15 GND4 Ground. 16 VCC3 Not connected to the pellet. Connect to ground. MIX local input termination pin. To be terminated. Supply pin for MIX. MIX RF input. Supply pin for LNA and biasing circuits. LNA emitter. Connect to ground via 1 nH inductance // 1 pF capacitance. LNA output. Biasing circuit is necessary. Supply pin for MIX. 3 2007-11-01 TA4500F Circuit Diagram of Test Board C13 LNA_OUT, f=1.9GHz C14 C12 MIX_IN, f=1.9GHz C11 L8 L9 L6 C5 VCC=3.0V L7 C4 C3 L3 C8 RF_IN, f=1.9GHz C15 C10 L5 IF_OUT1, f=240MHz L10 C7 L2 IF_OUT2, f=240MHz L4 C9 VCC=3.0V VCC=3.0V C1 C6 C2 R1 L1 LO_IN, f=1.66GHz List of External Chip Components Part Value Chip Series C1 1000 pF GRM15 series MURATA Decoupling capacitor C2 1000 pF GRM15 series MURATA Decoupling capacitor C3 1000 pF GRM15 series MURATA Decoupling capacitor C4 1000 pF GRM15 series MURATA Decoupling capacitor C5 1000 pF GRM15 series MURATA Decoupling capacitor C6 1000 pF GRM15 series MURATA Decoupling capacitor C7 1000 pF GRM15 series MURATA DC blocking capacitor C8 1000 pF GRM15 series MURATA DC blocking capacitor C9 5 pF GRM15 series MURATA IF_OUT matching C10 5 pF GRM15 series MURATA IF_OUT matching C11 39 pF GRM15 series MURATA MIX_IN matching C12 1 pF GRM15 series MURATA Determining LNA gain C13 82 pF GRM15 series MURATA LNA_OUT matching C14 1.2 pF GRM15 series MURATA LNA_OUT matching C15 3 pF GRM15 series MURATA RF_IN matching L1 8.2 nH LQG15HN series MURATA LO_IN matching L2 120 nH LQG15HN series MURATA MIX output load L3 120 nH LQG15HN series MURATA MIX output load L4 120 nH LQG15HN series MURATA IF_OUT matching L5 120 nH LQG15HN series MURATA IF_OUT matching L6 8.2 nH LQG15HN series MURATA MIX_IN matching L7 1 nH LQG15HN series MURATA Determining LNA gain L8 10 nH LQG15HN series MURATA LNA_OUT matching L9 15 nH LQG15HN series MURATA LNA output load L10 6.8 nH LQG15HN series MURATA LNA_IN matching R1 51 Ω ROHM LO termination load MCR01 series Description 4 2007-11-01 TA4500F Typical Operating Characteristics of Low-Noise Amplifier Block LNA Block POUT(1-,2-tone),PIM3 vs PIN V CC = 3 V, Ta = 25 °C, RF1 = 1.9000 GHz, RF2 = 1.9006 GHz for 2-tone, IM3 measurement 20 0 POUT(dBmW) POUT (1-tone) -20 POUT (2-tone) -40 PIM3 -60 POUT(1-tone) [dBmW] -80 POUT(2-tone) [dBmW] PIM3 [dBmW]) -100 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 PIN (dBmW) LNA Block GLNA , IIP3LNA , NFLNA vs Temperature V CC = 3 V, RF1 = 1.9000 GHz/-35 dBmW, RF2 = 1.9006 GHz/-35 dBmW for IIP3 measurement 16.6 2.75 GLNA 16.4 2.5 2.25 16.2 2 16.0 NFLNA 15.8 1.75 1.5 -7.2 15.6 1.25 -7.5 15.4 15.2 1 IIP3LNA -7.8 15.0 0.75 -8.1 14.8 0.5 -8.4 14.6 0.25 -8.7 14.4 -60 -40 -20 0 20 40 60 80 0 100 IIP3 (dBmW) Gain (dB) NF (dB) 3 16.8 GLNA [dB] NFLNA [dB] IIP3LNA [dBmW]) -9.0 Ta (°C) LNA Block GLNA , IIP3 LNA , NFLNA vs VCC Ta = 25 °C, RF1 = 1.9000 GHz/-35 dBmW, RF2 = 1.9006 GHz/-35 dBmW for IIP3 measurement 16.60 2.75 GLNA 16.50 2.5 16.45 2 16.35 1.75 1.5 -7.3 16.30 16.25 1.25 -7.4 IIP3LNA -7.5 16.20 1 16.15 0.75 -7.6 16.10 0.5 -7.7 16.05 0.25 -7.8 16.00 0 2.0 2.5 3.0 3.5 4.0 4.5 IIP3 (dBmW) Gain (dB) 2.25 NFLNA 16.40 NF (dB) 3 16.55 GLNA [dB] NFLNA [dB] IIP3LNA [dBmW]) -7.9 5.0 VCC (V) 5 2007-11-01 TA4500F Typical Operating Characteristics of Down Conversion Mixer Block MIX Block POUT(1-,2-tone),PIM3 , P1/2IF vs PIN V CC = 3 V,Ta = 25 °C, LO = 1.66 GHz/-15dBmW, RF1 = 1.9000 GHz, 1.7800 GHz, RF2 = 1.9006 GHz for 2-tone, IM3 measurement 0 -10 POUT (1-tone) -20 POUT (2-tone) POUT(dBmW) -30 -40 -50 -60 P1/2IF -70 POUT(1-tone) [dBmW] PIM3 POUT(2-tone) [dBmW] -80 PIM3 [dBmW]) -90 P1/2IF [dBmW] -100 -40 -35 -30 -25 -20 -15 -10 -5 0 PIN (dBmW) MIX Block GMIX, IIP3 MIX, NFMIX vs Temperature V CC = 3 V, LO = 1.66 GHz/-15 dBmW, RF1 = 1.9000 GHz/-25 dBmW, RF2 = 1.9006 GHz/-25 dBmW for IIP3 measurement 14 GMIX Gain (dB) 5.8 13 NFMIX 5.5 12 5.2 11 4.9 10 4.6 9 8.0 4.3 8 7.5 7 7.0 6 6.5 3.4 5 6.0 3.1 4 5.5 3 100 5.0 4.0 IIP3MIX 3.7 2.8 -60 -40 -20 0 20 40 60 80 IIP3 (dBmW) 6.1 NF (dB) 15 6.4 GMIX [dB] NFMIX [dB] IIP3MIX [dBmW]) Ta (°C) MIX Block GMIX, IIP3 MIX, NFMIX vs VCC Ta = 25 °C, LO = 1.66 GHz/-15 dBmW, RF1 = 1.9000 GHz/-25 dBmW, RF2 = 1.9006 GHz/-25 dBmW for IIP3 measurement 14 4.92 4.90 13 NFMIX 12 4.88 11 4.86 4.84 10 GMIX 4.82 9 8.0 4.80 8 7.5 IIP3MIX 7 7.0 4.76 6 6.5 4.74 5 6.0 4.72 4 5.5 4.70 3 5.0 4.78 2.0 2.5 3.0 3.5 4.0 4.5 IIP3 (dBmW) Gain (dB) NF (dB) 15 4.94 GMIX [dB] NFMIX [dB] IIP3MIX [dBmW]) 5.0 VCC (V) 6 2007-11-01 TA4500F Typical Operating Characteristics of Down Conversion Mixer Block (continued) MIX Block GMIX, IIP3 MIX, NFMIX vs Local Input Power V CC = 3 V, Ta = 25 °C, RF1 = 1.9000 GHz/-25 dBmW, RF2 = 1.9006 GHz/-25 dBmW for IIP3 measurement NFMIX 5.7 14 5.4 13 5.1 12 11 4.8 4.5 10 GMIX 4.2 9 8.0 3.9 8 7.5 3.6 7 7.0 6 6.5 3.0 5 6.0 2.7 4 5.5 3 5.0 IIP3MIX 3.3 2.4 -24 -21 -18 -15 -12 -9 IIP3 (dBmW) Gain (dB) NF (dB) 15 6.0 GMIX [dB] NFMIX [dB] IIP3MIX [dBmW]) -6 PLO (dBmW) 7 2007-11-01 TA4500F Circuit Diagram of Evaluation Board C8 C7 L7 C9 L6 L4 L5 VCC=3.0V L8 IF_OUT L10 f=243.95MHz C3 C6 RF_IN f=1.9GHz C10 L9 C5 R1 6 5 4 1 2 3 C11 U1 L3 L2 VCC=3.0V VCC=3.0V C1 C4 C2 L1 LO_IN f=1.65605GHz List of External Chip Components on Evaluation Board Part Value Chip Series Part Value Chip Series C1 1000 pF GRM15 series MURATA L2 120 nH LQG15HN series MURATA C2 1000 pF GRM15 series MURATA L3 120 nH LQG15HN series MURATA C3 1000 pF GRM15 series MURATA L4 5.6 nH LQG15HN series MURATA C4 1000 pF GRM15 series MURATA L5 2.2 nH LQG15HN series MURATA C5 1000 pF GRM15 series MURATA L6 3.3 nH LQG15HN series MURATA C6 1000 pF GRM15 series MURATA L7 5.6 nH LQG15HN series MURATA C7 1 pF GRM15 series MURATA L8 1 nH LQG15HN series MURATA C8 2 pF GRM15 series MURATA L9 6.8 nH LQG15HN series MURATA C9 1 pF GRM15 series MURATA L10 100 nH LQG15HN series MURATA C10 3 pF GRM15 series MURATA R1 1.2 kΩ MCR01 series C11 2.7 pF GRM15 series MURATA U1 243.95 MHz L1 8.2 nH LQG15HN series ROHM SAFDA243MRD9X00R00 MURATA MURATA Typical Electrical Characteristics of Evaluation Board (for Reference Only) VCC = 3.0 V, Ta = 25°C, Zg = Zl = 50 Ω, fLO_IN = 1.65605 GHz, pLO_IN = -15 dBmW, fIF_OUT = 243.95 MHz Characteristic Symbol Test Condition Typ Unit Conversion gain GC fRF_IN = 1.9 GHz, pRF_IN = -30 dBmW (Note 7) 17.5 dB Noise figure NF DSB 3.8 dB 3 order intermodulation distortion IM3 IF output: fRF_IN = 1.9 GHz, pRF_IN = -46 dBmW, rd 3 order: fRF_IN1 = 1.8994 GHz, fRF_IN2 = 1.8988 GHz, pRF_IN1 = pRF_IN2 = -46 dBmW 64.0 dB Image reduction ratio IMR fRF_IN = 1.9 GHz,1.4121 GHz, pRF_IN = -46 dBmW 27.0 dB 1/2 IF reduction ratio 1/2IFR fRF_IN = 1.9 GHz,1.778025 GHz, pRF_IN = -46 dBmW 48.0 dB rd Note 7: Conversion gain in the above table includes the insertion loss (3.5 dB typical) of SAW filter, SAFDA243MRD 9X00R00. 8 2007-11-01 TA4500F Typical Operating Characteristics of Evaluation Board TA4500F on Application Board POUT,PIM3 vs PIN V CC = 3 V, Ta = 25 °C LO = 1.65605 GHz/-15dBmW, RF1 = 1.9000 GHz for POUT measurement, RF1 = 1.9006 GHz, RF2 = 1.9012 GHz for upper channel IM3 measurement, RF1 = 1.8994 GHz, RF2 = 1.8988 GHz for low er channel IM3 measurement 0 -10 POUT -20 POUT(dBmW) -30 -40 PIM3(up) -50 PIM3(low ) -60 -70 POUT [dBmW] -80 PIM3(up) [dBmW]) -90 PIM3(low ) [dBmW] -100 -50 -45 -40 -35 -30 -25 -20 PIN (dBmW) Pattern Layout of Evaluation Board (Top Layer) 5.6nH 1pF 0Ω 2pF 1000pF 2.2nH 5.6nH 1000pF 120nH 3.3nH 3pF 1000pF 2.7pF 1000pF 100ｎH 1nH 1pF 1000pF 6.8nH 120nH 1000pF 1.2kΩ 1000pF 0Ω 8.2nH 9 1000pF 2007-11-01 TA4500F Notice The circuits and measurements contained in this document are given in the context of example applications of the product only. Moreover, these example application circuits are not intended for mass production since the high-frequency characteristics (i.e., the AC characteristics) of the device will be affected by the external components that the customer uses, by the design of the circuit and by various other conditions. It is the responsibility of the customer to design external circuits that correctly implement the intended application and to check the characteristics of the design. TOSHIBA assumes no responsibility for the integrity of customer circuit designs or applications. 10 2007-11-01 TA4500F Package Physical Dimensions QS16 Unit: mm Weight: 0.0065 g (typ.) 11 2007-11-01 TA4500F RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 12 2007-11-01