T3GF3WBG
CMOS Digital Integrated Circuits
Silicon Monolithic
T3GF3WBG
1. Functional Description
•
Dual-Supply Bus Transceiver for SD Memory Card
2. General
This device is an advanced high-speed dual-supply bus transceiver fabricated with silicon-gate CMOS technology.
Designed for use as an interface between a 1.8-V bus and a 1.8-V/2.9-V bus in mixed 1.8-V/2.9-V supply systems.
The A-port interfaces with the 1.8-V bus, the B-port with the 1.8-V/2.9-V bus.
The direction of data transmission is determined by the level of the DIR input.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features
(1)
Compliant with SD specification Part 1 Physical Layer Specification 3.0 (SDR12/SDR25/DDR50)
(2)
Bidirectional interface between 1.8-V and 2.9-V buses
(3)
High-speed operation: tpd (A to B) = 5.0 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.9 ± 0.1 V)
tpd (B to A) = 5.0 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.9 ± 0.1 V)
tpd (A to B) = 7.0 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 1.8 ± 0.1 V)
tpd (B to A) = 7.0 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 1.8 ± 0.1 V)
(4)
Output current: IOHB/IOLB = ±6 mA (min) (VCCB = 2.8 V)
IOHA/IOLA = ±6 mA (min) (VCCA = 1.65 V)
(5)
Integrated EMI filter on B-port
(6)
Integrated pull-up and pull-down resistors on B-port
(7)
Latch-up performance: ±200 mA
(8)
ESD performance: Human body model > ±2000 V
IEC61000-4-2 Level 4 (Contact) > ±8 kV (SD card side)
IEC61000-4-2 Level 4 (Air) > ±15 kV (SD card side)
CDM > 500 V
(9)
Ultra-small package: WCSP25
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4. Packaging and Pin Assignment (Top View)
S-UFBGA25-0202-0.40-001
4.1. Pin Assignment
1
2
3
4
5
A
Dat2.h
CMD-dir
B
Dat3.h
SEL
Dat0-dir
VBatt
Dat2-B
VCCA
VCCB
Dat3-B
C
Clk.h
Enable
GND
GND
CLK-B
D
Dat0.h
CMD.h
CD
CMD-B
Dat0-B
E
Dat1.h
Clk-f
Dat123-dir
WP
Dat1-B
5. Marking
Fig. 5.1 Marking
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6. Principle of Operation
6.1. Truth Table
Input
Clk.h
Output
Clk-f
Output
CLK-B
L
L
L
H
H
H
Input
CMD-dir
Function
CMD.h
Function
CMD-B
Outputs
L
Output
Input
CMD.h = CMD-B
H
Input
Output
CMD-B = CMD.h
Input
Dat0-dir
Function
Dat0.h
Function
Dat0-B
Outputs
L
Output
Input
Dat0.h = Dat0-B
H
Input
Output
Dat0-B = Dat0.h
Input
Dat123-dir
Function
Dat1.h - Dat3.h
Function
Dat1-B - Dat3-B
Outputs
L
Output
Input
Datn.h = Datn-B
H
Input
Output
Datn-B = Datn.h
Input
Enable
Input
SEL
UVLO
Regulator
Function
L
X
X
OFF
H
X
Detect
OFF
H
L
Release
2.9 V
H
H
Release
1.8 V
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7. Block Diagram
Fig. 7.1 Block Diagram 1
Fig. 7.2 Block Diagram 2
Fig. 7.3 Block Diagram 3
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Fig. 7.4 Block Diagram 4
Fig. 7.5 Block Diagram 5
Fig. 7.6 Block Diagram 6
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8. Absolute Maximum Ratings (Note)
Characteristics
Symbol
Supply voltage
Input voltage (DIR, Clk.h)
Note
Rating
Unit
VCCA
-0.5 to 3.0
V
VBatt
5.5
VIN
-0.5 to VCCA +0.5
Input voltage (Enable, SEL)
-0.5 to 5.5
Bus I/O voltage
VI/OA
Clamp diode current (DIR, Clk.h)
(Note 1)
-0.5 to VCCA +0.5
VI/OB
-0.5 to VCCB +0.5
IIK
±25
Clamp diode current (Enable, SEL)
mA
-25
I/O diode current
II/OK
Output current
IOUTA
±25
IOUTB
±25
ICCA
±50
VCC/ground current per supply pin
(Note 2)
±25
Power dissipation
PD
400
mW
Storage temperature
Tstg
-55 to 150
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: High (H) or Low (L) state. IOUT absolute maximum rating must be observed.
Note 2: VOUT < GND, VOUT > VCC
9. Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage (DIR, Clk.h)
Symbol
Note
VCCA
Test Condition
Rating
Unit
1.65 to 1.95
V
VBatt
3.1 to 5.0
VIN
0 to VCCA
Input voltage (Enable, SEL)
0 to 5.0
Bus I/O voltage
VI/OA
(Note 1)
0 to VCCA
Output current
IOUTA
VCCA = 1.65 to 1.95 V
±6
IOUTB
VCCB = 2.8 to 3.0 V, VCCB is
supplied from the built-in LDO.
±6
85
0 to 10
ns/V
VI/OB
0 to VCCB
Operating temperature
Topr
Input rise time
dt/dv
VCCA = 1.65 V, VCCB = 2.8 V
Input fall time
mA
0 to 10
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs and bus inputs must be tied to either VCC or GND. Please connect both bus inputs and the bus
outputs with VCC or GND when the I/O of the bus terminal changes by the function. In this case, please note
that the output is not short-circuited.
Note: Don't input the signal during the period of changing the output voltage of the LDO.
Note 1: High (H) or Low (L) state.
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10. Electrical Characteristics
10.1. DC Characteristics (Note)
(Unless otherwise specified, Ta = -30 to 85
, 1.65 V ≤ VCCA ≤ 1.95 V)
85
Characteristics
Symbol
Test Condition
(Note 1)
VCCA (V)
VCCB (V)
Min
Max
Unit
1.65 to 1.95
1.7 to 3.0
VCCA × 0.65
V
2.8 to 3.0
2.0
1.7 to 1.9
VCCB × 0.65
VCCA × 0.35
High-level input voltage
(DIR, An)
VIHA
High-level input voltage
(Bn)
VIHB
Low-level input voltage
(DIR, An)
VILA
1.7 to 3.0
Low-level input voltage
(Bn)
VILB
2.8 to 3.0
0.8
1.7 to 1.9
VCCB × 0.35
High-level output voltage
VOHA VIN = VIH or VIL, IOHA = -100 µA
1.7 to 3.0
VCCA - 0.2
1.15
2.8 to 3.0
VCCB - 0.2
1.7 to 1.9
VCCB - 0.2
VIN = VIH or VIL, IOHB = -6 mA
2.8
2.2
VIN = VIH or VIL, IOHB = -4 mA
1.7
1.2
1.7 to 3.0
0.2
0.3
2.8 to 3.0
0.2
1.7 to 1.9
0.2
VIN = VIH or VIL, IOLB = 6 mA
2.8
0.4
VIN = VIH or VIL, IOLB = 4 mA
1.7
0.3
1.7 to 3.0
±5.0
VIN = VIH or VIL, IOHA = -6 mA
1.65
VOHB VIN = VIH or VIL, IOHB = -100 µA 1.65 to 1.95
Low-level output voltage
VOLA VIN = VIH or VIL, IOLA = 100 µA
VIN = VIH or VIL, IOLA = 6 mA
VOLB VIN = VIH or VIL, IOLB = 100 µA
Input leakage current
Quiescent supply current
1.65
1.65 to 1.95
IINA
VINA = VCCA or GND
DIR = High
VCD = VWP = VCCA
IINB
VCMD-B, VDAT0-B,
VDAT1-B, VDAT2-B = VCCB
VDAT3-B = GND, DIR = Low
VCD = VWP = VCCA
±5.0
ICCA
VINA = VCCA or GND
DIR = High
VCD = VWP = VCCA
20
µA
Note: VCCB is supplied from the built-in LDO.
Note 1: An is a host side signal. Bn is a card side signal.
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10.2. AC Characteristics (Note)
(Unless otherwise specified, Ta = -30 to 85
, Input: tr = tf = 2.0 ns)
85
10.2.1. VCCA = 1.8 ± 0.15 V, VCCB = 2.9 ± 0.1 V
Characteristics
Symbol
Min
Typ.
Max
Unit
3.5
5.0
ns
Propagation delay time (An → Bn)
3.5
5.0
Propagation delay time (Clk.h → Clk-f)
1.0
5.7
9.5
-1.8
0.0
3.0
1.5
1.5
0.5
Propagation delay time (Bn → An)
Note
Test Condition
tPLH/tPHL
Skew (CLK-f to CMD/DAT)
See Fig. 10.2.1, 10.2.2
tskew.f
Output rise/fall time (An)
tTLH/tTHL
See Fig. 10.2.1, 10.2.2
Output rise/fall time (Bn)
Output skew
tosLH/tosHL (Note 1) See Fig. 10.2.3
Note: An is a host side signal. Bn is a card side signal. VCCB is supplied from the built-in LDO.
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm - tPLHn|, tosHL = |tPHLm - tPHLn|)
10.2.2. VCCA = 1.8 ± 0.15 V, VCCB = 1.8 ± 0.1 V
Characteristics
Symbol
Min
Typ.
Max
Unit
4.5
7.0
ns
Propagation delay time (An → Bn)
5.0
7.0
Propagation delay time (Clk.h → Clk-f)
1.0
8.0
13.5
-0.8
0.4
1.6
1.5
1.5
0.5
Propagation delay time (Bn → An)
Skew (CLK-f to CMD/DAT)
Output rise/fall time (An)
Note
Test Condition
tPLH/tPHL
See Fig. 10.2.1, 10.2.2
tskew.f
tTLH/tTHL
See Fig. 10.2.1, 10.2.2
Output rise/fall time (Bn)
Output skew
tosLH/tosHL (Note 1) See Fig. 10.2.3
Note: An is a host side signal. Bn is a card side signal. VCCB is supplied from the built-in LDO.
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm - tPLHn|, tosHL = |tPHLm - tPHLn|)
10.3. Dynamic Switching Characteristics (Note)
, Input: tr = tf = 2.0 ns, CL = 15 pF)
(Unless otherwise specified,Ta = 25
25
Characteristics
Quiet output maximum dynamic VOL
Symbol
(A → B)
VOLP
(B → A)
Quiet output minimum dynamic VOL
(A → B)
Note
Test Condition
(Note 1) See Fig. 10.3.1
VIH = VCC, VIL = 0 V
VCCA (V) VCCB (V)
1.8
2.9
(A → B)
0.35
V
-0.35
-0.25
VOHP
3.25
(B → A)
Quiet output minimum dynamic VOH
Unit
0.25
VOLV
(B → A)
Quiet output maximum dynamic VOH (A → B)
Typ.
2.05
VOHV
2.55
(B → A)
1.55
Note: An is a host side signal. Bn is a card side signal.
Note 1: Parameter guaranteed by design.
)
10.4. Capacitive Characteristics (Unless otherwise specified, Ta = 25
25
Characteristics
Power dissipation capacitance
Symbol
CPDA
CPDB
Note
Test Condition
(Note 1) A → B (DIR = High)
VCCA (V) VCCB (V)
1.8
2.9
Typ.
Unit
24
pF
B → A (DIR = Low)
22
A → B (DIR = High)
76
B → A (DIR = Low)
28
Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
ICC(opr) = CPD × VCC × fIN + ICC/6 (per bit)
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Fig. 10.2.1 Parameter for AC Test Circuit
Fig. 10.2.2 AC Waveform tPLH, tPHL, tTLH, tTHL
Fig. 10.2.3 AC Waveform tosLH, tosHL
Table 10.2.1 AC Waveform Symbols
VCC
Symbol
2.9 ± 0.1 V
VIH
VCC
VM
VCC/2
1.8 ± 0.15 V
Value
VIH
VCC
VM
VCC/2
Fig. 10.3.1 Quiet Output Measurement Circuit VOHP, VOHV, VOLP, VOLV
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11. Regulator Section
11.1. Electrical Characteristics (Unless otherwise specified, VIN = VOUT + 1 V,
)
IOUT = 1 mA, CIN = 0.1 µF, COUT = 2.2 µF, Tj = 25
25
Characteristics
Symbol
Note
Test Condition
Min
Typ.
Max
Unit
V
Supply voltage
VBatt
3.1
5.0
Output voltage
VCCB
(Note 1) SEL = Low
2.8
2.9
3.0
SEL = High
1.7
1.8
1.9
2.4
2.7
2.6
2.8
UVLO detect voltage
VUVLO1
UVLO release voltage
VUVLO2
Line regulation
REGLine
VOUT + 0.5 V ≤ VIN ≤ 5.0 V,
IOUT = 1 mA
3
15
Load regulation
REGLoad
1 mA ≤ IOUT ≤ 100 mA
150
mV
Quiescent current
IB(ON)
IOUT = 0 mA
80
160
Standby current
IB(OFF)
VEnable = 0 V, VSEL = 0 V
0.1
1.0
VIN = VOUT = + 1 V,
IOUT = 10 mA,
10 Hz ≤ f ≤ 100 kHz, Ta = 25
140
µVms
Output noise voltage
Vn
µA
Temperature coefficient of output
voltage
TCVO
-30 ≤ Topr ≤ 85
100
ppm/
Ripple rejection
R.R
VIN = VOUT + 1 V,
IOUT = 10 mA, f = 1 kHz,
VRipple = 500 mVp-p, Ta = 25
40
dB
High-level input voltage
VIH
Enable, SEL
1.5
VBatt
V
Low-level input voltage
VIL
0
0.25
Control current (ON)
ICT(ON)
VEnable = 1.5 V
7.5
Control current (OFF)
ICT(OFF)
VEnable = 0 V
0.1
µA
Startup time
tstart
SEL = Low
200
µs
Transition time (from 2.9 V to 1.8 V)
ttrans
5
ms
Note 1: The relation between the supply voltage and the output voltage is shown in the below figure.
This figure shows the representative typical behavior of the LDO.
Fig. 11.1.1 UVLO Characteristics
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11.2. EMI Filter Response (Typical performance)
Fig. 11.2.1 EMI Filter Response (Typical performance)
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Package Dimensions
Unit: mm
Weight: 0.006 g (typ.)
Package Name(s)
TOSHIBA: S-UFBGA25-0202-0.40-001
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's
written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible
for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage
to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate
the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA
information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the
precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application
with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications,
including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating
and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample
application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications.
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AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
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