74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs General Description Features The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package. n Ideal for low power/low noise 3.3V applications n Implements patented EMI reduction circuitry n Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75Ω n 4 kV minimum ESD immunity Ordering Code: Order Number Package Number 74LVQ573SC M20B 74LVQ573SJ M20D 74LVQ573QSC Package Description 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC 20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for SOIC and QSOP DS011361-1 IEEE/IEC DS011361-3 Pin Descriptions Pin Names DS011361-2 © 1998 Fairchild Semiconductor Corporation DS011361 Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs www.fairchildsemi.com 74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs May 1998 Truth Table Functional Description Inputs The LVQ573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram DS011361-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 3.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V 2.0V to 3.6V 0V to VCC 0V to VCC −40˚C to +85˚C 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ± 50 mA ± 400 mA −65˚C to +150˚C Note 2: Unused inputs must be held HIGH or LOW. They may not float. ± 300 mA DC Electrical Characteristics Symbol Parameter VCC (V) TA = +25˚C TA = −40˚C to +85˚C Typ VIH VIL VOH Minimum High Level Input Voltage 3.0 Maximum Low Level Input Voltage 3.0 Minimum High Level Output Voltage 1.5 Units Conditions Guaranteed Limits 2.0 2.0 V VOUT = 0.1V or VCC − 0.1V 1.5 0.8 0.8 V VOUT = 0.1V or VCC − 0.1V 2.9 2.9 V IOUT = −50 µA 2.58 2.48 V VIN = VIL or VIH (Note 3) 0.1 0.1 V IOUT = 50 µA 3.0 0.36 0.44 V VIN = VIL or VIH (Note 3) 3.6 ± 0.1 ± 1.0 µA 3.0 2.99 3.0 IOH = −12 mA VOL Maximum Low Level Output Voltage 3.0 0.002 IOL = 12 mA IIN Maximum Input Leakage Current IOLD Minimum Dynamic Output Current (Note 4) IOHD ICC Maximum Quiescent Supply Current IOZ 3-STATE Leakage Curent VI = VCC, GND 3.6 36 mA VOLD = 0.8 VMax (Note 5) 3.6 −25 mA VOHD = 2.0V VMin (Note 5) 3.6 4.0 40.0 µA VIN = VCC or GND 3.6 ± 0.25 ± 2.5 µA VI = VCC, GND VI (OE) = VIL, VIH VO = VCC, GND VOLP Quiet Output Maximum Dynamic VOL 3.3 0.4 0.8 V (Notes 6, 7) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.4 −0.8 V (Notes 6, 7) VIHD Maximum High Level Dynamic Input Voltage 3.3 1.6 2.0 V (Notes 6, 8) VILD Maximum Low Level Dynamic Input Voltage 3.3 1.6 0.8 V (Notes 6, 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com AC Electrical Characteristics Symbol tPHL Propagation Delay tPLH Dn to On tPLH Propagation Delay tPHL LE to On tPZL Output Enable Time tPZH Output Disable Time tPHZ TA = +25˚C CL = 50 pF VCC (V) Parameter tPLZ tOSHL Output to Output Skew (Note 9) tOSLH Dn to On TA = −40˚C to +85˚C CL = 50 pF Min Typ Max Min 2.7 2.5 10.2 14.8 2.5 16.0 3.3 ± 0.3 2.5 8.5 10.5 2.5 11.0 2.7 2.5 10.2 16.9 2.5 18.0 3.3 ± 0.3 2.5 8.5 12.0 2.5 12.5 2.7 2.5 10.2 18.3 2.5 19.0 3.3 ± 0.3 2.5 8.5 13.0 2.5 13.5 2.7 1.0 10.8 20.4 1.0 21.0 3.3 ± 0.3 1.0 9.0 14.5 1.0 15.0 Units Max 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements Symbol TA = +25˚C CL = 50 pF VCC (V) Parameter Typ Setup Time, HIGH or LOW tS Dn to LE Hold Time, HIGH or LOW tH Dn to LE LE Pulse Width, HIGH tW TA = −40˚C to +85˚C CL = 50 pF Units Guaranteed Minimum 2.7 0 4.0 4.5 3.3 ± 0.3 0 3.0 3.0 2.7 0 1.5 1.5 3.3 ± 0.3 0 1.5 1.5 2.7 2.4 5.0 6.0 3.3 ± 0.3 2.0 4.0 4.0 ns ns ns Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open CPD (Note 10) Power Dissipation Capacitance 37 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. www.fairchildsemi.com 4 Conditions Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC Package Number M20B 20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ Package Number M20D 5 www.fairchildsemi.com 74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC (also known as QSOP) Package Number MQA20 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. 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