RENESAS 7751

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER
7700 FAMILY / 7751 SERIES
7751
Group
User’s Manual
Preface
This manual describes the hardware of the Mitsubishi
CMOS 16-bit microcomputers 7751 Group. After
reading this manual, the users will be able to
understand the functions, so that they can utilize their
capabilities fully.
For details concerning the software, refer to the 7751
Series Software Manual. For details concerning the
development support tools (assembler, emulation
pods), refer to the respective user’s manuals.
Table of Contents
Table of Contents
CHAPTER 1. DESCRIPTION
1.1
1.2
1.3
1.4
Performance overview ..........................................................................................................
Pin configuration ...................................................................................................................
Pin description ......................................................................................................................
Block diagram ........................................................................................................................
1-3
1-4
1-5
1-8
CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit ....................................................................................................... 2-2
2.1.1 Accumulator (Acc) ......................................................................................................... 2-3
2.1.2 Index register X (X) ....................................................................................................... 2-3
2.1.3 Index register Y (Y) ....................................................................................................... 2-3
2.1.4 Stack pointer (S) ............................................................................................................ 2-4
2.1.5 Program counter (PC) ................................................................................................... 2-5
2.1.6 Program bank register (PG) ......................................................................................... 2-5
2.1.7 Data bank register (DT) ................................................................................................ 2-6
2.1.8 Direct page register (DPR) ........................................................................................... 2-6
2.1.9 Processor status register (PS) ..................................................................................... 2-8
2.2 Bus interface unit ............................................................................................................... 2-10
2.2.1 Overview ....................................................................................................................... 2-10
2.2.2 Functions of bus interface unit (BIU) ........................................................................ 2-12
2.2.3 Operation of bus interface unit (BIU)........................................................................ 2-15
2.3 Access space ....................................................................................................................... 2-17
2.3.1 Banks ............................................................................................................................ 2-18
2.3.2 Direct page ................................................................................................................... 2-18
2.4 Memory assignment ........................................................................................................... 2-19
2.4.1 Memory assignment in internal area ......................................................................... 2-19
2.5 Processor modes ................................................................................................................ 2-22
2.5.1 Single-chip mode ......................................................................................................... 2-23
2.5.2 Memory expansion and microprocessor modes ....................................................... 2-23
2.5.3 Setting processor modes ............................................................................................ 2-26
[Precautions when operating in single-chip mode] ............................................................ 2-28
CHAPTER 3. INPUT/OUTPUT PINS
3.1 Programmable I/O ports ...................................................................................................... 3-2
3.1.1 Direction register ............................................................................................................ 3-3
3.1.2 Port register .................................................................................................................... 3-4
3.2 I/O pins of internal peripheral devices ............................................................................ 3-8
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Table of Contents
CHAPTER 4. INTERRUPTS
4.1 Overview ..................................................................................................................................4-2
4.2 Interrupt sources ................................................................................................................... 4-4
4.3 Interrupt control .................................................................................................................... 4-6
4.3.1 Interrupt disable flag (I) ................................................................................................ 4-8
4.3.2 Interrupt request bit ....................................................................................................... 4-8
4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) ....... 4-8
4.4 Interrupt priority level ........................................................................................................ 4-10
4.5 Interrupt priority level detection circuit ........................................................................ 4-11
4.6 Interrupt priority level detection time ............................................................................ 4-13
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine ........................... 4-14
4.7.1 Change in IPL at acceptance of interrupt request .................................................. 4-16
4.7.2 Storing registers ........................................................................................................... 4-17
4.8 Return from interrupt routine........................................................................................... 4-18
4.9 Multiple interrupts ...............................................................................................................
4-18
___
4.10 External interrupts
(INT
i interrupt) ................................................................................ 4-20
___
4.10.1 Function of INTi interrupt request
bit ...................................................................... 4-23
___
4.10.2 Switch of occurrence factor of INT i interrupt request ........................................... 4-25
CHAPTER 5. TIMER A
5.1 Overview ..................................................................................................................................5-2
5.2 Block description .................................................................................................................. 5-3
5.2.1 Counter and reload register (timer Ai register) ......................................................... 5-4
5.2.2 Count start register........................................................................................................ 5-5
5.2.3 Timer Ai mode register ................................................................................................. 5-6
5.2.4 Timer Ai interrupt control register ............................................................................... 5-7
5.2.5 Port P5 and port P6 direction registers ..................................................................... 5-8
5.3 Timer mode ............................................................................................................................ 5-9
5.3.1 Setting for timer mode ................................................................................................ 5-11
5.3.2 Count source ................................................................................................................ 5-13
5.3.3 Operation in timer mode ............................................................................................. 5-14
5.3.4 Select function ............................................................................................................. 5-15
5.4 Event counter mode ........................................................................................................... 5-19
5.4.1 Setting for event counter mode ................................................................................. 5-22
5.4.2 Operation in event counter mode .............................................................................. 5-24
5.4.3 Select functions ............................................................................................................ 5-26
5.5 One-shot pulse mode ......................................................................................................... 5-30
5.5.1 Setting for one-shot pulse mode ............................................................................... 5-32
5.5.2 Count source ................................................................................................................ 5-34
5.5.3 Trigger ........................................................................................................................... 5-35
5.5.4 Operation in one-shot pulse mode ............................................................................ 5-36
5.6 Pulse width modulation (PWM) mode ............................................................................ 5-39
5.6.1 Setting for PWM mode ............................................................................................... 5-41
5.6.2 Count source ................................................................................................................ 5-43
5.6.3 Trigger ........................................................................................................................... 5-43
5.6.4 Operation in PWM mode ............................................................................................ 5-44
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7751 Group User’s Manual
Table of Contents
CHAPTER 6. TIMER B
6.1 Overview ..................................................................................................................................6-2
6.2 Block description .................................................................................................................. 6-2
6.2.1 Counter and reload register (timer Bi register) ......................................................... 6-3
6.2.2 Count start register........................................................................................................ 6-4
6.2.3 Timer Bi mode register ................................................................................................. 6-5
6.2.4 Timer Bi interrupt control register ............................................................................... 6-6
6.2.5 Port P6 direction register ............................................................................................. 6-7
6.3 Timer mode ............................................................................................................................ 6-8
6.3.1 Setting for timer mode ................................................................................................ 6-10
6.3.2 Count source ................................................................................................................ 6-11
6.3.3 Operation in timer mode ............................................................................................. 6-12
6.4 Event counter mode ........................................................................................................... 6-14
6.4.1 Setting for event counter mode ................................................................................. 6-16
6.4.2 Operation in event counter mode .............................................................................. 6-17
6.5 Pulse period/pulse width measurement mode ............................................................. 6-19
6.5.1 Setting for pulse period/pulse width measurement mode ...................................... 6-21
6.5.2 Count source ................................................................................................................ 6-23
6.5.3 Operation in pulse period/pulse width measurement mode ................................... 6-24
CHAPTER 7. SERIAL I/O
7.1 Overview ..................................................................................................................................7-2
7.2 Block description .................................................................................................................. 7-3
7.2.1 UARTi transmit/receive mode register ........................................................................ 7-4
7.2.2 UARTi transmit/receive control register 0 .................................................................. 7-6
7.2.3 UARTi transmit/receive control register 1 .................................................................. 7-7
7.2.4 UARTi transmit register and UARTi transmit buffer register ................................... 7-9
7.2.5 UARTi receive register and UARTi receive buffer register .................................... 7-11
7.2.6 UARTi baud rate register (BRGi) .............................................................................. 7-13
7.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers 7-14
7.2.8 Port P8 direction register ........................................................................................... 7-16
7.3 Clock synchronous serial I/O mode ............................................................................... 7-17
7.3.1 Transfer clock (synchronizing clock) ......................................................................... 7-18
7.3.2 Transfer data format.................................................................................................... 7-19
7.3.3 Method of transmission ............................................................................................... 7-20
7.3.4 Transmit operation ....................................................................................................... 7-24
7.3.5 Method of reception .................................................................................................... 7-26
7.3.6 Receive operation ........................................................................................................ 7-30
7.3.7 Process on detecting overrun error ........................................................................... 7-33
7.4 Clock asynchronous serial I/O (UART) mode ............................................................... 7-35
7.4.1 Transfer rate (frequency of transfer clock) .............................................................. 7-36
7.4.2 Transfer data format.................................................................................................... 7-38
7.4.3 Method of transmission ............................................................................................... 7-40
7.4.4 Transmit operation ....................................................................................................... 7-44
7.4.5 Method of reception .................................................................................................... 7-46
7.4.6 Receive operation ........................................................................................................ 7-49
7.4.7 Process on detecting error ......................................................................................... 7-51
7.4.8 Sleep mode .................................................................................................................. 7-52
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Table of Contents
CHAPTER 8. A-D CONVERTER
8.1 Overview ..................................................................................................................................8-2
8.2 Block description .................................................................................................................. 8-3
8.2.1 A-D control register 0 ................................................................................................... 8-4
8.2.2 A-D control register 1 ................................................................................................... 8-6
8.2.3 A-D register i (i = 0 to 7) ............................................................................................. 8-7
8.2.4 A-D conversion interrupt control register .................................................................... 8-8
8.2.5 Port P7 direction register ............................................................................................. 8-9
8.3 A-D conversion method (successive approximation conversion method) ............8-10
8.4 Absolute accuracy and differential non-linearity error .............................................. 8-13
8.4.1 Absolute accuracy ....................................................................................................... 8-13
8.4.2 Differential non-linearity error ..................................................................................... 8-14
8.5 Comparison voltage in 8-bit mode ................................................................................. 8-15
8.6 One-shot mode .................................................................................................................... 8-16
8.6.1 Settings for one-shot mode ........................................................................................ 8-16
8.6.2 One-shot mode operation description ....................................................................... 8-18
8.7 Repeat mode ........................................................................................................................ 8-20
8.7.1 Settings for repeat mode ............................................................................................ 8-20
8.7.2 Repeat mode operation description .......................................................................... 8-22
8.8 Single sweep mode ............................................................................................................ 8-23
8.8.1 Settings for single sweep mode ................................................................................ 8-23
8.8.2 Single sweep mode operation description ................................................................ 8-25
8.9 Repeat sweep mode 0 ....................................................................................................... 8-27
8.9.1 Settings for repeat sweep mode 0 ............................................................................ 8-27
8.9.2 Repeat sweep mode 0 operation description .......................................................... 8-29
8.10 Repeat sweep mode 1 ..................................................................................................... 8-31
8.10.1 Settings for repeat sweep mode 1 .......................................................................... 8-31
8.10.2 Repeat sweep mode 1 operation description ........................................................ 8-34
CHAPTER 9. WATCHDOG TIMER
9.1 Block description .................................................................................................................. 9-2
9.1.1 Watchdog timer .............................................................................................................. 9-3
9.1.2 Watchdog timer frequency select register .................................................................. 9-4
9.2 Operation description .......................................................................................................... 9-5
9.2.1 Basic operation .............................................................................................................. 9-5
9.2.2 Operation in Stop mode ............................................................................................... 9-7
9.2.3 Operation in Hold state ................................................................................................. 9-7
9.3 Precautions when using watchdog timer ........................................................................ 9-8
CHAPTER 10. STOP MODE
10.1 Clock generating circuit .................................................................................................. 10-2
10.2 Operation description ...................................................................................................... 10-3
10.2.1 Termination by interrupt request occurrence ......................................................... 10-4
10.2.2 Termination by hardware reset ................................................................................ 10-5
10.3 Precautions for Stop mode ............................................................................................ 10-6
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Table of Contents
CHAPTER 11. WAIT MODE
11.1 Clock generating circuit .................................................................................................. 11-2
11.2 Operation description ...................................................................................................... 11-3
11.2.1 Termination by interrupt request occurrence ......................................................... 11-4
11.2.2 Termination by hardware reset ................................................................................ 11-4
11.3 Precautions for Wait mode ............................................................................................. 11-5
CHAPTER 12. CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices ...................................................... 12-2
12.1.1 Descriptions of signals .............................................................................................. 12-2
12.1.2 Operation of bus interface unit (BIU) ..................................................................... 12-8
12.2 Bus cycle .......................................................................................................................... 12-11
12.3 Ready function ................................................................................................................ 12-14
12.3.1 Operation description .............................................................................................. 12-15
12.4 Hold function ................................................................................................................... 12-18
12.4.1 Operation description .............................................................................................. 12-19
CHAPTER 13. RESET
13.1 Hardware reset .................................................................................................................. 13-2
13.1.1 Pin state ..................................................................................................................... 13-3
13.1.2 State of CPU, SFR area, and internal RAM area................................................. 13-4
13.1.3 Internal processing sequence
after reset ............................................................... 13-9
______
13.1.4 Time supplying “L” level to RESET pin ................................................................ 13-10
13.2 Software reset .................................................................................................................. 13-12
CHAPTER 14. CLOCK GENERATING CIRCUIT
14.1 Oscillation circuit example ............................................................................................. 14-2
14.1.1 Connection example using resonator/oscillator ...................................................... 14-2
14.1.2 Input example of externally generated clock ......................................................... 14-2
14.2 Clock .................................................................................................................................... 14-3
14.2.1 Clock generated in clock generating circuit ........................................................... 14-4
14.2.2 Operation clock for internal peripheral devices ..................................................... 14-5
7751 Group User’s Manual
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Table of Contents
CHAPTER 15. ELECTRICAL CHARACTERISTICS
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Absolute maximum ratings ............................................................................................. 15-2
Recommended operating conditions ............................................................................ 15-3
Electrical characteristics ................................................................................................. 15-4
A-D converter characteristics ........................................................................................ 15-5
Internal peripheral devices ............................................................................................. 15-6
Ready and Hold ............................................................................................................... 15-13
Single-chip mode ............................................................................................................ 15-16
Memory expansion mode and microprocessor mode : When 2-φ access in
low-speed running ......................................................................................................... 15-18
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in
low-speed running ......................................................................................................... 15-23
15.10 Memory expansion mode and microprocessor mode : When 4- φ access in
low-speed running ....................................................................................................... 15-28
15.11 Memory expansion mode and microprocessor mode : When 3- φ access in
high-speed running ...................................................................................................... 15-33
15.12 Memory expansion mode and microprocessor mode : When 4- φ access in
high-speed running ...................................................................................................... 15-38
15.13 Memory expansion mode and microprocessor mode : When 5- φ access in
high-speed running ...................................................................................................... 15-43
15.14 Memory expansion mode and microprocessor mode : When 2- φ access in
high-speed running (Internal RAM access) ............................................................
15-48
_
15.15 Testing circuit for ports P0 to P8, φ 1 , and E ......................................................... 15-51
CHAPTER 16. STANDARD CHARACTERISTICS
16.1 Standard characteristics ................................................................................................. 16-2
16.1.1 Programmable I/O port (CMOS output) standard characteristics ........................ 16-2
16.1.2 Icc–f(XIN) standard characteristics .......................................................................... 16-3
16.1.3 A-D converter standard characteristics ................................................................... 16-4
CHAPTER 17. APPLICATIONS
17.1 Memory expansion ............................................................................................................ 17-2
17.1.1 Memory expansion model ......................................................................................... 17-2
17.1.2 How to calculate timing ............................................................................................ 17-4
17.1.3 Points in memory expansion .................................................................................... 17-8
17.1.4 Example of memory expansion .............................................................................. 17-26
17.1.5 Example of I/O expansion ...................................................................................... 17-37
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7751 Group User’s Manual
Table of Contents
CHAPTER 18. PROM VERSION
18.1 EPROM mode ..................................................................................................................... 18-3
18.1.1 Pin description ........................................................................................................... 18-3
18.1.2 Programming/reading to/from built-in PROM .......................................................... 18-4
18.1.3 Programming algorithm of built-in PROM ............................................................... 18-7
18.1.4 Electrical characteristics of programming algorithm .............................................. 18-9
18.2 Usage precaution ............................................................................................................ 18-10
18.2.1 Precautions on all PROM versions ....................................................................... 18-10
18.2.2 Precautions on one time PROM version .............................................................. 18-11
18.2.3 Precautions on EPROM version ............................................................................ 18-11
CHAPTER 19. FLASH MEMORY VERSION
19.1 Parallel input/output mode ............................................................................................. 19-3
19.1.1 Pin description ........................................................................................................... 19-4
19.1.2 Access to built–in flash memory ............................................................................. 19-5
19.1.3 Read–only mode ........................................................................................................ 19-7
19.1.4 Read/write (software command control) mode ...................................................... 19-9
19.1.5 Electrical characteristics ......................................................................................... 19-18
19.1.6 Program/erase algorithm flow chart ...................................................................... 19-20
19.2 Serial input/output mode ............................................................................................... 19-21
19.2.1 Pin description ......................................................................................................... 19-21
19.2.2 Access to built–in flash memory ........................................................................... 19-23
19.2.3 Electrical characteristics ......................................................................................... 19-31
19.2.4 Program algorithm flow chart ................................................................................. 19-33
APPENDIX
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
1.
2.
3.
4.
5.
6.
7.
8.
9.
Memory assignment ........................................................................................... 20-2
Memory assignment in SFR area ................................................................... 20-5
Control registers ................................................................................................. 20-9
Package outlines .............................................................................................. 20-32
Example for processing unused pins .......................................................... 20-34
Hexadecimal instruction code table ............................................................. 20-37
Machine instructions ....................................................................................... 20-40
Examples of noise immunity improvement ................................................ 20-61
Q & A .................................................................................................................. 20-71
7751 Group User’s Manual
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Table of Contents
MEMORANDUM
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7751 Group User’s Manual
CHAPTER 1
DESCRIPTION
1.1
1.2
1.3
1.4
Performance overview
Pin configuration
Pin description
Block diagram
DESCRIPTION
The 16-bit single-chip microcomputers 7751 Group is suitable for office, business, and industrial equipment
controllers that require high-speed processing of large amounts of data.
These microcomputers develop with the M37751M6C-XXXFP as the base chip. This manual describes the
functions about the M37751M6C-XXXFP unless there is a specific difference and refers to the
M37751M6C-XXXFP as “M37751.”
Notes 1: About details concerning each microcomputer’s development status of the 7751 Group, inquire of
“CONTACT ADDRESSES FOR FURTHER INFORMATION” described last.
2: How the 7751 Group’s type name see is described below.
M 3 77 51 M 6 C–XXX FP
Mitsubishi integrated prefix
Represent an original single-chip microcomputer
Series designation using 2 digits
Circuit function identification code using 2 digits
Memory identification code using a digit
M: Mask ROM
E: EPROM
F: Flash memory
S: External ROM
Memory size identification code using a digit
Difference of electrical characteristics identification code
using a digit
Mask ROM number
Package style
FP: Plastic molded QFP
FS: Ceramic QFN
1–2
7751 Group User’s Manual
DESCRIPTION
1.1 Performance overview
1.1 Performance overview
Table 1.1.1 shows the performance overview of the M37751.
Table 1.1.1 M37751 performance overview
Functions
Parameters
Number of basic instructions
109
Instruction execution time
100 ns (the minimum instruction at f(XIN) = 40 MHz)
Operating clock frequency f(XIN)
40 MHz (maximum at high-speed running)
49152 bytes
Memory size
Programmable Input/Output
ports
Multifunction timers
Serial I/O
ROM
RAM
P0–P2, P4–P8
2048 bytes
P3
4 bits ✕ 1
TA0–TA4
16 bits ✕ 5
TB0–TB2
16 bits ✕ 3
(UART or clock synchronous serial I/O) ✕ 2
UART0, UART1
8 bits ✕ 8
A-D converter
10-bit successive approximation method ✕ 1 (8 channels)
Watchdog timer
Interrupts
12 bits ✕ 1
Clock generating circuit
Built-in (externally connected to a ceramic
resonator or a quartz-crystal oscillator)
Supply voltage
Power dissipation
5 V ±10 %
125 mW (at f(X IN) = 40 MHz frequency, typ.)
Port Input/Output
characteristics
3 external, 16 internal (priority levels 0 to 7 can
be set for each interrupt with software)
Input/Output withstand voltage 5 V
5 mA
Output current
Memory expansion
Maximum 16 Mbytes
Operating temperature range
–20°C to 85°C
CMOS high-performance silicon gate process
Device structure
80-pin plastic molded QFP
Package
Note: All of the 7751 Group microcomputers are the same except for the package type, memory type,
memory size, and electric characteristics.
7751 Group User’s Manual
1–3
DESCRIPTION
1.2 Pin configuration
1.2 Pin configuration
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7/ADTRG
VSS
AVSS
VREF
AVCC
VCC
P80/CTS0/RTS0
P81/CLK0
P82/RXD0
P83/TXD0
Figure 1.2.1 shows the M37751 pin configuration.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
2
63
3
62
M37751M6C-XXXFP
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
P42/φ1
P41/RDY
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
24
41
P40/HOLD
BYTE
CNVSS
RESET
XIN
XOUT
E
Vss
P33/HLDA
P32/ALE
P31/BHE
P30/R/W
P27/A23/D7
P26/A22/D6
P25/A21/D5
P24/A20/D4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Outline : 80P6N-A
Fig. 1.2.1 M37751 pin configuration (top view)
1–4
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7751 Group User’s Manual
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
P00/A0
P01/A1
P02/A2
P03/A3
P04/A4
P05/A5
P06/A6
P07/A7
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A16/D0
P21/A17/D1
P22/A18/D2
P23/A19/D3
DESCRIPTION
1.3 Pin description
1.3 Pin description
Tables 1.3.1 to 1.3.3 list the pin description.
Table 1.3.1 Pin description (1)
Name
Pin
Vcc, Vss
Power supply
CNVss
CNVss
Input/Output
Functions
Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin.
Input
This pin controls the processor mode.
[Single-chip mode] [Memory expansion mode]
Connect to Vss pin.
[Microprocessor mode]
Connect to Vcc pin.
______
RESET
Reset input
Input
The microcomputer is reset when supplying “L” level
to this pin.
XIN
Clock input
Input
XOUT
Clock output
Output
These are I/O pins of the internal clock generating
circuit. Connect a ceramic resonator or quartz-crystal
oscillator between X IN and X OUT pins. When using an
external clock, the clock source should be input to X IN
pin and X OUT pin _
should be left open.
_
Output
E
Enable output
BYTE
External data bus width Input
selection input
AVcc
[Memory expansion mode] [Microprocessor mode]
Input level to this pin determines whether the external
data bus has a 16-bit width or 8-bit width. The width
is 16 bits when the level is “L”, and 8 bits when the
level is “H.”
The power supply pin for the A-D converter. Externally
connect AVcc to Vcc pin.
Analog supply input
The power supply pin for the A-D converter. Externally
connect AVss to Vss pin.
AVss
VREF
This pin outputs E signal.
Data/instruction code read or data write is performed
when output from this pin is “L” level.
Reference voltage input Input
This is a reference voltage input pin for the A-D converter.
7751 Group User’s Manual
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DESCRIPTION
1.3 Pin description
Table 1.3.2 Pin description (2)
Pin
P00–P0 7
Name
I/O port P0
Input/Output
I/O
Functions
[Single-chip mode]
Port P0 is an 8-bit CMOS I/O port. This port has an
I/O direction register and each pin can be programmed
for input or output.
A0–A 7
P10–P1 7
I/O port P1
Output
[Memory expansion mode] [Microprocessor mode]
Low-order 8 bits (A0–A 7) of the address are output.
I/O
[Single-chip mode]
Port P1 is an 8-bit I/O port with the same function as
P0.
A8/D8–
[Memory expansion mode] [Microprocessor mode]
A15/D15
●External bus width = 8 bits (When the BYTE pin is
“H” level)
Middle-order 8 bits (A8–A15) of the address are output.
●External bus width = 16 bits (When the BYTE pin is
“L” level)
Data (D8 to D15) input/output and output of the middleorder 8 bits (A 8–A 15) of the address are performed
with the time sharing system.
P20–P2 7
I/O port P2
[Single-chip mode]
I/O
Port P2 is an 8-bit I/O port with the same function as P0.
A16/D0–
[Memory expansion mode] [Microprocessor mode]
A23/D7
Data (D 0 to D 7) input/output and output of the highorder 8 bits (A 16–A 23) of the address are performed
with the time sharing system.
[Single-chip mode]
P30–P3 3
I/O port P3
I/O
Port P3 is a 4-bit I/O port with the same function as P0.
__
R/W,
BHE,
ALE,
____
Output
[Memory expansion mode] [Microprocessor
mode]
__ ____
_____
_____
P30–P33 respectively output R/W, BHE, ALE, and HLDA
signals.
__
HLDA
●R/W
The Read/Write signal indicates the data bus state.
The state is read while this signal is “H” level, and
write
while this is “L” level.
____
●BHE
“L” level is output when an odd-numbered address is
accessed.
●ALE
This is used to obtain only the address from address
and
data multiplex signals.
_____
●HLDA
This is the signal to externally indicate the state when
the microcomputer is in Hold state.
“L” level is output during Hold state.
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7751 Group User’s Manual
DESCRIPTION
1.3 Pin description
Table 1.3.3 Pin description (3)
Pin
P4 0–P47
Name
I/O port P4
Input/Output
I/O
Functions
[Single-chip mode]
Port P4 is an 8-bit I/O port with the same function as
P0. P42 can be programmed as the clock φ 1 output pin.
_____
HOLD,
Input
[Memory expansion _____
mode]
RDY,
Input
P4 2–P47
I/O
P40 functions as the HOLD input pin, P41 as the RDY
input pin. The microcomputer
is in Hold state while “L”
_____
level is input to the HOLD pin.
____
____
The microcomputer
is in Ready state while “L” level is
____
input to the RDY pin.
P4 2–P4 7 function as I/O ports with the same functions
as P0.
P4 2 can be programmed for the clock φ 1 output pin.
_____
Input
Input
HOLD,
____
RDY,
φ 1,
P4 3–P47
[Microprocessor mode]
_____
Output
I/O
____
P40 functions as the HOLD input pin, P41 as the RDY
input pin. P4 2 always functions as the clock φ1 output
pin.
P4 3–P4 7 function as I/O ports with the same functions
as P0.
P5 0–P57
I/O port P5
I/O
P6 0–P67
I/O port P6
I/O
P7 0–P77
I/O port P7
I/O
Port P7 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as input pins for
A-D converter.
P8 0–P87
I/O port P8
I/O
Port P8 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as I/O pins for
serial I/O.
Port P5 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as I/O pins for
Timers A0–A3.
Port P6 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as I/O pins for
Timer A4, input pins for external interrupt and input
pins for Timers B0–B2.
7751 Group User’s Manual
1–7
DESCRIPTION
1.4 Block diagram
1.4 Block diagram
External data bus
width selection input
BYTE
Figure 1.4.1 shows the M37751 block diagram.
Data Bus (Even)
Stack Pointer S (16)
Input/Output
port P2
Input/Output
port P3
Input/Output
port P4
P2 (8)
P3 (4)
P4 (8)
P5 (8)
A-D Converter (10)
UART1 (9)
UART0 (9)
Timer B1 (16)
Direct Page Register DPR (16)
Timer B0 (16)
Reset input
RESET
Processor Status Register PS (11)
Timer A1 (16)
Input Buffer Register IB (16)
Timer A0 (16)
VCC
Data Bank Register DT (8)
Timer B2 (16)
Program Bank Register PG (8)
Timer A2 (16)
(0V)
VSS
Progtamu Counter PC (16)
Central Processing Unit (CPU)
Incrementer/Decrementer (24)
Watchdog Timer
CNVss
Data Address Register DA (24)
Timer A3 (16)
Program Address Register PA (24)
Address Bus
Input/Output
port P5
P1 (8)
Instruction Queue Buffer Q2 (8)
Input/Output
port P1
Instruction Queue Buffer Q1 (8)
Incrementer (24)
(0V)
AVSS
P0 (8)
Instruction Queue Buffer Q0 (8)
Bus
Interface
Unit
(BIU)
AVCC
Reference
voltage input
VREF
Instruction Register (8)
Data Buffer DBL (8)
Input/Output
port P0
Data Bus (Odd)
Data Buffer DBH (8)
P6 (8)
RAM
2048 bytes
P7 (8)
Input/Output
port P7
ROM
48 Kbytes
P8 (8)
Input/Output
port P8
Accumulator A (16)
Arithmetic Logic
Unit (16)
Fig. 1.4.1 M37751 block diagram
1–8
Input/Output
port P6
Accumulator B (16)
Clock generating circuit
Clock input Clock output
XIN
XOUT
Enable output
E
Index Register X (16)
Timer A4 (16)
Index Register Y (16)
7751 Group User’s Manual
CHAPTER 2
CENTRAL
PROCESSING UNIT
(CPU)
2.1
2.2
2.3
2.4
2.5
Central processing unit
Bus interface unit
Access space
Memory assignment
Processor modes
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1 Central processing unit
The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1.
b15
b0
b8 b7
AH
b15
b0
b8 b7
BH
Accumulator B (B)
BL
b15
b0
b8 b7
XH
Index register X (X)
XL
b15
b0
b8 b7
YH
YL
b15
Index register Y (Y)
b0
b8 b7
SH
b7
Accumulator A (A)
AL
Stack pointer (S)
SL
b0
Data bank register (DT)
DT
b16 b15
b23
b8 b7
PG
b0
PCH
b7
Program counter (PC)
PCL
b0
Program bank register (PG)
b15
b0
b8 b7
DPRH
b15
DPRL
b0
b8 b7
PSH
b15
0
b10
0
0
0
0
Direct page register (DPR)
b9 b8 b7 b6
IPL
Processor status register (PS)
PSL
N V
b5 b4 b3 b2
b1
b0
m
Z
C
x
D
I
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level
Fig. 2.1.1 CPU registers structure
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.1 Accumulator (Acc)
Accumulators A and B are available.
(1) Accumulator A (A)
Accumulator A is the main register of the microcomputer. The transaction of data such as calculation,
data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits,
and the low-order 8 bits can also be used separately. The data length flag (m) determines whether
the register is used as a 16-bit register or as an 8-bit register. Flag m is a part of the processor status
register which is described later. When an 8-bit register is selected, only the low-order 8 bits of
accumulator A are used and the contents of the high-order 8 bits is unchanged.
(2) Accumulator B (B)
Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be
used instead of accumulator A. The use of accumulator B, however except for some instructions,
requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B is
also controlled by the data length flag (m) just as in accumulator A.
2.1.2 Index register X (X)
Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register
length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag x
is a part of the processor status register which is described later. When an 8-bit register is selected, only
the low-order 8 bits of index register X are used and the contents of the high-order 8 bits is unchanged.
In an addressing mode in which index register X is used as an index register, the address obtained by
adding the contents of this register to the operand’s contents is accessed.
In the MVP or MVN instruction, a block transfer instruction, the contents of index register X indicate the
low-order 16 bits of the source address. The third byte of the instruction is the high-order 8 bits of the
source address.
In the RMPA instruction, a Repeat MultiPly and Accumulate instruction, the contents of index register X
indicate the low-order 16 bits of address in which multiplicands are stored.
Note: Refer to “7751 Series Software Manual” for addressing modes.
2.1.3 Index register Y (Y)
Index register Y is a 16-bit register with the same function as index register X. Just as in index register
X, the index register length flag (x) determines whether this register is used as a 16-bit register or as an
8-bit register.
In the MVP or MVN instruction, a block transfer instruction, the contents of index register Y indicate the
low-order 16 bits of the destination address. The second byte of the instruction is the high-order 8 bits of
the destination address.
In the RMPA instruction, a Repeat MultiPly and Accumulate instruction, the contents of index register Y
indicate the low-order 16 bits of address in which multipliers are stored.
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.4 Stack pointer (S)
The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when
addressing modes using the stack are executed. The contents of S indicate an address (stack area) for
storing registers during subroutine calls and interrupts. Bank 0 16 is specified for the stack area. (Refer to
“2.1.6 Program bank register (PG).”)
When an interrupt request is accepted, the microcomputer stores the contents of the program bank register
(PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the
contents of the program counter (PC) and the processor status register (PS) are stored. The contents of
S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting
of the interrupt request. (Refer to Figure 2.1.2.)
When completing the process in the interrupt routine and returning to the original routine, the contents of
registers stored in the stack area are restored into the original registers in the reverse sequence (PS→PC→PG)
by executing the RTI instruction. The contents of S is returned to the state before accepting an interrupt
request.
The same operation is performed during a subroutine call, however, the contents of PS is not automatically
stored. (The contents of PG may not be stored. This depends on the addressing mode.)
The user should store registers other than those described above with software when the user needs them
during interrupts or subroutine calls.
Additionally, initialize S at the beginning of the program because its contents are undefined at reset. The
stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore,
make sure of the subroutine’s nesting depth not to destroy the necessary data.
Note: Refer to “7751 Series Software Manual” for addressing modes.
Stack area
Address
S–5
S–4
Processor status register’s low-order byte (PSL)
S–3 Processor status register’s high-order byte (PSH)
S–2
Program counter’s low-order byte (PCL)
S–1
Program counter’s high-order byte (PCH)
S
Program bank register (PG)
● “S” is the initial address that the stack pointer (S)
indicates at accepting an interrupt request.
The S’s contents become “S–5” after storing the
above registers.
Fig. 2.1.2 Stored registers of the stack area
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.5 Program counter (PC)
The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at
which an instruction to be executed next (in other words, an instruction to be read out from an instruction
queue buffer next) is stored. The contents of the high-order program counter (PCH) become “FF16,” and the
low-order program counter (PCL) becomes “FE16” at reset. The contents of the program counter becomes
the contents of the reset’s vector address (addresses FFFE 16, FFFF 16) immediately after reset.
Figure 2.1.3 shows the program counter and the program bank register.
(b23)
b7
(b16)
b0 b15
PG
b8 b7
PCH
b0
PCL
Fig. 2.1.3 Program counter and program bank register
2.1.6 Program bank register (PG)
The program bank register is an 8-bit register. This register indicates the high-order 8 bits (bank) of the
address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out
from an instruction queue buffer next) is stored. These 8 bits are called bank.
When a carry occurs after adding the contents of the program counter or adding the offset value to the
contents of the program counter in the branch instruction and others, the contents of the program bank
register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the
program counter, the contents of the program bank register is automatically decremented by 1. Accordingly,
there is no need to consider bank boundaries in programming, usually.
In the single-chip mode, make sure to prevent the program bank register from being set to the value other
than “0016” by executing the branch instructions and others. It is because the access space of the singlechip mode is the internal area within the bank 016.
This register is cleared to “0016” at reset.
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.7 Data bank register (DT)
The data bank register is an 8-bit register. In the following addressing modes using the data bank register,
the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed.
Use the LDT instruction to set a value to this register.
In the single-chip mode, make sure to fix this register to “00 16”. It is because the access space of the
single-chip mode is the internal area within the bank 016.
This register is cleared to “00 16” at reset.
●Addressing modes using data bank register
•Direct indirect
•Direct indexed X indirect
•Direct indirect indexed Y
•Absolute
•Absolute bit
•Absolute indexed X
•Absolute indexed Y
•Absolute bit relative
•Stack pointer relative indirect indexed Y
•Multiplied accumulation
2.1.8 Direct page register (DPR)
The direct page register is a 16-bit register. The contents of this register indicate the direct page area
which is allocated in bank 0 16 or in the space across banks 0 16 and 1 16. The following addressing modes
use the direct page register.
The contents of the direct page register indicate the base address (the lowest address) of the direct page
area. The space which extends to 256 bytes above that address is specified as a direct page.
The direct page register can contain a value from “000016” to “FFFF16.” When it contains a value equal to
or more than “FF01 16,” the direct page area spans the space across banks 0 16 and 1 16.
When the contents of low-order 8 bits of the direct page register is “0016,” the number of cycles required
to generate an address is 1 cycle smaller than the number when its contents are not “0016.” Accordingly,
the access efficiency can be enhanced in this case.
This register is cleared to “000016” at reset.
Figure 2.1.4 shows a setting example of the direct page area.
●Addressing modes using direct page register
•Direct
•Direct bit
•Direct indexed X
•Direct indexed Y
•Direct indirect
•Direct indexed X indirect
•Direct indirect indexed Y
•Direct indirect long
•Direct indirect long indexed Y
•Direct bit relative
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
016
016
Direct page area when DPR = “000016”
FF16
12316
Bank 016
22216
Direct page area when DPR = “012316”
(Note 1)
FF1016
FFFF16
1000016
1000F16
Direct page area when DPR = “FF1016”
(Note 2)
Bank 116
Notes 1 : The number of cycles required to generate an address is 1 cycle smaller when the
low-order 8 bits of the DPR are “00 16 .”
2 : The direct page area spans the space across banks 0 16 and 1 16 when the DPR is
“FF01 16” or more.
Fig. 2.1.4 Setting example of direct page area
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.9 Processor status register (PS)
The processor status register is an 11-bit register.
Figure 2.1.5 shows the structure of the processor status register.
b15 b14 b13 b12 b11 b10 b9
0
0
0
0
0
IPL
b8
b7
b6
b5
b4
b3
b2
b1
b0
N
V
m
x
D
I
Z
C
Processor status
register (PS)
Note: Fix bits 11–15 to “0.”
Fig. 2.1.5 Processor status register structure
(1) Bit 0: Carry flag (C)
It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic
operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction
is executed, this flag’s contents determine whether the program causes a branch or not.
Use the SEC or SEP instruction to set this flag to “1,” and use the CLC or CLP instruction to clear
it to “0.”
(2) Bit 1: Zero flag (Z)
It is set to “1” when a result of an arithmetic operation or data transfer is “0,” and cleared to “0” when
otherwise. When the BNE or BEQ instruction is executed, this flag’s contents determine whether the
program causes a branch or not.
Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode addition (the ADC instruction).
(3) Bit 2: Interrupt disable flag (I)
It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and
zero division). Interrupts are disabled when this flag is “1.” When an interrupt request is accepted,
this flag is automatically set to “1” to avoid multiple interrupts. Use the SEI or SEP instruction to set
this flag to “1,” and use the CLI or CLP instruction to clear it to “0.” This flag is set to “1” at reset.
(4) Bit 3: Decimal mode flag (D)
It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic
is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed with each word
treated as two or four digits decimal (determined by the data length flag). Decimal adjust is automatically
performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP
instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared
to “0” at reset.
(5) Bit 4: Index register length flag (x)
It determines whether each of index register X and index register Y is used as a 16-bit register or
an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as an 8-bit
register when it is “1.” Use the SEP instruction to set this flag to “1,” and use the CLP instruction
to clear it to “0.” This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, the data is transferred
with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS
instructions. Refer to “7751 Series Software Manual” for details.
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
(6) Bit 5: Data length flag (m)
It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16bit unit when this flag is “0,” and as an 8-bit unit when it is “1.”
Use the SEM or SEP instruction to set this flag to “1,” and use the CLM or CLP instruction to clear
it to “0.” This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, the data is transferred
with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS
instructions. Refer to “7751 Series Software Manual” for details.
(7) Bit 6: Overflow flag (V)
It is used when adding or subtracting with a word regarded as signed binary. When the data length
flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the
range between –32768 and +32767, and cleared to “0” in all other cases. When the data length flag
(m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range
between –128 and +127, and cleared to “0” in all other cases.
The overflow flag is also set to “1” when a result of division exceeds the register length to be stored
in the DIV or DIVS instruction, a division instruction with unsigned or signed; and when a result of
addition exceeds the range between –2147483648 and +2147483647 in the RMPA instruction, a
Repeat MultiPly and Accumulate instruction.
When the BVC or BVS instruction is executed, this flag’s contents determine whether the program
causes a branch or not.
Use the SEP instruction to set this flag to “1,” and use the CLV or CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
(8) Bit 7: Negative flag (N)
It is set to “1” when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result
is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m)
is “1.”) It is cleared to “0” in all other cases. When the BPL or BMI instruction is executed, this flag
determines whether the program causes a branch or not. Use the SEP instruction to set this flag to
“1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
(9) Bits 10 to 8: Processor interrupt priority level (IPL)
These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The
interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each
interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in
the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request.
There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the
new IPL into the stack area and updating the processor status register with the PUL or PLP instruction.
The contents of IPL is cleared to “000 2” at reset.
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2 Bus interface unit
A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory•I/O devices.
BIU’s function and operation are described below.
When externally connecting devices, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
2.2.1 Overview
Transfer operation between the CPU and memory•I/O devices is always performed via the BIU.
Figure 2.2.1 shows the bus and bus interface unit (BIU).
➀ The BIU reads an instruction from the memory before the CPU executes it.
➁ When the CPU reads data from the memory•I/O device, the CPU first specifies the address from which
data is read to the BIU. The BIU reads data from the specified address and passes it to the CPU.
➂ When the CPU writes data to the memory•I/O device, the CPU first specifies the address to which data
is written to the BIU and write data. The BIU writes the data to the specified address.
➃ To perform the above operations ➀ to ➂, the BIU inputs and outputs the control signals, and control the
bus.
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7751 Group User’s Manual
(BIU)
(CPU)
7751 Group User’s Manual
Internal control signal
Internal bus A0 to A23
Internal bus D0 to D7
Internal bus D8 to D15
Internal bus
Bus
conversion
circuit
Internal
peripheral
device
(SFR)
Internal
memory
Notes 1: The CPU bus, internal bus, and external bus are independent of one another.
2: Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about control signals
of the external bus.
SFR : Special Function Register
Bus
interface
unit
CPU bus
Central
processing
unit
M37751
Control signals
A16/D0 to A23/D7
A8/D8 to A15/D15
A0 to A7
External bus
External
device
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
Fig. 2.2.1 Bus and bus interface unit (BIU)
2–11
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2.2 Functions of bus interface unit (BIU)
The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists the functions
of each register.
b0
b23
Program address register
PA
b0
b7
Q0
Instruction queue buffer
Q1
Q2
b23
b0
Data address register
DA
b15
b0
DBH
DBL
Data buffer
Fig. 2.2.2 Register structure of bus interface unit (BIU)
Table 2.2.1 Functions of each register
Name
Functions
Program address register
Indicates the storage address for the instruction which is next taken into the
instruction queue buffer.
Instruction queue buffer
Temporarily stores the instruction which has been taken in.
Data address register
Indicates the address for the data which is next read from or written to.
Data buffer
Temporarily stores the data which is read from the memory•I/O device by the
BIU or which is written to the memory•I/O device by the CPU.
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
The CPU and the bus send or receive data via BIU because each operates based on different clocks
(Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory • I/O
devices that require a long access time.
The BIU’s functions are described bellow.
φCPU. The period of φCPU is normally
the same as that of φ. The internal
Note: The CPU operates based on _
_
bus operates based on the E signal. The period of the E signal is twice that of φ at a minimum.
(1) Reading out instruction (Instruction prefetch)
When the CPU does not require to read or write data, that is, when the bus is not in use, the BIU
reads instructions from the memory and stores them in the instruction queue buffer. This is called
instruction prefetch.
The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU
can operate at high speed without waiting for access to the memory which requires a long access
time.
When the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the BIU
performs instruction prefetch. The instruction queue buffer can store instructions up to 3 bytes.
The contents of the instruction queue buffer is initialized when a branch or jump instruction is
executed, and the BIU reads a new instruction from the destination address.
When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU
extends the pulse duration of clock φ CPU in order to keep the CPU waiting until the BIU fetches the
required number of instructions or more.
(2) Reading data from memory•I/O device
The CPU specifies the storage address of data to be read to the BIU’s data address register, and
requires data. The CPU waits until data is ready in the BIU.
The BIU outputs the address received from the CPU onto the address bus, reads contents at the
specified address, and takes it into the data buffer.
The CPU continues processing, using data in the data buffer.
However, if the BIU uses the bus for instruction prefetch when the CPU requires to read data, the
BIU keeps the CPU waiting.
(3) Writing data to memory•I/O device
The CPU specifies the address of data to be written to the BIU’s data address register. Then, the
CPU writes data into the data buffer. The BIU outputs the address received from the CPU onto the
address bus and writes data in the data buffer into the specified address.
The CPU advances to the next processing without waiting for completion of BIU’s write operation.
However, if the BIU uses the bus for instruction prefetch when the CPU requires to write data, the
BIU keeps the CPU waiting.
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
(4) Bus control
To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and
controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses
the memory•I/O device is called the bus cycle. Table 2.2.2 shows the bus cycle at accessing the
internal area.
Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about the bus cycle at accessing
the external devices.
Table 2.2.2 Bus cycle at accessing internal area
In low-speed running (f(XIN) ≤ 25 MHz)
RAM
In high-speed running (f(XIN) ≤ 40 MHz)
1 bus cycle = 2
1 bus cycle = 2
E
E
Internal address bus
Internal data bus
Address
Internal address bus
Data
Internal data bus
ROM
Address
Data
1 bus cycle = 3
E
SFR
Internal address bus
Internal data bus
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7751 Group User’s Manual
Address
Data
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2.3 Operation of bus interface unit (BIU)
Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU).
About signals which are input/output externally when accessing external devices, refer to “Chapter 12.
CONNECTION WITH EXTERNAL DEVICES.”
(1) When fetching instructions into the instruction queue buffer
➀ When the instruction which is next fetched is located at an even address, the BIU fetches 2 bytes
at a time with the timing of waveform (a).
However, when accessing an external device which is connected with the 8-bit external data bus
width (BYTE = “H”), only 1 byte is fetched.
➁ When the instruction which is next fetched is located at an odd address, the BIU fetches only 1
byte with the timing of waveform (a). The contents at the even address are not taken.
(2) When reading or writing data to and from the memory•I/O device
➀ When accessing a 16-bit data which begins at an even address, waveform (a) is applied. The 16
bits of data are accessed at a time.
➁ When accessing a 16-bit data which begins at an odd address, waveform (b) is applied. The 16
bits of data are accessed separately in 2 operations, 8 bits at a time. Invalid data is not fetched
into the data buffer.
➂ When accessing an 8-bit data at an even address, waveform (a) is applied. The data at the odd
address is not fetched into the data buffer.
➃ When accessing an 8-bit data at an odd address, waveform (a) is applied. The data at the even
address is not fetched into the data buffer.
For instructions that are affected by the data length flag (m) and the index register length flag (x),
operation ➀ or ➁ is applied when flag m or x = “0”; operation ➂ or ➃ is applied when flag m or x
= “1.”
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
(a)
E
Internal address bus (A0
to A23)
to D7)
Data (Even address)
to D15)
Data (Odd address)
Internal data bus (D0
Internal data bus (D8
Address
(b)
E
to A23)
Internal address bus (A0
Invalid data
Data (Even address)
to D15)
Data (Odd address)
Invalid data
Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU)
2–16
Address (Even address)
to D7)
Internal data bus (D0
Internal data bus (D8
Address (Odd address)
7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.3 Access space
2.3 Access space
Figure 2.3.1 shows the M37751’s access space.
By combination of the program counter (PC), which is 16 bits of structure, and the program bank register
(PG), a 16-Mbyte space from addresses 016 to FFFFFF16 can be accessed. For details about access of an
external area, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
The memory and I/O devices are allocated in the same access space. Accordingly, it is possible to perform
transfer and arithmetic operations using the same instructions without discrimination of the memory from
I/O devices.
000000 16
SFR area
00007F 16
000080 16
Internal RAM area
00087F 16
Bank 0 16
004000 16
Internal ROM area
00FFFF 16
010000 16
……
020000 16
……
Bank 1 16
FE0000 16
Bank FE 16
: Indicates the memory assignment of
the internal areas.
FF0000 16
Bank FF 16
FFFFFF 16
: Indicates that nothing is assigned.
Note : Memory assignment of internal area varies according to the type of microcomputer. This
figure shows the case of the M37751M6C-XXXFP.
Refer to “Appendix 1. Memory assignment” for other products.
SFR : Special Function Register
Fig. 2.3.1 M37751’s access space
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.3 Access space
2.3.1 Banks
The access space is divided in units of 64 Kbytes. This unit is called “bank.” The high-order 8 bits of
address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank
register (DT). Each bank can be accessed efficiently by using an addressing mode that uses the data bank
register (DT).
If the program counter (PC) overflows at a bank boundary, the contents of the program bank register (PG)
is incremented by 1. If a borrow occurs in the program counter (PC) as a result of subtraction, the contents
of the program bank register (PG) is decremented by 1. Normally, accordingly, the user can program
without concern for bank boundaries.
SFR (Special Function Register), internal RAM, and internal ROM are assigned in bank 016. For details,
refer to section “2.4 Memory assignment.”
2.3.2 Direct page
A 256-byte space specified by the direct page register (DPR) is called “direct page.” A direct page is
specified by setting the base address (the lowest address) of the area to be specified as a direct page into
the direct page register (DPR).
By using a direct page addressing mode, a direct page can be accessed with less instruction cycles than
otherwise.
Note: Refer also to section “2.1 Central processing unit.”
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
2.4 Memory assignment
This section describes the internal area’s memory assignment. For more information about the external
area, refer also to section “2.5 Processor modes.”
2.4.1 Memory assignment in internal area
SFR (Special Function Register), internal RAM, and internal ROM are assigned in the internal area. Figure
2.4.1 shows the internal area’s memory assignment.
(1) SFR area
The registers for setting internal peripheral devices are assigned at addresses 016 to 7F 16. This area
is called SFR (Special Function Register). Figure 2.4.2 shows the SFR area’s memory assignment.
For each register in the SFR area, refer to each functional description in this manual.
For the state of the SFR area immediately after a reset, refer to section “13.1.2 State of CPU, SFR
area, and internal RAM area.”
(2) Internal RAM area
The M37751M6C-XXXFP (See Note) assigns the 2048-byte static RAM at addresses 8016 to 87F 16.
The internal RAM area is used as a stack area, as well as an area to store data. Accordingly, note
that set the nesting depth of a subroutine and multiple interrupts’ level not to destroy the necessary
data.
(3) Internal ROM area
The M37751M6C-XXXFP (See Note) assigns the 48-Kbyte mask RAM at addresses 4000 16 to FFFF16.
Its addresses FFD616 to FFFF16 are the vector addresses, which are called the interrupt vector table,
for reset and interrupts. In the microprocessor mode where use of the internal ROM area is inhibited,
assign a ROM at addresses FFD616 to FFFF 16.
Note : Refer to “Appendix 1. Memory assignment” for other products.
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
000000 16
00007F 16
000080 16
SFR area
Refer to Figure 2.4.2.
Internal RAM area
00087F 16
FFD6 16
004000 16
FFD8 16
FFDA 16
FFDC 16
FFDE 16
FFE0 16
FFE2 16
FFE4 16
FFE6 16
Internal ROM area
FFE8 16
FFEA 16
FFEC 16
FFEE 16
FFF016
FFF216
FFF416
FFF616
00FFD6 16
FFF816
FFFA 16
FFFC 16
FFFE 16
00FFFF 16
Interrupt vector table
A-D conversion L
H
L
UART1 transmit
H
L
UART1 receive H
L
UART0 transmit
H
UART0 receive L
H
L
Timer B2 H
L
Timer B1 H
L
Timer B0 H
L
Timer A4 H
L
Timer A3 H
L
Timer A2 H
L
Timer A1 H
L
Timer A0 H
L
INT2
H
L
INT1
H
L
INT0
H
L
Watchdog timer H
L
DBC (Note 1) H
BRK instruction L
H
L
zero divide
H
L
RESET
H
M37751M6C-XXXFP
: The internal memory is not assigned.
Notes 1: DBC is an interrupt only for debugging; do not use this interrupt.
2: Access to the internal ROM area is disabled in the microprocessor mode.
(Refer to section “2.5 Processor modes.” )
3: Memory assignment of internal area varies according to the type of microcomputer.
Refer to “Appendix 1. Memory assignment” for other products.
Fig. 2.4.1 Internal area’s memory assignment
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
Address
016
116
216 Port P0 register
316 Port P1 register
416 Port P0 direction register
516 Port P1 direction register
616 Port P2 register
716 Port P3 register
816 Port P2 direction register
916 Port P3 direction register
A16 Port P4 register
B16 Port P5 register
C16 Port P4 direction register
D16 Port P5 direction register
E16 Port P6 register
F16 Port P7 register
1016 Port P6 direction register
1116 Port P7 direction register
1216 Port P8 register
1316
1416 Port P8 direction register
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
1E16 A-D control register 0
1F16 A-D control register 1
2016 A-D register 0
2116
2216 A-D register 1
2316
2416
A-D register 2
2516
2616
A-D register 3
2716
2816 A-D register 4
2916
2A16 A-D register 5
2B16
2C16 A-D register 6
2D16
2E16 A-D register 7
2F16
3016 UART0 transmit/receive mode register
3116 UART0 baud rate register (BRG0)
3216 UART0 transmit buffer register
3316
3416 UART0 transmit/receive control register 0
3516 UART0 transmit/receive control register 1
3616 UART0 receive buffer register
3716
3816 UART1 transmit/receive mode register
3916 UART1 baud rate register (BRG1)
3A16
UART1 transmit buffer register
3B16
3C16 UART1 transmit/receive control register 0
3D16 UART1 transmit/receive control register 1
3E16
UART1 receive buffer register
3F16
Address
4016 Count start register
4116
4216 One-shot start register
4316
4416 Up-down register
4516
4616 Timer A0 register
4716
4816 Timer A1 register
4916
4A16 Timer A2 register
4B16
4C16 Timer A3 register
4D16
4E16 Timer A4 register
4F16
5016 Timer B0 register
5116
5216 Timer B1 register
5316
5416 Timer B2 register
5516
5616 Timer A0 mode register
5716 Timer A1 mode register
5816 Timer A2 mode register
5916 Timer A3 mode register
5A16 Timer A4 mode register
5B16 Timer B0 mode register
5C16 Timer B1 mode register
5D16 Timer B2 mode register
5E16 Processor mode register 0
5F16 Processor mode register 1
6016 Watchdog timer register
6116 Watchdog timer frequency select register
6216
6316
6416
6516
6616
6716
6816
6916
6A16
6B16
6C16
6D16
6E16
6F16
7016 A-D conversion interrupt control register
7116 UART0 transmit interrupt control register
7216 UART0 receive interrupt control register
7316 UART1 transmit interrupt control register
7416 UART1 receive interrupt control register
7516 Timer A0 interrupt control register
7616 Timer A1 interrupt control register
7716 Timer A2 interrupt control register
7816 Timer A3 interrupt control register
7916 Timer A4 interrupt control register
7A16 Timer B0 interrupt control register
7B16 Timer B1 interrupt control register
7C16 Timer B2 interrupt control register
7D16 INT0 interrupt control register
7E16 INT1 interrupt control register
7F16 INT2 interrupt control register
Fig. 2.4.2 SFR area’s memory map
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5 Processor modes
The M37751 can operate in 3 processor modes: single-chip mode, memory expansion mode, and microprocessor
mode. Some pins’ functions, memory assignment, and access space vary according to the processor modes.
This section describes the differences between the processor modes. Figure 2.5.1 shows a memory assignment
in each processor mode.
Single-chip mode
Memory expansion mode
Microprocessor mode
SFR area
SFR area
SFR area
Memory expansion mode
Microprocessor mode
00000016
00000216
(Note 1)
00008016
00000916
Internal
RAM area
Internal
RAM area
Internal
RAM area
00087F16
00088016
Not used
003FFF16
00400016
Internal
ROM area
Internal
ROM area
00FFFF16
01000016
FFFFFF16
: External area; Accessing this area make it possible to access external connected devices.
Notes 1: Addresses 216 to 916 become a external area in the memory expansion mode and microprocessor mode.
2: Refer to “Appendix 1. Memory assignment” for products other than M37751M6C–XXXFP.
Fig. 2.5.1 Memory assignment in each processor mode for M37751M6C-XXXFP
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5.1 Single-chip mode
Use this mode when not using external devices. In this mode, ports P0 to P8 function as programmable
I/O ports (when using an internal peripheral device, they function as its I/O pins).
In the single-chip mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed.
2.5.2 Memory expansion and microprocessor modes
Use these modes when connecting devices externally. In these modes, an external device can be connected
to any required location in the 16-Mbyte access space. For access to external devices, refer to “Chapter
12. CONNECTION WITH EXTERNAL DEVICES.”
The memory expansion and microprocessor modes have the same functions except for the following:
•In the microprocessor mode, access to the internal ROM area is disabled by force, and the internal ROM
area is handled as an external area.
•In the microprocessor mode, port P42 always functions as the clock φ1 output pin.
In the memory expansion and microprocessor modes, P0 to P3, P40, and P41 function as the I/O pins for
the signals required for accessing external devices. Consequently, these pins cannot be used as programmable
I/O ports.
If an external device is connected with an area with which the internal area overlaps, when this overlapping
area is read, data in the internal area is taken in the CPU, but data in the external area is not taken in.
If data is written to an overlapping area, the data is written to the internal area, and a signal is output
externally at the same timing as writing to the internal area.
Figure 2.5.2 shows a pin configuration in each processor mode. Table 2.5.1 lists the functions of P0 to P4
in each processor mode.
For the function of each pin, refer to section “1.3 Pin description,” “Chapter 3. INPUT/OUTPUT PINS,”
and “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
●Single-chip mode
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
41
65
40
66
39
67
38
68
37
69
36
70
35
71
34
M37751M6C–XXXFP
72
73
33
32
74
31
75
30
76
29
77
28
78
27
79
26
80
25
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
✽1 Connect this pin to Vss pin in the single-chip
mode.
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
P42/φ1
P41
1
P24
P25
P26
P27
P30
P31
P32
P33
Vss
E
XOUT
XIN
RESET
CNVSS ✽1
BYTE
P40
: These pins have different functions between the
single-chip and the memory expansion/microprocessor modes.
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
A0
A1
A2
A3
A4
A5
A6
A7
A8/D8
A9/D9
A10/D10
A11/D11
A12/D12
A13/D13
A14/D14
A15/D15
A16/D0
A17/D1
A18/D2
A19/D3
●Memory expansion/Microprocessor mode
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
41
65
40
66
39
67
38
68
37
69
36
70
35
71
34
M37751M6C–XXXFP
72
73
33
32
74
31
75
30
76
29
77
28
78
27
79
26
80
25
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
✽2 P42/φ1
RDY
1
Fig. 2.5.2 Pin configuration in each processor mode (top view)
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7751 Group User’s Manual
A20/D4
A21/D5
A22/D6
A23/D7
R/W
BHE
ALE
HLDA
Vss
E
XOUT
XIN
RESET
CNVSS
BYTE
HOLD
✽2 This pin functions as φ1 in the microprocessor
mode.
: These pins have different functions between the
single-chip and the memory expansion/microprocessor modes.
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
Table 2.5.1 Functions of ports P0 to P4 in each processor mode
Processor
Single-chip mode
Memory expansion/Microprocessor mode
modes
Pins
P0
A0 – A7
P
P: Functions as a programmable
I/O port.
P1
• When external data bus width is 16 bits (BYTE = “L”)
P
P: Functions as a programmable
I/O port.
D(odd)
A8 – A15
D (odd): Data at odd address
• When external data bus width is 8 bits (BYTE = “H”)
A8 – A15
P2
• When external data bus width is 16 bits (BYTE = “L”)
P
D(even)
A16 – A23
P: Functions as a programmable
I/O port.
D (even): Data at even address
• When external data bus width is 8 bits (BYTE = “H”)
D
A16 – A23
D : Data
P3
P33
P
P: Functions as a programmable
I/O port.
P4
HLDA
ALE
P32
P31
BHE
P30
R/W
P43 – P47
P
P: Functions as a programmable
I/O port.
(Note 1)
P
P: Functions as a programmable I/O port.
P42
(Note 2)
1
P41
RDY
P40
HOLD
Notes 1: P42 also functions as the clock 1 output pin. (Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”)
2: P42 functions as a programmable I/O port in the memory expansion mode, and that functions as the clock 1 output pin by software
selection. (Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”)
3: This table lists a switch of pins’ functions by switching the processor mode. Refer to the following section about the input/output
timing of each signal:
•“Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
•“Chapter 15. ELECTRICAL CHARACTERISTICS.”
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5.3 Setting processor modes
The voltage supplied to the CNVss pin and the processor mode bits (bits 1 and 0 at address 5E16) set the
processor mode.
●When Vss level is supplied to CNVss pin
After a reset, the microcomputer starts operating in the single-chip mode. The processor mode is switched
by the processor mode bits after the microcomputer starts operating. When the processor mode bits are
set to “01 2 ,” the microcomputer enters the memory expansion mode; when these bits are set to “10 2,”
the microcomputer enters the microprocessor mode.
_
The processor mode is switched at the rising edge of signal E after writing to the processor mode bits.
Figure 2.5.3 shows the timing when pin functions are switched by switching the processor mode from the
single-chip mode to the memory expansion or microprocessor mode with the processor mode bits.
When the processor mode is switched during the program execution, the contents of the instruction
queue buffer is not initialized. (Refer to “Appendix 9. Q & A.”)
●When Vcc level is supplied to CNVss pin
After a reset, the microcomputer starts operating in the microprocessor mode. In this case, the microcomputer
cannot operate in the other modes. (Fix the processor mode bits to “102 .”)
Table 2.5.2 lists the methods for setting processor modes. Figure 2.5.4 shows the structure of processor
mode register 0 (address 5E 16).
Written to processor mode bits
E
P00
Programmable I/O port P00
External address bus A0
Note: Functions of pins P01 to P07, P1 to P3, P40 to P42 are switched at the same timing shown above.
Function of pin P42 is, however, switched only when the processor mode is switched to the
microprocessor mode.
Fig. 2.5.3 Timing when pin functions are switched
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
Table 2.5.2 Methods for setting processor modes
Processor mode
CNVss pin level
Processor mode bits
b1
Single-chip mode
Vss (0 V) (Note 1)
0
b0
0
Memory expansion mode
Vss (0 V) (Note 1)
Microprocessor mode
Vss (0 V) (Note 1)
Vcc (5 V) (Note 2)
0
1
1
0
Notes 1: The microcomputer starts operating in the single-chip mode after a reset. The microcomputer can
be switched to the other processor modes by setting the processor mode bits.
2: The microcomputer starts operating in the microprocessor mode after a reset. The microcomputer
cannot operate in the other modes, so that fix the processor mode bits as follows:
•b1 = “1” and b0 = “0.”
b7
b6
0
b5
b4
b3
b2
0
b1
b0
Processor mode register 0 (Address 5E16)
Bit
0
Bit name
Processor mode bits
1
2
Fix this bit to “0.”
3
Software reset bit
4
Interrupt priority detection time
select bits
5
6
Fix this bit to “0.”
7
Clock φ1 output select bit
(Note 2)
Functions
At reset
RW
0
RW
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not selected
0
RW
(Note 1)
0
RW
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0
WO
b5 b4
0
RW
0
RW
0
RW
0
RW
0 0 : 7 cycles of φ
0 1 : 4 cycles of φ
1 0 : 2 cycles of φ
1 1 : Not selected
0 : Clock φ1 output disabled
(P42 functions as a programmable
I/O port.)
1 : Clock φ1 output enabled
(P42 functions as a clock φ1 output pin.)
Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1”
after a reset. (Fixed to “1.”)
2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”)
: Bits 7 to 2 are not used for setting of the processor mode.
Fig. 2.5.4 Structure of processor mode register 0
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
[Precautions when operating in single-chip mode]
The bus cycle select bits (bits 4 and 5 at address 5F16) is not used in the single-chip mode. However, do
not make those bits state of not selected in all cases. Especially in low-speed running, rewrite both bits
at the same time to “012,” “10 2” or “11 2.” These bits are cleared to “002” at reset.
b7
b6
0 0
b5
b4
b3
b2
b1
b0
0 0
Processor mode register 1 (Address 5F16)
Bit
1, 0
Bit name
Functions
Fix these bits to “0.”
At reset
RW
0
RW
2
Clock source for peripheral
devices select bit
(Note)
0:
1:
divided by 2
0
RW
3
CPU running speed select bit
(Note)
0 : High-speed running
1 : Low-speed running
0
RW
4
Bus cycle select bits
In high-speed running
0
RW
0
RW
0
RW
b5 b4
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
In low-speed running
5
b5 b4
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
7, 6
Fix these bits to “0.”
Note: Fix this bit to “0” when f(XIN ) > 25 MHz.
Fig. 2.5.5 Structure of processor mode register 1
2–28
7751 Group User’s Manual
CHAPTER 3
INPUT/OUTPUT
PINS
3.1 Programmable I/O ports
3.2 I/O pins of internal peripheral devices
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
This chapter describes the programmable I/O ports in the single-chip mode. For P0 to P4, which change
their functions according to the processor mode, refer also to the section “2.5 Processor modes” and
“Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
3.1 Programmable I/O ports
The 7751 Group has 68 programmable I/O ports, P0 to P8.
The programmable I/O ports have direction registers and port registers in the SFR area. Figure 3.1.1 shows
the memory map of direction registers and port registers.
P4 2 and P5 to P8 also function as the I/O pins of the internal peripheral devices. For the functions, refer
to the section “3.2 I/O pins of internal peripheral devices” and relevant sections of each internal peripheral
devices.
Addresses
216
Port P0 register
316
Port P1 register
416
Port P0 direction register
516
Port P1 direction register
616
Port P2 register
716
Port P3 register
816
Port P2 direction register
916
Port P3 direction register
A16 Port P4 register
B16 Port P5 register
C16
Port P4 direction register
D16
Port P5 direction register
E16 Port P6 register
F16 Port P7 register
1016
Port P6 direction register
1116
Port P7 direction register
1216
Port P8 register
1316
1416
Port P8 direction register
Fig. 3.1.1 Memory map of direction registers and port registers
3–2
7751 Group User’s Manual
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
3.1.1 Direction register
This register determines the input/output direction of the programmable I/O port. Each bit of this register
corresponds one for one to each pin of the microcomputer.
Figure 3.1.2 shows the structure of port Pi (i = 0 to 8) direction register.
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi direction register (i = 0 to 8)
(Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416)
Bit
Bit name
Functions
At reset
RW
0
RW
0
RW
0
RW
0
Port Pi0 direction bit
1
Port Pi1 direction bit
2
Port Pi2 direction bit
3
Port Pi3 direction bit
0
RW
4
Port Pi4 direction bit
0
RW
5
Port Pi5 direction bit
0
RW
6
Port Pi6 direction bit
0
RW
7
Port Pi7 direction bit
0
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Note: Bits 7 to 4 of the port P3 direction register cannot be written and are fixed to “0” at reading.
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Corresponding
pin
Pi7
Pi6
Pi5
Pi4
Pi3
Pi2
Pi1
Pi0
Fig. 3.1.2 Structure of port Pi (i = 0 to 8) direction register
7751 Group User’s Manual
3–3
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
3.1.2 Port register
Data is input/output to/from externals by writing/reading data to/from the port register. The port register
consists of a port latch which holds the output data and a circuit which reads the pin state. Each bit of the
port register corresponds one for one to each pin of the microcomputer. Figure 3.1.3 shows the structure
of the port Pi (i = 0 to 8) register.
● When outputting data from programmable I/O ports set to output mode
➀ By writing data to the corresponding bit of the port register, the data is written into the port latch.
➁ The data is output from the pin according to the contents of the port latch.
By reading the port register of a port set to output mode, the contents of the port latch is read out,
instead of the pin state. Accordingly, the output data is correctly read without being affected by an
external load. (Refer to Figures 3.1.4 and 3.1.5.)
● When inputting data from programmable I/O ports set to input mode
➀ The pin which is set to input mode enters the floating state.
➁ By reading the corresponding bit of the port register, the data which is input from the pin can be
read out.
By writing data to the port register of a programmable I/O port set to input mode, the data is only
written into the port latch and is not output to externals. The pin retains floating.
3–4
7751 Group User’s Manual
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi register (i = 0 to 8)
(Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216)
Bit
Bit name
Functions
At reset
RW
Data is input/output to/from a pin by
reading/writing from/to the corresponding bit.
Undefined
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
Port Pi0
1
Port Pi1
2
Port Pi2
3
Port Pi3
4
Port Pi4
Undefined
RW
5
Port Pi5
Undefined
RW
6
Port Pi6
Undefined
RW
7
Port Pi7
Undefined
RW
0 : “L” level
1 : “H” level
Note: Bits 7 to 4 of the port P3 register cannot be written and are fixed to “0” at reading.
Fig. 3.1.3 Port Pi (i = 0 to 8) register structure
7751 Group User’s Manual
3–5
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
Figures 3.1.4 and 3.1.5 show the port peripheral circuits.
[Inside dotted-line not included]
Ports P00 to P07, P10 to P17, P20 to P27,
P30 to P33, P43 to P46
[Inside dotted-line included]
Direction register
Data bus
Port latch
Ports P40, P41, P47, P51/TA0 IN, P53/TA1IN,
P55/TA2 IN, P57/TA3 IN, P61/TA4IN,
P62/INT0 to P64/INT2, P65/TB0IN to P67/TB2IN,
P82/RxD0, P86/RxD1
(There is no hysteresis for P8 2/RxD0 and P86/RxD1.)
[Inside dotted-line not included. ]
Ports P42/ 1, P83 /TxD0, P87/TxD1
Direction register
“1”
[Inside dotted-line included. ]
Output
Data bus
Port latch
Ports P50/TA0OUT, P52/TA1OUT, P54/TA2OUT,
P56/TA3OUT, P60/TA4OUT
[ Inside dotted-line not included]
Direction register
Ports P70/AN0 to P76/AN6
[ Inside dotted-line included]
Port P77/AN7/ADTRG
Data bus
Port latch
Analog input
Fig. 3.1.4 Port peripheral circuits (1)
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7751 Group User’s Manual
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
Ports P80/CTS0/RTS0, P81/CLK0,
P84/CTS1/RTS1, P85/CLK1
“1”
“0”
Direction register
Output
Data bus
Port latch
E output pin
Fig. 3.1.5 Port peripheral circuits (2)
7751 Group User’s Manual
3–7
INPUT/OUTPUT PINS
3.2 I/O pins of internal peripheral devices
3.2 I/O pins of internal peripheral devices (P4 2, P5–P8)
P4 2 and P5 to P8 also function as the I/O pins of the internal peripheral devices. Table 3.2.1 lists I/O pins
for the internal peripheral devices.
For their functions, refer to relevant sections of each internal peripheral device. For the clock φ1 output pin,
refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
Table 3.2.1 I/O pins for internal peripheral devices
Port
I/O pins for internal peripheral devices
P4 2
Clock φ 1 output pin
P5
I/O pins of Timer A
P60, P6 1
P6 2 to P6 4
Input pins of external interrupts
P6 5 to P6 7
Input pins of Timer B
P7
P8
Input pins of A-D converter
3–8
I/O pins of Serial I/O
7751 Group User’s Manual
CHAPTER 4
INTERRUPTS
4.1 Overview
4.2 Interrupt sources
4.3 Interrupt control
4.4 Interrupt priority level
4.5 Interrupt priority level detection circuit
4.6 Interrupt priority level detection time
4.7 Sequence from acceptance of interrupt
request to execution of interrupt routine
4.8 Return from interrupt routine
4.9 Multiple interrupts ____
4.10 External interrupts (INTi interrupt)
4.11 Precautions when using interrupts
INTERRUPTS
4.1 Overview
The suspension of the current operation in order to perform another operation owing to a certain factor is
referred to as “Interrupt.” This chapter describes the interrupts.
4.1 Overview
The M37751 has 19 interrupt sources to generate interrupt requests.
Figure 4.1.1 shows the interrupt processing sequence.
When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set
in the interrupt vector table (addresses FFD6 16 to FFFF 16). Set the start address of each interrupt routine
at each interrupt vector address in the interrupt vector table.
Executing routine
Accept interrupt request
ress
add
t
r
sta ne
h to t routi
c
n
p
Bra terru
of in
Interrupt routine
Process interrupt
Suspend processing
Resume processing
Retu
rn to
origin
al ro
utine
Fig. 4.1.1 Interrupt processing sequence
4–2
7751 Group User’s Manual
RTI instruction
INTERRUPTS
4.1 Overview
When an interrupt request is accepted, the contents of the registers listed below immediately preceding the
acceptance of the interrupt request are automatically saved to the stack area in order of registers ➀→➁→➂.
➀ Program bank register (PG)
➁ Program counter (PC L, PC H)
➂ Processor status register (PSL, PS H)
Figure 4.1.2 shows the state of the stack area just before entering the interrupt routine.
Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer
was executing before the interrupt request was accepted. As the RTI instruction is executed, the register
contents saved in the stack area are restored in order of registers ➂→➁→➀, and a return is made to the
routine executed before the acceptance of interrupt request and processing is resumed from it.
When an interrupt request is accepted and the RTI instruction is executed, the only above registers ➀ to
➂ are automatically saved and restored. When there are any other registers of which contents are necessary
to be kept, use software to save and restore them.
Stack area
Address
[S] – 5
[S] – 4
Processor status register’s low-order byte (PSL)
[S] – 3 Processor status register’s high-order byte (PSH)
[S] – 2
Program counter’s low-order byte (PCL)
[S] – 1
Program counter’s high-order byte (PCH)
[S]✽
Program bank register (PG)
✽ [S] is an initial value that the stack pointer (S) indicates at
accepting an interrupt request. The S’s contents become
[S] – 5 after saving the above registers.
Fig. 4.1.2 State of stack area just before entering interrupt routine
7751 Group User’s Manual
4–3
INTERRUPTS
4.2 Interrupt sources
4.2 Interrupt sources
Table 4.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start
address of each interrupt routine at the vector addresses listed in this table.
Table 4.2.1 Interrupt sources and interrupt vector addresses
Interrupt source
High-order
address
Reset
Zero division
Remarks
Interrupt vector address
Low-order
address
Non-maskable
Non-maskable software interrupt
FFFF16
FFFE 16
FFFD 16
FFFC 16
FFFA 16
FFF816
Non-maskable software interrupt
DBC (Note)
FFFB 16
FFF916
Watchdog timer
FFF716
FFF616
Non-maskable interrupt
INT0
____
FFF516
FFF416
External interrupt due to ____
INT 0 pin input signal
INT1
INT2
FFF316
FFF216
FFF116
FFF016
External interrupt due to ____
INT 1 pin input signal
External interrupt due to INT 2 pin input signal
Timer A0
FFEF 16
FFED16
FFEE 16
FFEC16
Internal interrupt from Timer A0
Timer A1
Timer A2
FFEB 16
FFEA 16
Internal interrupt from Timer A2
Timer A3
FFE916
FFE816
Internal interrupt from Timer A3
Timer A4
Timer B0
FFE716
FFE616
FFE516
FFE416
Internal interrupt from Timer A4
Internal interrupt from Timer B0
Timer B1
FFE216
FFE016
Internal interrupt from Timer B1
Timer B2
FFE316
FFE116
UART0 receive
FFDF 16
FFDE16
Internal interrupt from UART0
UART0 transmit
FFDD16
FFDC 16
UART1 receive
FFDB16
FFDA16
UART1 transmit
FFD9 16
FFD8 16
A-D conversion
FFD7 16
FFD6 16
BRK instruction
____
____
____
Not used usually
Internal interrupt from Timer A1
Internal interrupt from Timer B2
Internal interrupt from UART1
Internal interrupt from A-D converter
____
Note: The DBC interrupt source is used exclusively for debugger control.
4–4
____
7751 Group User’s Manual
INTERRUPTS
4.2 Interrupt sources
Table 4.2.2 lists occurrence factors of internal interrupt request, which occur due to internal operation.
Table 4.2.2 Occurrence factors of internal interrupt request
Interrupt
Interrupt request occurrence factors
Zero division
Occurs when “0” is specified as the divisor for the DIV instruction (Division instruction).
interrupt
(Refer to “7751 Series Software Manual.”)
BRK instruction
Occurs when the BRK instruction is executed.
interrupt
Watchdog timer
(Refer to “7751 Series Software Manual.”)
Occurs when the most significant bit of the watchdog timer becomes “0.”
interrupt
(Refer to “Chapter 9. WATCHDOG TIMER.”)
Timer Ai interrupt
Differs according to the timer Ai’s operating modes.
(i = 0 to 4)
(Refer to “Chapter 5. TIMER A.”)
Timer Bi interrupt
Differs according to the timer Bi’s operating modes.
(i = 0 to 2)
UARTi receive
(Refer to “Chapter 6. TIMER B.”)
Occurs at serial data reception. (Refer to “Chapter 7. SERIAL I/O.”)
interrupt (i = 0, 1)
UARTi transmit
Occurs at serial data transmission. (Refer to “Chapter 7. SERIAL I/O.”)
interrupt (i = 0, 1)
A-D conversion
Occurs when A-D conversion is completed. (Refer to “Chapter 8. A-D CONVERTER.”)
interrupt
7751 Group User’s Manual
4–5
INTERRUPTS
4.3 Interrupt control
4.3 Interrupt control
The enabling and disabling of maskable interrupts are controlled by the following :
•Interrupt request bit
•Interrupt priority level select bits
•Processor interrupt priority level (IPL)
•Interrupt disable flag (I)
The interrupt disable flag (I) and the processor interrupt priority level (IPL) are assigned to the processor
status register (PS). The interrupt request bit and the interrupt priority level select bits are assigned to the
interrupt control register of each interrupt.
Figure 4.3.1 shows the memory assignment of the interrupt control registers, and Figure 4.3.2 shows their
structure.
●Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software.
●Non-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts):
An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their
interrupt control registers and are independent of the interrupt disable flag (I).
Address
7016
A-D conversion interrupt control register
7116
UART0 transmit interrupt control register
7216
UART0 receive interrupt control register
7316
UART1 transmit interrupt control register
7416
UART1 receive interrupt control register
7516
Timer A0 interrupt control register
7616
Timer A1 interrupt control register
7716
Timer A2 interrupt control register
7816
Timer A3 interrupt control register
7916
Timer A4 interrupt control register
7A16
Timer B0 interrupt control register
7B16
Timer B1 interrupt control register
7C16
Timer B2 interrupt control register
7D16
INT0 interrupt control register
7E16
INT1 interrupt control register
7F16
INT2 interrupt control register
Fig. 4.3.1 Memory assignment of interrupt control registers
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7751 Group User’s Manual
INTERRUPTS
4.3 Interrupt control
b7
b6
b5
b4
b3
b2
b1
b0
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 7016 to 7C16)
Bit
0
Interrupt priority level select bits
1
2
3
Functions
Bit name
Interrupt request bit
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt request
1 : Interrupt request
0
RW
Undefined
–
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
b2 b1 b0
7 to 4 Nothing is assigned.
b7
b6
b5
b4
b3
b2
b1
b0
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit
0
Functions
Bit name
Interrupt priority level select bits
1
2
b2 b1 b0
3
Interrupt request bit (Note)
0 : No interrupt request
1 : Interrupt request
0
RW
4
Polarity select bit
0 : Set the interrupt request bit at
“H” level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
“L” level for level sense and at
rising edge for edge sense.
0
RW
5
Level sense/Edge sense select
bit
0 : Edge sense
1 : Level sense
0
RW
Undefined
–
7, 6
Nothing is assigned.
Note: The INT0 to INT2 interrupt request bits are invalid when selecting the level sense.
Fig. 4.3.2 Structure of interrupt control register
7751 Group User’s Manual
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INTERRUPTS
4.3 Interrupt control
4.3.1 Interrupt disable flag (I)
All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts
are disabled; when the flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1”
at reset, clear the flag to “0” when enabling interrupts.
4.3.2 Interrupt request bit
When an interrupt request occurs, this bit is set to “1.” The bit remains set to “1” until the interrupt request
is accepted, and it is cleared to “0” when the interrupt request is accepted.
This bit ____
also can be set to “0” or “1” by software.
____
For the INT i interrupt request bit (i = 0 to 2), when using the INT i interrupt with level sense, the bit is
ignored.
4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL)
The interrupt priority level select bits are used to determine the priority level of each interrupt. Use the SEB
or CLB instruction to set these bits.
When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority
level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition.
Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0.
Each interrupt priority level > Processor interrupt priority level (IPL)
Table 4.3.1 lists the setting of interrupt priority level, and Table 4.3.2 lists the interrupt enabled level
corresponding to IPL contents.
All the interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor
interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt
requests are accepted only when the following conditions are satisfied.
•Interrupt disable flag (I) = “0”
•Interrupt request bit = “1”
•Interrupt priority level > Processor interrupt priority level (IPL)
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INTERRUPTS
4.3 Interrupt control
Table 4.3.1 Setting of interrupt priority level
Interrupt priority level select bits
b1
b0
b2
0
0
0
Interrupt priority level
Level 0 (Interrupt disabled)
0
0
1
Level 1
0
1
0
0
1
1
Level 2
Level 3
1
1
0
0
Level 4
0
1
Level 5
1
1
0
Level 6
1
1
1
Level 7
Priority
—
Low
High
Table 4.3.2 Interrupt enabled level corresponding to IPL contents
IPL2
0
IPL1
IPL0
0
0
Enabled interrupt priority level
Enable level 1 and above interrupts.
0
0
1
Enable level 2 and above interrupts.
0
1
0
Enable level 3 and above interrupts.
0
1
1
Enable level 4 and above interrupts.
1
0
0
Enable level 5 and above interrupts.
1
1
0
1
1
0
Enable level 6 and level 7 interrupts.
Enable only level 7 interrupt.
1
1
1
Disable all maskable interrupts.
IPL 0: Bit 8 in processor status register (PS)
IPL 1: Bit 9 in processor status register (PS)
IPL 2: Bit 10 in processor status register (PS)
7751 Group User’s Manual
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INTERRUPTS
4.4 Interrupt priority level
4.4 Interrupt priority level
When two or more interrupt requests are detected at the same sampling timing, at which whether an
interrupt request exists or not is checked, in the case of the interrupt disable flag (I) = “0” (interrupts
enabled); they are accepted in order of priority levels, with the highest priority interrupt request accepted
first.
Among a total of 19 interrupt sources, the user can set the desired priority levels for 16 interrupt sources
except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt.
Use the interrupt priority level select bits to set their priority levels. Additionally, the reset, which is handled
as one that has the highest priority of all interrupts, and the watchdog timer interrupt have their priority levels
set by hardware. Figure 4.4.1 shows the interrupt priority levels set by hardware.
Note that software interrupts are not affected by interrupt priority levels. Whenever the instruction is executed,
a branch is certain to be made to the interrupt routine.
Reset
Watchdog
timer
Priority levels determined by hardware
••••••••••••••••••
16 interrupt sources except software interrupts
and watchdog timer interrupt
The user can set the desired priority levels inside of the dotted line.
High
Priority level
Fig. 4.4.1 Interrupt priority levels set by hardware
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7751 Group User’s Manual
Low
INTERRUPTS
4.5 Interrupt priority level detection circuit
4.5 Interrupt priority level detection circuit
The interrupt priority level detection circuit selects the interrupt having the highest priority level when more
than one interrupt request occurs at the same sampling timing. Figure 4.5.1 shows the interrupt priority level
detection circuit.
Level 0 (initial value)
Interrupt priority level
Interrupt priority level
A-D conversion
Timer A4
UART1 transmit
Timer A3
UART1 receive
Timer A2
UART0 transmit
Timer A1
UART0 receive
Timer A0
Timer B2
INT2
Timer B1
INT1
Timer B0
INT0
The highest priority level interrupt
IPL
Processor interrupt priority level
Interrupt
disable flag (I)
Watchdog timer interrupt
Accepting of interrupt request
Reset
Fig. 4.5.1 Interrupt priority level detection circuit
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INTERRUPTS
4.5 Interrupt priority level detection circuit
The following explains the operation of the interrupt priority detection circuit using Figure 4.5.2.
The interrupt priority level of a requested interrupt (Y in Figure 4.5.2) is compared with the resultant priority
level sent from the preceding comparator (X in Figure 4.5.2); whichever interrupt of the higher priority level
is sent to the next comparator (Z in Figure 4.5.2). (Initial comparison value is “0.”) For interrupts for which
no interrupt request occurs, the priority level sent from the preceding comparator is forwarded to the next
comparator. When the two priority levels are found the same by comparison, the priority level sent from the
preceding comparator is forwarded to the next comparator. Accordingly, when the same priority level is set
by software, the interrupt requests are subject to the following relation about priority:
A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive
> Timer
B2____
____
____
> Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT 2 > INT1 > INT 0
Among the multiple interrupt requests sampled at the same time, one that has the highest priority level is
detectedd by the above comparison.
Then this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When
this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable
flag (I) is “0,” the interrupt request is accepted. A interrupt request which is not accepted here is retained
until it is accepted or its interrupt request bit is cleared to “0” by software.
The interrupt priority is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch
cycle. However, when an op-code fetch cycle is generated during detection of an interrupt priority, new
detection of that does not start. (Refer to Figure 4.6.1.) Since the state of the interrupt request bit and
interrupt priority levels are latched during detection of interrupt priority, even if the bit state and priority
levels change, the detection is performed on the previous state before it has changed.
X
Y
Time
Interrupt source Y
Comparator
(Priority level
comparison)
X : Resultant priority level sent from the preceding
comparator (Highest priority at this point)
Y : Priority level of interrupt source Y
Z : Highest priority at this point
Z
●When X
Y then Z = X
●When X < Y then Z = Y
Fig. 4.5.2 Interrupt priority level detection model
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INTERRUPTS
4.6 Interrupt priority level detection time
4.6 Interrupt priority level detection time
After sampling had started, an interrupt priority level detection time has elapses before an interrupt request
is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the
interrupt priority level detection time.
As the interrupt priority level detection time, normally select “2 cycles of internal clock φ .”
(1) Interrupt priority detection time select bits
b7
b6
0
b5
b4
b3
b2
b1
b0
0
Processor mode register 0 (Address 5E16
Processor mode bits
Fix to “0.”
Software reset bit
b5, b4
Interrupt priority detection time select bits
00
7 cycles of
[(a) shown below]
01
4 cycles of
[(b) shown below]
10
2 cycles of
[(c) shown below]
11
Not selected
Fix to “0.”
Clock φ 1 output select bit
(2) Interrupt priority level detection time
φ
Op code fetch cycle
(Note)
Sampling pulse
(a) 7 cycles
Interrupt priority level
(b) 4 cycles
detection time
(c) 2 cycles
Note: Pulse exists when “2 cycles of φ ” is selected.
Fig. 4.6.1 Interrupt priority level detection time
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INTERRUPTS
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
The sequence from the acceptance of interrupt request to the execution of the interrupt routine is described
below.
When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt
is cleared to “0,” and then the interrupt processing starts from the next cycle of completion of the instruction
which is being executed at accepting the interrupt request. Figure 4.7.1 shows the sequence from acceptance
of interrupt request to execution of interrupt routine.
After execution of an instruction at accepting the interrupt request is completed, an INTACK (Interrupt
Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine
allocated in addresses 016 to FFFF16.
The INTACK sequence is automatically performed in the following order.
➀ The contents of the program bank register (PG) just before performing the INTACK sequence are stored
to stack.
➁ The contents of the program counter (PC) just before performing the INTACK sequence are stored to
stack.
➂ The contents of the processor status register (PS) just before performing the INTACK sequence is stored
to stack.
➃ The interrupt disable flag (I) is set to “1.”
➄ The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL).
➅ The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt
vector address are set into the program counter (PC).
Performing the INTACK sequence requires at least 15 cycles of internal clock φ . Figure 4.7.2 shows the
INTACK sequence timing.
Execution is started beginning with an instruction at the start address of the interrupt routine after completing
the INTACK sequence.
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INTERRUPTS
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
Interrupt request is accepted.
Interrupt request occurs.
@
@
Instruction Instruction
1
2
➀
INTACK sequence
➁
Time
Instructions in interrupt routine
➂
Interrupt response time
@ : Duration for detecting interrupt priority
level
➀ Time from the occurrence of an interrupt request until the completion of executing an instruction
which is being executed at the occurrence.
➁ Time from the instruction next to ➀ (Note) until the completion of executing an instruction which is
being done at the end of priority detection
Note : At this time, interrupt priority detection starts.
➂ Time required to execute the INTACK sequence (15 cycles of φ at minimum)
Fig. 4.7.1 Sequence from acceptance of interrupt request to execution of interrupt routine
●When 2 access in low-speed running and stack pointer(S)’s content is even
φ
φ CPU
AH(CPU)
Undefined
00
00
00
00
00
00
00
00
AMAL(CPU)
Undefined
0000
0000
0000
[S]
[S]–2
[S]–4
[S]–4
FFXX16
DATAH(CPU)
Undefined
IPL
DATAL(CPU)
Undefined
Vector address
(Low order)
PG
00
ADM‘ ADL
PCH
PSH
ADM
Next instruction
PCL
PSL
ADL
Next instruction
E
INTACK sequence
[S]
: Contents of stack pointer (S)
FFXX16 : Vector address
Fig. 4.7.2 INTACK sequence timing (at minimum)
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INTERRUPTS
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
4.7.1 Change in IPL at acceptance of interrupt request
When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the
interrupt priority level of the accepted interrupt. This results in easy control of multiple interrupts. (Refer
to section “4.9 Multiple interrupts.”)
When at reset or the watchdog timer or the software interrupt is accepted, the value shown in Table 4.7.1
is set in the IPL.
Table 4.7.1 Change in IPL at interrupt request acceptance
Interrupt source
Change in IPL
Reset
Level 0 (“000 2”) is set.
Watchdog timer
Level 7 (“111 2”) is set.
Zero division
No change
BRK instruction
Other interrupts
No change
4–16
Interrupt priority level of the accepted interrupt request is set.
7751 Group User’s Manual
INTERRUPTS
4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
4.7.2 Storing registers
The register storing operation performed during INTACK sequence depends on whether the contents of the
stack pointer (S) at accepting interrupt request are even or odd.
When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the
processor status register (PS) are stored as a 16-bit unit simultaneously at each other. When the contents
of the stack pointer (S) are odd, they are stored with twice by an 8-bit unit for each. Figure 4.7.3 shows
the register storing operation.
In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and
processor status register (PS) are stored to the stack area. The other necessary registers must be stored
by software at the beginning of the interrupt routine.
Using the PSH instruction can store all CPU registers except the stack pointer (S).
(1) Content of stack pointer (S) is even
Address
[S] – 5 (odd)
Storing order
[S] – 4 (even)
Low-order byte of processor status register (PSL)
[S] – 3 (odd)
High-order byte of processor status register (PSH)
[S] – 2 (even)
Low-order byte of program counter (PCL)
[S] – 1 (odd)
High-order byte of program counter (PCH)
[S] (even)
➂ Stores 16 bits at a time.
➁ Stores 16 bits at a time.
➀
Program bank register (PG)
Storing is completed with 3 times.
(2) Content of stack pointer (S) is odd
Address
Storing order
[S] – 5 (even)
[S] – 4 (odd)
Low-order byte of processor status register (PSL)
➃
[S] – 3 (even)
High-order byte of processor status register (PSH)
➄
[S] – 2 (odd)
Low-order byte of program counter (PCL)
➁
[S] – 1 (even)
High-order byte of program counter (PCH)
➂
Program bank register (PG)
➀
[S] (odd)
Stores by each 8 bits.
Storing is completed with 5 times.
✽ [S] is an initial value that the stack pointer (S) indicates at accepting an interrupt
request. The S’s contents become [S] – 5 after storing the above registers.
Fig. 4.7.3 Register storing operation
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INTERRUPTS
4.8 Return from interrupt routine 4.9 Multiple interrupts
4.8 Return from interrupt routine
When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank
register (PG), program counter (PC), and processor status register (PS) immediately before performing the
INTACK sequence, which were saved to the stack area, are automatically restored, and control returns to
the routine executed before the acceptance of interrupt request and processing is resumed from it left off.
For any register that is saved by software in the interrupt routine, restore it with the same data length and
same register length as it was saved by using the PUL instruction and others before executing the RTI
instruction.
4.9 Multiple interrupts
When a branch is made to the interrupt routine, the microcomputer becomes the following situation:
•Interrupt disable flag (I) = “1” (interrupts disabled)
•Interrupt request bit of the accepted interrupt = “0”
•Processor interrupt priority level (IPL) = interrupt priority level of the accepted interrupt
Accordingly, as long as the IPL remains unchanged, the microcomputer can accept the interrupt request that
has higher priority than the interrupt request being executed now by clearing the interrupt disable flag (I)
to “0” in the interrupt routine. This is multiple interrupts.
Figure 4.9.1 shows the multiple interrupt mechanism.
The interrupt requests that have not been accepted owing to their low priority levels are retained. When the
RTI instruction is executed, the interrupt priority level of the routine that the microcomputer was executing
before accepting the interrupt request is restored to the IPL. Therefore, one of the interrupt requests being
retained is accepted when the following condition is satisfied at next detection of interrupt priority level:
Interrupt priority level of interrupt request being retained > Processor interrupt priority level (IPL)
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INTERRUPTS
4.9 Multiple interrupts
Nesting
Request
Time
Reset
Main routine
I=1
Interrupt 1
IPL = 0
I=0
Interrupt priority level=3
Interrupt 1
I=1
Interrupt 2
IPL = 3
Multiple interrupt
I=0
Interrupt priority level=5
Interrupt 2
I=1
IPL = 5
Interrupt 3
RTI
Interrupt priority level=2
I=0
IPL = 3
Interrupt 3
RTI
I=0
This request cannot be accepted
because its priority level is lower
than interrupt 1’s.
IPL = 0
The instruction of main routine is not
executed then.
Interrupt 3
I=1
IPL = 2
RTI
I=0
IPL = 0
I : Interrupt disable flag
IPL : processor interrupt priority level
: They are set automatically.
: Set by software.
Fig. 4.9.1 Multiple interrupt mechanism
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
___
4.10 External interrupts (INTi interrupt)
___
An external interrupt request occurs by input signals to the INT i (i = 0 to 2) pin. The occurrence factor of
interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits
___
5 and 4 at addresses 7D 16 to 7F 16) shown in Figure 4.10.1. Table 4.10.1 lists the occurrence factor of INT i
interrupt request. ___
___
When using P6 2/INT 0 to P6 4/INT 2 pins as input pins of external interrupts, set the corresponding bits at
register) to “0.” (Refer to Figure 4.10.2.)
address 1016 (port P6 direction
___
The signals input to the INT i pin require “H”___
or “L” level___
width of 250 ns or more independent of the f(XIN).
Additionally, even when using the pins P62/INT 0 to P64/INT2 as the input pins of external interrupt, the user
can obtain the pin’s state by reading bits 2 to 4 at address E 16 (port P6 register).
Note: When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request,
make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising
or “H” level as that, make sure that the input signal is held “H” for 250 ns or more.
___
Table 4.10.1 Occurrence factor of INT i interrupt
request
___
INT i interrupt request occurrence factor
b5
b4
___
0
0
Interrupt request occurs at falling of the signal input to the ___
INT i pin (edge sense).
0
1
Interrupt request occurs at rising of the signal input to the INT i pin (edge sense).
___
1
0
Interrupt request occurs while the INT
i pin level is “H” (level sense).
___
1
1
Interrupt request occurs while the INTi pin level is “L” (level sense).
___
___
The INTi interrupt
request occurs by___
always detecting the INT i pin’s state. Accordingly, when the user does
___
not use the INT i interrupt, set the INT i interrupt’s priority level to level 0.
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
b7
b6
b5
b4
b3
b2
b1
b0
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit
Bit name
0
Interrupt priority level select bits
1
2
Functions
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
b2 b1 b0
3
Interrupt request bit (Note)
0 : No interrupt request
1 : Interrupt request
0
RW
4
Polarity select bit
0 : Set the interrupt request bit at
“H” level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
“L” level for level sense and at
rising edge for edge sense.
0
RW
5
Level sense/Edge sense select bit
0 : Edge sense
1 : Level sense
0
RW
Undefined
–
7, 6
Nothing is assigned.
Note: The INT0 to INT2 interrupt request bits are invalid when selecting the level sense.
___
Fig. 4.10.1 Structure of INT i (i=0 to 2) interrupt control register
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
b7
b6
b5
b4
b3
b2
b1
b0
Port P6 direction register (Address 1016)
Bit
Corresponding pin
0
TA4OUT pin
1
TA4IN pin
Functions
At reset
RW
0
RW
0
RW
0
RW
0
RW
0 : Input mode
1 : Output mode
When using pins as external interrupt
input pins,set the corresponding bits
to “0.”
2
INT0 pin
3
INT1 pin
4
INT2 pin
0
RW
5
TB0IN pin
0
RW
6
TB1IN pin
0
RW
7
TB2IN pin
0
RW
: Bits 0, 1 and bits 5 to 7 are not used for external interrupts.
Fig. 4.10.2 Relationship between port P6 direction register and input pins of external interrupt
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
___
4.10.1 Function of INT i interrupt request bit
(1) Selecting edge sense mode
The interrupt request bit has the same function as that of internal interrupts. That is, when an
interrupt request occurs, the interrupt request bit is set to “1.” The bit remains set to “1” until the
interrupt request is accepted; it is cleared to “0” when the interrupt request is accepted. By software,
this bit also can be set to “0” in order to clear the interrupt request or “1” in order to generate the
interrupt request.
(2) Selecting
level sense mode
___
The INT i interrupt request bit becomes ignored.
___
In this case,
the interrupt request occurs continuously while the level of the INT i pin is ___
valid level ✽1.
___
✽2
When the INTi pin level changes from the valid level to the invalid level before the INT i interrupt
request is accepted, this interrupt request is not retained. (Refer to Figure 4.10.4.)
Valid level✽1: This means the level which is selected by the polarity select bit (bit 4 at addresses 7D 16
to 7F16).
Invalid level ✽2: This means the reversed level of a valid level.
Data bus
INTi pin
Edge detection
circuit
Interrupt request bit
“0”
Level sense/Edge sense
select bit
Interrupt request
“1”
___
Fig. 4.10.3 Circuit of INTi Interrupt
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
Interrupt request is accepted.
When the INTi pin’s level changes to an
invalid level before an interrupt request is
accepted, the interrupt request is not
retained.
Return to main routine.
Valid
INTi pin level
Invalid
Main routine
Main routine
First interrupt routine
Second interrupt
routine
Third interrupt
routine
___
Fig. 4.10.4 Occurrence of INT i interrupt request in level sense mode
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
___
4.10.2 Switch of occurrence factor
of INTi interrupt request
___
To
switch
the
occurrence
factor
of
INT
i interrupt request from the level sense to the edge sense, set the
___
INT
i
interrupt
control
register
in
the
sequence
shown in Figure 4.10.5 (1). To change the polarity, set the
___
INTi interrupt control register in the sequence shown in Figure 4.10.5 (2).
(1) Switching from level sense to edge sense
(2) Changing polarity
Set the interrupt priority level to level 0
( Disable INTi interrupt )
Set the interrupt priority level to level 0
( Disable INTi interrupt )
Clear level sense/edge sense select bit to “0”
( Select edge sense )
Set polarity select bit
Clear interrupt request bit to “0”
Clear interrupt request bit to “0”
Set the interrupt priority level to level 1–7
(Enable acceptance of INTi interrupt request)
Set the interrupt priority level to level 1–7
(Enable acceptance of INTi interrupt request)
Note: Follow the above procedure each. Do not perform 2 or more setting at the same
time, with 1 instruction.
___
Fig. 4.10.5 Switching flow of occurrence factor of INT i interrupt request
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INTERRUPTS
4.11 Precautions when using interrupts
4.11 Precautions when using interrupts
To change the interrupt priority level select bits (bits 0 to 2 at addresses 7016 to 7F 16), 2 to 7 cycles of φ
are required after executing an write-instruction until completion of the interrupt priority level’s change.
Accordingly, it is necessary to reserve enough time by software when changing the interrupt priority level
of which interrupt source is the same within a very short execution time consisting of a few instructions.
Figure 4.11.1 shows a program example to reserve time required for changing interrupt priority level. The
time for change depends on the interrupt priority detection timer select bits (bits 4 and 5 at address 5E 16).
Table 4.11.1 lists the relation between the number of instructions to be inserted with program example of
Figure 4.11.1 and the interrupt priority detection time select bits.
:
LDM.B #0XH, 007XH
NOP
NOP
NOP
LDM.B #0XH, 007XH
:
; Write to interrupt priority level select bits
; Insert NOP instruction (Note)
;
;
; Write to interrupt priority level select bits
Note: All instructions (other than instructions for writing to address 7X16) which have the
same cycles as NOP instruction can also be inserted. Confirm the number of
instructions to be inserted by Table 4.11.1.
Fig. 4.11.1 Program example to reserve time required for changing interrupt priority level
Table 4.11.1 Relation between number of instructions to be inserted with program example of Figure
4.11.1 and interrupt priority detection time select bits
Interrupt priority detection time select bits (Note)
b5
b4
0
0
0
1
1
1
0
1
Note: We recommend [b5 = “1”, b4 = “0”].
4–26
Interrupt priority level
detection time
Number of inserted
instructions
7 cycles of φ
NOP instruction 4 or more
4 cycles of φ
NOP instruction 2 or more
2 cycles of φ
Do not select.
NOP instruction 1 or more
7751 Group User’s Manual
CHAPTER 5
TIMER A
5.1
5.2
5.3
5.4
5.5
5.6
Overview
Block description
Timer mode
Event counter mode
One-shot pulse mode
Pulse width modulation (PWM) mode
TIMER A
5.1 Overview
Timer A is used primarily for output to externals. It consists of five counters, timers A0 to A4, each equipped
with a 16-bit reload function. Timers A0 to A4 operate independently of one another.
5.1 Overview
Timer Ai (i = 0 to 4) has four operating modes listed below. Except for the event counter mode, Timers A0
to A4 all have the same functions.
● Timer mode
The timer counts an internally generated count source. Following functions can be used in this mode:
•Gate function
•Pulse output function
● Event counter mode
The timer counts an external signal. Following functions can be used in this mode:
•Pulse output function
•Two-phase pulse signal processing function (Timers A2, A3, and A4)
● One-shot pulse mode
The timer outputs a pulse which has an arbitrary width once.
● Pulse width modulation (PWM) mode
Timer outputs pulses which have an arbitrary width in succession. The timer functions as which pulse
width modulator as follows:
•16-bit pulse width modulator
•8-bit pulse width modulator
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TIMER A
5.2 Block description
5.2 Block description
Figure 5.2.1 shows the block diagram of Timer A. Explanation of relevant registers to Timer A is described
below.
f 2/f 4
f 16/f 32
f 64/f 128
f 512/f 1024
Count source
select bits
Data bus (odd)
Data bus (even)
(Low-order 8 bits)
Timer mode
One-shot pulse mode
PWM mode
Timer Ai reload register (16)
Timer mode
(Gate function)
TAi IN
Polarity
switching
(High-order 8 bits)
Timer Ai counter (16)
Event counter mode
Count start bit
Trigger
Timer Ai
interrupt
request bit
Up-count/down-count
switching
(Always down-count except
for event counter mode)
Down-count
Up-down bit
Pulse output
function select bit
TAi OUT
Toggle
F.F.
Fig. 5.2.1 Block diagram of Timer A
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TIMER A
5.2 Block description
5.2.1 Counter and reload register (timer Ai register)
Each of timer Ai counter and reload register consists of 16 bits.
The counter down-counts each time the count source is input. In the event counter mode, it can also
function as an up-counter.
The reload register is used to store the initial value of the counter. When the counter underflows or
overflows, the reload register’s contents are reloaded into the counter.
Values are set to the counter and reload register by writing a value to the timer Ai register. Table 5.2.1
lists the memory assignment of the timer Ai register.
The value written into the timer Ai register when counting is not in progress is set to the counter and reload
register. The value written into the timer Ai register when counting is in progress is set to only the reload
register. In this case, the reload register’s updated contents are transferred to the counter at the next
reload time. The value got when reading out the timer Ai register varies according to the operating mode.
Table 5.2.2 lists reading and writing from and to the timer Ai register.
Table 5.2.1 Memory assignment of timer Ai register
Timer Ai register
Timer A0 register
High-order byte
Address 47 16
Low-order byte
Address 4616
Timer A1 register
Address 49 16
Address 4816
Timer A2 register
Address 4B 16
Address 4A 16
Timer A3 register
Timer A4 register
Address 4D16
Address 4F 16
Address 4C16
Address 4E 16
Note: When reset, the contents of the timer Ai
register are undefined.
Table 5.2.2 Reading and writing from and to timer Ai register
Operating mode
Timer mode
Event counter mode
One-shot pulse mode
Pulse width modulation (PWM) mode
Read
Counter value is read out.
(Note 1)
Undefined value is read out.
Write
<During counting>
Written to only reload register.
<When not counting>
Written to both counter and
reload register.
Notes 1: Also refer to “[Precautions when operating in timer mode]” and “[Precautions when operating in event counter mode].”
2: When reading and writing to/from the timer Ai register, perform them in a unit of 16 bits.
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TIMER A
5.2 Block description
5.2.2 Count start register
This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure
5.2.2 shows the structure of the count start register.
b7
b6
b5
b4
b3
b2
b1
b0
Count start register (Address 40 16)
Bit
Bit name
Functions
0 : Stop counting
1 : Start counting
At reset
RW
0
RW
0
Timer A0 count start bit
1
Timer A1 count start bit
0
RW
2
Timer A2 count start bit
0
RW
3
Timer A3 count start bit
0
RW
4
Timer A4 count start bit
0
RW
5
Timer B0 count start bit
0
RW
6
Timer B1 count start bit
0
RW
7
Timer B2 count start bit
0
RW
: Bits 7 to 5 are not used for Timer A.
Fig. 5.2.2 Structure of count start register
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TIMER A
5.2 Block description
5.2.3 Timer Ai mode register
Figure 5.2.3 shows the structure of the timer Ai mode register. Operating mode select bits are used to
select the operating mode of timer Ai. Bits 2 to 7 have different functions according to the operating mode.
These bits are described in the paragraph of each operating mode.
b7
b6
b5
b4
b3
b2
b1
b0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
Bit name
Functions
At reset
RW
0
RW
0
RW
0
RW
3
0
RW
4
0
RW
5
0
RW
6
0
RW
7
0
RW
0
Operating mode select bits
1
2
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot pulse mode
1 1 : Pulse width modulation (PWM) mode
These bits have different functions according to the operating mode.
Fig. 5.2.3 Structure of timer Ai mode register
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TIMER A
5.2 Block description
5.2.4 Timer Ai interrupt control register
Figure 5.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer
to “Chapter 4. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
Timer Ai interrupt control registers (i = 0 to 4) (Addresses 7516 to 7916)
Bit
0
Functions
Bit name
Interrupt priority level select bits
1
2
3
Interrupt request bit
7 to 4
Nothing is assigned.
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt request
1 : Interrupt request
0
RW
Undefined
–
b2 b1 b0
Fig. 5.2.4 Structure of timer Ai interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select a timer Ai interrupt’s priority level. When using timer Ai interrupts, select priority
levels 1 to 7. When a timer Ai interrupt request occurs, its priority level is compared with the
processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority
level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To
disable timer Ai interrupts, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when the timer Ai interrupt request occurs. This bit is automatically cleared to
“0” when the timer Ai interrupt request is accepted. This bit can be set to “1” or “0” by software.
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TIMER A
5.2 Block description
5.2.5 Port P5 and port P6 direction registers
The I/O pins of Timers A0 to A3 are shared with port P5, and the I/O pins of Timer A4 are shared with
port P6. When using these pins as Timer Ai’s input pins, set the corresponding bits of the port P5 and port
P6 direction registers to “0” to set these ports for the input mode. When used as Timer Ai’s output pins,
these pins are forcibly set to output pins of Timer Ai regardless of the direction registers’s contents. Figure
5.2.5 shows the relationship between the port P5 and port P6 direction registers and the Timer Ai’s I/O
pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P5 direction register (Address D16)
Bit
b7
b6
b5
b4
b3
b2
b1
Corresponding pin name
0
TA0 OUT pin
1
TA0 IN pin
Functions
0: Input mode
1: Output mode
When using these pins as
Timer Ai’s input pins, set the
corresponding bits to “0.”
At reset
RW
0
RW
0
RW
0
RW
2
TA1 OUT pin
3
TA1 IN pin
0
RW
4
TA2 OUT pin
0
RW
5
TA2 IN pin
0
RW
6
TA3 OUT pin
0
RW
7
TA3 IN pin
0
RW
At reset
RW
0
RW
0
RW
0
RW
b0
Port P6 direction register (Address 10 16)
Bit
Corresponding pin name
0
TA4 OUT pin
1
TA4 IN pin
Functions
0: Input mode
1: Output mode
When using these pins as
Timer Ai’s input pins, set the
corresponding bits to “0.”
2
INT0 pin
3
INT1 pin
0
RW
4
INT2 pin
0
RW
5
TB0 IN pin
0
RW
6
TB1 IN pin
0
RW
7
TB2 IN pin
0
RW
: Bits 7 to 2 are not used for Timer A.
Fig. 5.2.5 Relationship between port P5 and port P6 direction registers and Timer Ai’s I/O pins
5–8
7751 Group User’s Manual
TIMER A
5.3 Timer mode
5.3 Timer mode
In this mode, the timer counts an internally generated count source. (Refer to Table 5.3.1.) Figure 5.3.1
shows the structures of the timer Ai mode register and timer Ai register in the timer mode.
Table 5.3.1 Specifications of timer mode
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request occurrence timing
TAiIN pin function
TAiOUT pin function
Read from timer Ai register
Write to timer Ai register
Specifications
f 2/f4 , f16/f 32, f64 /f128, or f 512/f 1024
• Down-count
• When the counter underflows, reload register’s contents are reloaded
and counting continues.
When count start bit is set to “1.”
When count start bit is cleared to “0.”
When the counter underflows.
Programmable I/O port or gate input
Programmable I/O port or pulse output
Counter value can be read out.
● While counting is stopped
When a value is written to timer Ai register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to timer Ai register, it is written to only
reload register. (Transferred to counter at next reload timing.)
7751 Group User’s Manual
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TIMER A
5.3 Timer mode
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Timer Ai mode register (i = 0 to 4) (Addresses 56 16 to 5A 16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 0 : Timer mode
1
RW
0
RW
0 : No pulse output
(TAiOUT pin functions as a programmable
I/O port.)
1 : Pulse output
(TAiOUT pin functions as a pulse output
pin.)
0
RW
3
Gate function select bits
b4 b3
0
RW
0
RW
0
RW
0
RW
0
RW
At reset
RW
Undefined
RW
0 0 : No gate function
0 1 : (TAiIN pin functions as a programmable I/O port.)
1 0 : Gate function
(Counter counts only while TAi IN
pin’s input signal is “L” level.)
1 1 : Gate function
(Counter counts only while TAi IN
pin’s input signal is “H” level.)
5
Fix this bit to “0” in the timer mode.
6
Count source select bits
b7 b6
0 0 : f 2/f4
0 1 : f 16/f32
1 0 : f 64/f128
1 1 : f 512/f1024
Timer A0 register (Addresses 4716, 46 16)
Timer A1 register (Addresses 4916, 48 16)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Bit
Functions
15 to 0 These bits can be set to “0000 16” to “FFFF 16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
Fig. 5.3.1 Structures of timer Ai mode register and timer Ai register in timer mode
5–10
0
Pulse output function select bit
7
(b8)
b0 b7
RW
2
4
(b15)
b7
At reset
7751 Group User’s Manual
TIMER A
5.3 Timer mode
5.3.1 Setting for timer mode
Figures 5.3.2 and 5.3.3 show an initial setting example for registers relevant to the timer mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4.
INTERRUPTS.”
Selecting timer mode and each function
b7
b0
0
0 0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Selection of timer mode
Pulse output function select bit
0: No pulse output.
1: Pulses output.
Gate function select bits
b4 b3
0 0:
No gate function
0 1:
1 0: Gate function (Counter counts only while TAiIN pin’s input signal is “L” level.)
1 1: Gate function (Counter counts only while TAiIN pin’s input signal is “H” level.)
Count source select bits
b7 b6
0 0: f2/f4
0 1: f16/f32
1 0: f64/f128
1 1: f512/f1024
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Can be set to “000016” to “FFFF16” (n).
Note : Counter divides the count source frequency by n + 1.
Continue to Figure 5.3.3 on next page.
Fig. 5.3.2 Initial setting example for registers relevant to timer mode (1)
7751 Group User’s Manual
5–11
TIMER A
5.3 Timer mode
From preceding Figure 5.3.2 .
Setting interrupt priority level
b7
b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 75 16 to 79 16)
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
Setting port P5 and port P6 direction registers
b7
b0
Port P5 direction register (Address D16)
TA0IN pin
TA1IN pin
TA2IN pin
TA3IN pin
b7
b0
Port P6 direction register (Address 1016)
TA4IN pin
When gate function is selected, set the bit corresponding to the TAi IN pin to “0.”
Setting count start bit to “1.”
b7
b0
Count start register (Address 40 16)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Count starts
Fig. 5.3.3 Initial setting example for registers relevant to timer mode (2)
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7751 Group User’s Manual
TIMER A
5.3 Timer mode
5.3.2 Count source
In the timer mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count
source. Table 5.3.2 lists the count source frequency.
Table 5.3.2 Count source frequency
Count source
select bits
f(X IN) = 25 MHz
Clock source for peripheral
Clock source for peripheral
devices select bit = “0”
devices select bit = “1”
Count source
Count
source
Frequency
Frequency
f4
f2
12.5 MHz
6.25 MHz
f 32
f 16
1.5625 MHz
781.25 kHz
b7
b6
0
0
0
1
1
0
f 128
1
f 1024
1
195.3125 kHz
f 64
24.4141 kHz
f 512
f(X IN) = 40 MHz
Clock source for peripheral
devices select bit = “0”
Count source
Frequency
f4
10 MHz
f 32
1.25 MHz
390.625 kHz
f 128
312.5 kHz
48.8281 kHz
f 1024
39.0625 kHz
Clock source for peripheral devices select bit : bit 2 at address 5F 16
7751 Group User’s Manual
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TIMER A
5.3 Timer mode
5.3.3 Operation in timer mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ When the counter underflows, the reload register’s contents are reloaded and counting continues.
➂ The timer Ai interrupt request bit is set to “1” when the counter underflows in ➁. The interrupt request
bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0”
by software.
Figure 5.3.4 shows an example of operation in the timer mode.
n = Reload register’s contents
Counter contents (Hex.)
FFFF16
Starts counting.
1 / fi ✕ (n+1)
Stops counting.
n
Restarts counting.
0000 16
Time
Set to “1” by software.
Count start bit
Cleared to “0” by software.
Set to “1” by software.
“1”
“0”
Timer Ai interrupt “1”
request bit “0”
fi = frequency of count source
(f2/f4, f16/f32, f64/f128 , f512 /f1024 )
Cleared to “0” when interrupt request is
accepted or cleared by software.
Fig. 5.3.4 Example of operation in timer mode (without pulse output and gate functions)
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7751 Group User’s Manual
TIMER A
5.3 Timer mode
5.3.4 Select function
The following describes the selective gate and pulse output functions.
(1) Gate function
The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5616
to 5A16 ) to “102” or “112.” The gate function makes it possible to start or stop counting depending on
the TAiIN pin’s input signal. Table 5.3.3 lists the count valid levels.
Figure 5.3.5 shows an example of operation selecting the gate function.
When selecting the gate function, set the port P5 and port P6 direction registers’ bits which correspond
to the TAiIN pin for the input mode. Additionally, make sure that the TAiIN pin’s input signal has a pulse
width equal to or more than two cycles of the count source.
Table 5.3.3 Count valid levels
Gate function select bits
b4
b3
1
0
Count valid level (Duration when counter counts)
While TAi IN pin’s input signal is “L” level
1
1
While TAi IN pin’s input signal is “H” level
Note: The counter does not count while the TAi IN pin’s input signal is not at the count valid level.
7751 Group User’s Manual
5–15
TIMER A
5.3 Timer mode
FFFF16
n = Reload register’s contents
➀ Starts counting.
Counter contents (Hex.)
n
➁ Stops counting.
000016
Set to “1” by software.
Time
Count start bit “1”
“0”
TAiIN pin’s
input signal
Count valid
level
Invalid level
Timer Ai interrupt “1”
request bit “0”
➀ The counter counts when the count start bit = “1” and the TAiIN pin’s input signal is at the count valid
level.
➁ The counter stops counting while the TAiIN pin’s input signal is not at the count valid level, and the
counter value is retained.
Fig. 5.3.5 Example of operation selecting gate function
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7751 Group User’s Manual
Cleared to “0” when
interrupt request is
accepted or cleared
by software.
TIMER A
5.3 Timer mode
(2) Pulse output function
The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses
5616 to 5A16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output
pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAiOUT pin
outputs pulses of which polarity is inverted each time the counter underflows.
When the count start bit (address 4016) is “0” (count stopped), the TAiOUT pin outputs “L” level. Figure
5.3.6 shows an example of operation selecting the pulse output function.
n = Reload register’s contents
FFFF16
counter contents (Hex.)
Starts counting.
Starts counting.
n
Restarts
counting.
000016
Time
Set to “1” by software.
Cleared to “0” by software.
Set to “1” by software.
Count start bit “1”
“0”
Pulse output from “H”
TAiout pin “L”
Timer Ai interrupt “1”
request bit “0”
Cleared to “0” when interrupt request is accepted or cleared by software.
Fig. 5.3.6 Example of operation selecting pulse output function
7751 Group User’s Manual
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TIMER A
5.3 Timer mode
[Precautions when operating in timer mode]
By reading the timer Ai register, the counter value can be read out at any timing while counting is in
progress. However, if the timer Ai register is read at the reload timing shown in Figure 5.3.7, the value
“FFFF 16” is read out. When reading the timer Ai register after setting a value to the register while counting
is not in progress and before the counter starts counting, the set value is read out correctly.
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
FFFF n – 1
n = Reload register’s contents
Fig. 5.3.7 Reading timer Ai register
5–18
n–1
7751 Group User’s Manual
Time
TIMER A
5.4 Event counter mode
5.4 Event counter mode
In this mode, the timer counts an external signal. (Refer to Tables 5.4.1 and 5.4.2.) Figure 5.4.1 shows the
structures of the timer Ai mode register and timer Ai register in the event counter mode.
Table 5.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing
function)
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request occurrence timing
TAi IN pin function
TAi OUT pin function
Read from timer Ai register
Write to timer Ai register
Specifications
● External signal input to the TAiIN pin
● The count source’s valid edge can be selected between the falling
and the rising edges by software.
● Up-count or down-count can be switched by external signal or software.
● When the counter overflows or underflows, reload register’s contents
are reloaded and counting continues.
When count start bit is set to “1.”
When count start bit is cleared to “0.”
When the counter overflows or underflows.
Count source input
Programmable I/O port, pulse output, or up-count/down-count switch
signal input
Counter value can be read out.
● While counting is stopped
When a value is written to timer Ai register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to timer Ai register, it is written to only reload
register. (Transferred to counter at next reload time.)
7751 Group User’s Manual
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TIMER A
5.4 Event counter mode
Table 5.4.2 Specifications of event counter mode (when using two-phase pulse signal processing
function with timers A2, A3, and A4)
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request occurrence timing
TAjIN, TAj OUT (j = 2 to 4) pin function
Read from timer Aj register
Write to timer Aj register
5–20
Specifications
External signal (two-phase pulse) input to the TAjIN or TAjOUT pin (j =
2 to 4)
● Up-count or down-count can be switched by external signal (twophase pulse).
● When the counter overflows or underflows, reload register’s contents
are reloaded and counting is continued.
When count start bit is set to “1.”
When count start bit is cleared to “0.”
When the counter overflows or underflows.
Two-phase pulse input
Counter value can be read out.
● While counting is stopped
When a value is written to timer A2, A3, or A4 register, it is written
to both reload register and counter.
● While counting is in progress
When a value is written to timer A2, A3, or A4 register, it is written
to only reload register. (Transferred to counter at next reload time.)
7751 Group User’s Manual
TIMER A
5.4 Event counter mode
b7
b6
b5
✕ ✕ 0
b4
b3
b2
b1
b0
0 1
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 1 : Event counter mode
1
At reset
RW
0
RW
0
RW
2
Pulse output function select bit
0 : No pulse output (TAiOUT pin
functions as a programmable I/O
port.)
1 : Pulse output (TAiOUT pin functions
as a pulse output pin.)
0
RW
3
Count polarity select bit
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0
RW
4
Up-down switching factor select
bit
0 : Contents of up-down register
1 : Input signal to TAiOUT pin
0
RW
5
Fix this bit to “0” in event counter mode.
0
RW
6
These bits are ignored in event counter mode.
0
RW
0
RW
At reset
RW
Undefined
RW
7
✕ : It may be either “0” or “1.”
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1
when down-counting, or by FFFF16 – n + 1
when up-counting.
When reading, the register indicates the
counter value.
Fig. 5.4.1 Structures of timer Ai mode register and timer Ai register in event counter mode
7751 Group User’s Manual
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TIMER A
5.4 Event counter mode
5.4.1 Setting for event counter mode
Figures 5.4.2 and 5.4.3 show an initial setting example for registers relevant to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.”
Selecting event counter mode and each function
b7
b0
✕ ✕ 0
0 1
Timer Ai mode register (i = 0 to 4)
(Addresses 56 16 to 5A 16)
Selection of event counter mode
Pulse output function select bit
0: No pulse output
1: Pulse output
Count polarity select bit
0: Counts at falling edge of external signal.
1: Counts at rising edge of external signal.
Up-down switching factor select bit
0: Contents of up-down register
1: Input signal to TAi OUT pin
✕ : It may be either “0” or “1.”
Setting up–down register
b7
b0
Up–down register (Address 44 16)
Timer A0 up–down bit
Timer A1 up–down bit
Timer A2 up–down bit
Timer A3 up–down bit
Timer A4 up–down bit
Set the corresponding up–down bit when the contents of
the up – down register are selected as the up – down
switching factor.
0: Down–count
1: Up–count
Timer A2 two–phase pulse signal processing select bit
Timer A3 two–phase pulse signal processing select bit
Timer A4 two–phase pulse signal processing select bit
Set the corresponding bit to “1” when the two–phase pulse
signal processing function is selected for timers A2 to A4.
0: Two–phase pulse signal processing
function disabled
1: Two–phase pulse signal processing
function enabled
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C 16)
Timer A4 register (Addresses 4F16, 4E16)
Can be set to “0000 16” to “FFFF 16” (n).
✻ The counter divides the count source frequency by n + 1
when down-counting, or by FFFF 16 – n + 1 when upcounting.
Continue to Figure 5.4.3 on next page.
Fig. 5.4.2 Initial setting example for registers relevant to event counter mode (1)
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TIMER A
5.4 Event counter mode
From preceding Figure 5.4.2 .
Setting interrupt priority level
b7
b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 75 16 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits
to level 1-7.
When disabling interrupts, set these
bits to level 0.
Setting port P5 and port P6 direction registers
b7
b0
Port P5 direction register (Address D16)
TA0OUT pin
TA0IN pin
TA1OUT pin
TA1IN pin
TA2OUT pin
TA2IN pin
TA3OUT pin
TA3IN pin
b7
b0
Port P6 direction register (Address 1016)
TA4OUT pin
TA4IN pin
Clear the bit corresponding to the TAi IN pin to “0.”
When selecting the TAi OUT pin’s input signal as up-down switching factor, set the
bit corresponding to the TAi OUT pin to “0.”
When selecting the two–phase pulse signal processing function, set the bit
corresponding to the TAj OUT (j = 2 to 4) pin to “0.”
Setting the count start bit to “1”
b7
b0
Count start register
(Address 40 16)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Count starts
Fig. 5.4.3 Initial setting example for registers relevant to event counter mode (2)
7751 Group User’s Manual
5–23
TIMER A
5.4 Event counter mode
5.4.2 Operation in event counter mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ The counter counts the count source’s valid edges.
➂ When the counter underflows or overflows, the reload register’s contents are reloaded and counting
continues.
➃ The timer Ai interrupt request bit is set to “1” when the counter underflows or overflows in ➂.
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
Figure 5.4.4 shows an example of operation in the event counter mode.
n = Reload register’s contents
FFFF16
Counter contents (Hex.)
Starts counting.
n
000016
Time
Set to “1” by software.
Count start bit “1”
“0”
Set to “1” by software.
Up-down bit “1”
“0”
Timer Ai interrupt “1”
request bit “0”
Cleared to “0” when interrupt request is accepted or cleared by software.
Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down
switching factor select bit = “0” ).
Fig. 5.4.4 Example of operation in event counter mode (without pulse output function and two-phase
pulse signal processing function)
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TIMER A
5.4 Event counter mode
(1) Switching between up-count and down-count
The up-down register (address 4416) or the input signal from the TAiOUT pin is used to switch the upcount from and to the down-count. This switching is performed by the up-down bit when the up-down
switching factor select bit (bit 4 at addresses 56 16 to 5A 16) is “0,” and by the input signal from the
TAiOUT pin when the up-down switching factor select bit is “1.”
When switching the up-count/down-count, this switching is actually performed when the count source’s
next valid edge is input.
●Switching by up-down bit
The counter down-counts when the up-down bit is “0,” and up-counts when the up-down bit is “1.”
Figure 5.4.5 shows the structure of the up-down register.
●Switching by TAiOUT pin’s input signal
The counter down-counts when the TAiOUT pin’s input signal is at “L” level, and up-counts when the
TAi OUT pin’s input signal is at “H” level.
When using the TAiOUT pin input signal to switch the up-count/down-count, set the port P5 and P6
direction registers’ bits which correspond to the TAi OUT pin for the input mode.
b7
b6
b5
b4
b3
b2
b1
b0
Up-down register (Address 4416)
Bit
Functions
Bit name
0
Timer A0 up-down bit
1
Timer A1 up-down bit
0 : Down-count
1 : Up-count
This function is valid when the
contents of the up-down register are
selected as the up-down switching
factor.
At reset
RW
0
RW
0
RW
0
RW
0
RW
2
Timer A2 up-down bit
3
Timer A3 up-down bit
4
Timer A4 up-down bit
0
RW
5
Timer A2 two-phase pulse signal 0 : Disabled Two-phase pulse signal
processing function
processing select bit
(Note)
1 : Enabled Two-phase pulse signal
processing function
Timer A3 two-phase pulse signal
processing select bit
(Note)
When not using the two-phase pulse
signal processing function, make
Timer A4 two-phase pulse signal
sure to set the bit to “0.”
processing select bit
(Note)
The value is “0” at reading.
0
WO
0
WO
0
WO
6
7
Note: Use the LDM or STA instruction when writing to bits 5 to 7.
Fig. 5.4.5 Structure of up-down register
7751 Group User’s Manual
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TIMER A
5.4 Event counter mode
5.4.3 Select functions
The following describes the selective pulse output, and two-phase pulse signal processing functions.
(1) Pulse output function
The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses
56 16 to 5A 16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output
pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAiOUT pin
outputs pulses of which polarity is inverted each time the counter underflows or overflows. (Refer to
Figure 5.3.6.)
When the count start bit (address 4016) is “0” (count stopped), the TAiOUT pin outputs “L” level.
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TIMER A
5.4 Event counter mode
(2) Two-phase pulse signal processing function (Timers A2 to A4)
For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the twophase pulse signal processing select bits (bits 5 to 7 at address 4416) to “1.” (Refer to Figure 5.4.5.)
Figure 5.4.6 shows the timer A2, A3, and A4 mode registers when the two-phase pulse signal
processing function is selected.
With timers selecting the two-phase pulse signal processing function, the timer counts two kinds of
pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal
processing: normal processing and quadruple processing. In timers A2 and A3, normal processing
is performed; in timer A4, quadruple processing is performed.
For some bits of the port P5 and P6 direction registers correspond to pins used for two-phase pulse
input, set these bits for the input mode.
b7
b6
b5
b4
b3
b2
b1
b0
✕ ✕ 0
1
0
0
0
1
Timer A2 mode register (Address 5816)
Timer A3 mode register (Address 5916)
Timer A4 mode register (Address 5A16)
✕ : It may be either “0” or “1.”
Fig. 5.4.6 Timer A2, A3, and A4 mode registers when two-phase pulse signal processing function is
selected
●Normal processing
The timer up-counts the rising edges to the TAkIN pin when the phase has the relationship that the
TAk IN pin’s input signal level goes from “L” to “H” while the TAk OUT (k = 2 and 3) pin’s input signal
is “H” level.
The timer down-counts the falling edges to the TAk IN pin when the phase has the relationship that
the TAkIN pin’s input signal level goes from “H” to “L” while the TAkOUT pin’s input signal is “H” level.
(Refer to Figure 5.4.7.)
“H”
TAkOUT
“L”
“H”
TAkIN
(k=2, 3) “L”
UpUp
count
Upcount
Upcount
+1
+1
+1
Downcount
Downcount
Downcount
–1
–1
–1
Fig. 5.4.7 Normal processing
7751 Group User’s Manual
5–27
TIMER A
5.4 Event counter mode
●Quadruple processing
The timer up-counts all rising and falling edges to the TA4 OUT and TA4IN pins when the phase has
the relationship that the TA4IN pin’s input signal level goes from “L” to “H” while the TA4OUT pin’s
input signal is “H” level.
The timer down-counts all rising and falling edges to the TA4 OUT and TA4 IN pins when the phase
has the relationship that the TA4 IN pin’s input signal level goes from “H” to “L” while the TA4 OUT
pin’s input signal is “H” level. (Refer to Figure 5.4.8.)
Table 5.4.3 lists the input signals to the TA4OUT and TA4IN pins when the quadruple processing is
selected.
“H”
TA4OUT
“L”
Up-count all edges
+1
TA4IN
+1
+1
+1
Down-count all edges
–1
+1
+1
+1
+1
+1
Table 5.4.3 TA4 OUT and TA4 IN pins’ input signals when
quadruple operation is selected
Input signal to TA4OUT pin Input signal to TA4IN pin
5–28
–1
Down-count all edges
Fig. 5.4.8 Quadruple processing
Down-count
–1
“L”
+1
“H” level
“L” level
Rising
Falling
“H” level
“L” level
Rising
Falling
–1
“H”
Up-count all edges
Up-count
–1
Rising
Falling
“L” level
“H” level
Falling
Rising
“H” level
“L” level
7751 Group User’s Manual
–1
–1
–1
–1
–1
TIMER A
5.4 Event counter mode
[Precautions when operating in event counter mode]
1. By reading the timer Ai register, the counter value can be read out at any timing while counting is in
progress. However, when the timer Ai register is read at the reload timing shown in Figure 5.4.9, a value
“FFFF 16” (at the underflow) or “000016” (at the overflow) is read out. When reading the timer Ai register
after setting a value to the register while counting is not in progress and before the counter starts
counting, the set value is read out correctly.
(1) For down-count
(2) For up-count
Reload
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
n–1
FFFF n – 1
Counter value
(Hex.)
Read value
(Hex.)
FFFD FFFE FFFF
n+1
FFFD FFFE FFFF 0000 n + 1
Time
n = Reload register’s contents
n
Time
n = Reload register’s contents
Fig. 5.4.9 Reading timer Ai register
2. The TAi OUT pin is used for all functions listed below. Accordingly, only one of these functions can be
selected for each timer.
•Switching between up-count and down-count by TAi OUT pin’s input signal
•Pulse output function
•Two-phase pulse signal processing function for timers A2 to A4
7751 Group User’s Manual
5–29
TIMER A
5.5 One-shot pulse mode
5.5 One-shot pulse mode
In this mode, the timer outputs a pulse which has an arbitrary width once. (Refer to Table 5.5.1.) When a
trigger occurs, the timer outputs “H” level from the TAiOUT pin for an arbitrary time. Figure 5.5.1 shows the
structures of the timer Ai mode register and timer Ai register in the one-shot pulse mode.
Table 5.5.1 Specifications of one-shot pulse mode
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request occurrence timing
TAi IN pin function
TAi OUT pin function
Read from timer Ai register
Write to timer Ai register
Specifications
f 2/f 4, f16/f 32, f 64/f128 , or f512 /f1024
● Down-count
● When the counter value becomes “000016,” reload register’s contents are reloaded and counting stops.
● If a trigger occurs during counting, reload register’s contents are
reloaded then and counting continues.
● When a trigger occurs. (Note)
● Internal or external trigger can be selected by software.
,
● When the counter value becomes “000016 ”
● When count start bit is cleared to “0”
When counting stops.
Programmable I/O port or trigger input
One-shot pulse output
An undefined value is read out.
● While counting is stopped
When a value is written to timer Ai register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to timer Ai register, it is written to only
reload register. (Transferred to counter at next reload time.)
Note: The trigger is generated with the count start bit = “1.”
5–30
7751 Group User’s Manual
TIMER A
5.5 One-shot pulse mode
b7
b6
b5
0
b4
b3
b2
b1
b0
1 1 0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
0
1
2
3
Bit name
Functions
Operating mode select bits
6
(b8)
b0 b7
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
At reset
RW
Undefined
WO
1 0 : One-shot pulse mode
Fix this bit to “1” in one-shot pulse mode.
b4 b3
Trigger select bits
0 0 : Writing “1” to one-shot start bit
0 1 : (TAiIN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAiIN pin’s input signal
1 1 : Rising edge of TAiIN pin’s input signal
Fix this bit to “0” in one-shot pulse mode.
Count source select bits
7
(b15)
b7
RW
@
4
5
At reset
b1 b0
b0
b7 b6
0 0 : f2/f4
0 1 : f16/f32
1 0 : f64/f128
1 1 : f512/f1024
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the “H” level
width of the one-shot pulse output from the
TAiOUT pin is expressed as follows : n / fi.
fi: Frequency of count source (f2/f4, f16/f32, f64/f128, or f512/f024)
Fig. 5.5.1 Structures of timer Ai mode register and timer Ai register in one-shot pulse mode
7751 Group User’s Manual
5–31
TIMER A
5.5 One-shot pulse mode
5.5.1 Setting for one-shot pulse mode
Figures 5.5.2 and 5.5.3 show an initial setting example for registers relevant to the one-shot pulse mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.”
Selecting one-shot pulse mode and each function
b7
b0
0
1 1 0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16)
Selection of one-shot pulse mode
Trigger select bits
b4 b3
00:
Writing “1” to one-shot start bit: Internal trigger
01:
1 0 : Falling of TAi IN pin’s input signal: External trigger
1 1 : Rising of TAi IN pin’s input signal: External trigger
Count source select bits
b7 b6
0 0 : f 2/f4
0 1 : f 16/f32
1 0 : f 64/f128
1 1 : f 512/f1024
Setting “H” level width of one-shot pulse
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 46 16)
Timer A1 register (Addresses 4916, 48 16)
Timer A2 register (Addresses 4B16, 4A 16)
Timer A3 register (Addresses 4D16, 4C 16)
Timer A4 register (Addresses 4F16, 4E 16)
Can be set to “0000 16” to “FFFF 16” (n).
n
fi
fi: Frequency of count source
However, if n = “0000 16”, the counter does not
operate and the TAi OUT pin outputs “L” level. At this
time, no timer Ai interrupt request occurs.
Note. “H” level width =
Setting interrupt priority level
b7
b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 75 16 to 79 16)
Interrupt priority level select bits
When using interrupts, set these bits to level 1-7.
When disabling interrupts, set these bits to level 0.
Continue to Figure 5.5.3 .
Fig. 5.5.2 Initial setting example for registers relevant to one-shot pulse mode (1)
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7751 Group User’s Manual
TIMER A
5.5 One-shot pulse mode
From preceding Figure 5.5.2.
When external trigger
is selected
When internal trigger
is selected
Setting port P5 and port P6 direction registers
b7
Setting count start bit to “1”
b0
Port P5 direction register
(Address D 16)
b7
b0
Count start register (Address 40 16)
Timer A0 count start bit
TA0IN pin
TA1IN pin
TA2IN pin
TA3IN pin
b7
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
b0
Port P6 direction register
(Address 10 16)
Timer A4 count start bit
TA4IN pin
Set the corresponding bit to “0.”
Setting one-shot start bit to “1”
b7
Setting count start bit to “1”
b7
b0
One-shot start register (Address
4216)
b0
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Timer A3 count start bit
Timer A4 count start bit
Trigger input to TAi IN pin
Trigger generated
Count starts
Fig. 5.5.3 Initial setting example for registers relevant to one-shot pulse mode (2)
7751 Group User’s Manual
5–33
TIMER A
5.5 One-shot pulse mode
5.5.2 Count source
In the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5A 16) select
the count source. Table 5.5.2 lists the count source frequency.
Table 5.5.2 Count source frequency
Count source
select bits
b7
0
b6
0
1
1
0
1
1
0
f(X IN) = 25 MHz
Clock source for peripheral
Clock source for peripheral
devices select bit = “0”
devices select bit = “1”
Count
source
Count source
Frequency
Frequency
f4
f2
12.5 MHz
6.25 MHz
f 32
f 16
1.5625 MHz
781.25 kHz
f128
f1024
195.3125 kHz
24.4141 kHz
Clock source for peripheral
devices select bit = “0”
Count source
Frequency
f4
10 MHz
f32
1.25 MHz
f 64
390.625 kHz
f 128
312.5 kHz
f512
48.8281 kHz
f1024
39.0625 kHz
Clock source for peripheral devices select bit : bit 2 at address 5F 16
5–34
f(X IN) = 40 MHz
7751 Group User’s Manual
TIMER A
5.5 One-shot pulse mode
5.5.3 Trigger
The counter is enabled for counting when the count start bit (address 40 16) is set to “1.” The counter starts
counting when a trigger is generated after it has been enabled. An internal or an external trigger can be
selected as that trigger.
An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 5A 16) are “002”
or “012”; an external trigger is selected when the bits are “102” or “11 2.”
If a trigger is generated during counting, the reload register’s contents are reloaded and the counter
continues counting. If generating a trigger during counting, make sure that a certain time which is equivalent
to one cycle of the timer’s count source or more has passed between the previous generated trigger and
a new generated trigger.
(1) When selecting internal trigger
A trigger is generated when writing “1” to the one-shot start bit (address 4216). Figure 5.5.4 shows
the structure of the one-shot start register.
(2) When selecting external trigger
A trigger is generated at the falling of the TAiIN pin’s input signal when bit 3 at addresses 5616 to 5A16
is “0,” or at its rising when bit 3 is “1.”
When using an external trigger, set the port P5 and P6 direction registers’ bits which correspond to
the TAi IN pins for the input mode.
b7
b6
b5
b4
b3
b2
b1
b0
One-shot start register (Address 42 16)
.
Bit
Bit name
Functions
At reset
RW
0
WO
0
WO
0
WO
0
Timer A0 one-shot start bit
1
Timer A1 one-shot start bit
1 : Start outputting one-shot pulse
(valid when selecting internal
trigger.)
2
Timer A2 one-shot start bit
The value is “0” at reading.
3
Timer A3 one-shot start bit
0
WO
4
Timer A4 one-shot start bit
0
WO
Undefined
–
7 to 5 Nothing is assigned.
Fig. 5.5.4 Structure of one-shot start register
7751 Group User’s Manual
5–35
TIMER A
5.5 One-shot pulse mode
5.5.4 Operation in one-shot pulse mode
➀ When the one-shot pulse mode is selected with the operating mode select bits, the TAi OUT pin outputs
“L” level.
➁ When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when
a trigger is generated.
➂ When the counter starts counting, the TAi OUT pin outputs “H” level. (However, if the timer Ai register has
a value “000016” set in it, the counter does not operate and the output from the TAi OUT pin remains “L.”
The timer Ai interrupt request does not occur.)
➃ When the counter value becomes “000016,” the output from the TAiOUT pin becomes “L” level. Additionally,
the reload register’s contents are reloaded and the counter stops counting there.
➄ Simultaneously at ➃, the timer Ai interrupt request bit is set to “1.”
This interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
Figure 5.5.5 shows an example of operation in the one-shot pulse mode.
When a trigger is generated after ➃ above, the counter and TAi OUT pin perform the same operations
beginning from ➁ again. Furthermore, if a trigger is generated during counting, the counter down-counts
once after this generated new trigger, and it continues counting with the reload register’s contents reloaded.
If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of
the timer’s count source or more has passed between the previous generated trigger and a new generated
trigger.
The one-shot pulse output from the TAi OUT pin can be disabled by clearing the timer Ai mode register’s bit
2 to “0.” Accordingly, timer Ai can be also used as an internal one-shot timer that does not perform the
pulse output. In this case, the TAiOUT pin functions as a programmable I/O port.
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7751 Group User’s Manual
TIMER A
5.5 One-shot pulse mode
Counter contents (Hex.)
FFFF16
n = Reload register’s contents
Starts counting.
Stops
counting.
Stops counting.
Starts counting.
n
Reloaded
Reloaded
000116
Time
Set to “1” by software.
➀ Count start bit
“1”
“0”
➁ Trigger during counting
TAiIN pin “H”
input signal “L”
1 / fi ✕ (n)
1 / fi ✕ (n+1)
One-shot pulse “H”
output from “L”
TAiOUT pin
Timer Ai interrupt “1”
request bit “0”
fi = Frequency of count source
(f2/f4, f16/f32, f64/f128, or f512/f1024)
Cleared to “0” when interrupt request is accepted
or cleared by software.
➀ When the count start bit = “0” (counting stopped), the TAiOUT pin outputs “L” level.
➁ When a trigger is generated during counting, the counter counts the count source n + 1 times after a new trigger is generated.
Note: The above applies when an external trigger (rising of TAiIN pin’s input signal) is selected.
Fig. 5.5.5 Example of operation in one-shot pulse mode (selecting external trigger)
7751 Group User’s Manual
5–37
TIMER A
5.5 One-shot pulse mode
[Precautions when operating in one-shot pulse mode]
1. If the count start bit is cleared to “0” during counting, the counter stops counting and the TAiOUT pin’s
output level becomes “L.” At the same time, the timer Ai interrupt request bit is set to “1.”
2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when
selecting an external trigger, there will be a delay equivalent to one cycle of count source at maximum
from when a trigger is input to the TAiIN pin till when a one-shot pulse is output.
TAiIN pin’s “H”
input signal “L”
Trigger input
Count
source
One-shot pulse
output from
TAiOUT pin
Starts outputting of one-shot pulse
Output delay
Note: The above applies when an external trigger (falling of TAiIN pin’s input signal) is selected.
Fig. 5.5.6 Output delay in one-shot pulse output
3. When setting the timer’s operating mode in one of the followings, the timer Ai interrupt request bit is set
to “1.”
●When the one-shot pulse mode is selected after a reset
●When the operating mode is switched from the timer mode to the one-shot pulse mode
●When the operating mode is switched from the event counter mode to the one-shot pulse mode
Therefore, when using the timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt
request bit to “0” after above setting.
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7751 Group User’s Manual
TIMER A
5.6 Pulse width modulation (PWM) mode
5.6 Pulse width modulation (PWM) mode
In this mode, the timer continuously outputs pulses which have an arbitrary width. (Refer to Table 5.6.1.)
Figure 5.6.1 shows the structures of the timer Ai mode register and timer Ai register in the PWM mode.
Table 5.6.1 Specifications of PWM mode
Item
Specifications
Count source
f 2/f 4, f16/f 32, f 64/f128 , or f512 /f1024
Count operation
● Down-count (operating as an 8-bit or 16-bit pulse width modulator)
● Reload register’s contents are reloaded at rising of PWM pulse and
counting continues.
● A trigger generated during counting does not affect the counting.
Count start condition
● When a trigger is generated.
● Internal or external trigger can be selected by software.
Count stop condition
When count start bit is cleared to “0.”
Interrupt request occurrence timing
At falling of PWM pulse
TAiIN pin function
Programmable I/O port or trigger input
TAiOUT pin function
PWM pulse output
An undefined value is read out.
Read from timer Ai register
● While counting is stopped
Write to timer Ai register
When a value is written to timer Ai register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to timer Ai register, it is written to only
reload register. (Transferred to counter at next reload time.)
7751 Group User’s Manual
5–39
TIMER A
5.6 Pulse width modulation (PWM) mode
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16)
Bit
0
Bit name
Functions
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
b1 b0
Operating mode select bits
1 1 : PWM mode
1
2
3
Fix this bit to “1” in PWM mode.
b4 b3
Trigger select bits
0 0 : Writing “1” to count start bit
0 1 : (TAiIN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAi IN pin’s input signal
1 1 : Rising edge of TAi IN pin’s input signal
4
5
16/8-bit PWM mode select bit
6
Count source select bits
0 : As a 16-bit pulse width modulator
1 : As an 8-bit pulse width modulator
b7 b6
0 0 : f2/f4
0 1 : f16/f32
1 0 : f64/f128
1 1 : f512/f1024
7
<When operating as a 16-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 49 16, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C 16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Functions
Bit
15 to 0 These bits can be set to “0000 16” to “FFFE 16.”
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
n
TAiOUT pin is expressed as follows:
fi
At reset
RW
Undefined
WO
fi: Frequency of count source (f 2/f4, f16/f32, f64/f128 , or f512/f1024 )
<When operating as an 8-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 49 16, 4816)
Timer A2 register (Addresses 4B16, 4A 16)
Timer A3 register (Addresses 4D16, 4C 16)
Timer A4 register (Addresses 4F16, 4E 16)
Functions
Bit
7 to 0 These bits can be set to “00 16” to “FF 16.”
Assuming that the set value = m, PWM
pulse’s period output from the TAi OUT pin is
8
expressed as follows: (m + 1)(2 – 1)
fi
15 to 8 These bits can be set to “00 16” to “FE16.”
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
TAiOUT pin is expressed as follows:
n(m + 1)
At reset
RW
Undefined
WO
Undefined
WO
fi
fi: Frequency of count source (f 2/f4, f16/f32, f64/f128 , or f512/f1024 )
Fig. 5.6.1 Structures of timer Ai mode registers and timer Ai registers in PWM mode
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7751 Group User’s Manual
TIMER A
5.6 Pulse width modulation (PWM) mode
5.6.1 Setting for PWM mode
Figures 5.6.2 and 5.6.3 show an initial setting example for registers relevant to the PWM mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.”
Selecting PWM mode and each function
b7
b0
1 1 1
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16)
Selection of PWM mode
Trigger select bits
b4 b3
00:
Writing “1” to count start bit: Internal trigger
01:
1 0 : Falling of TAi IN pin’s input signal : External trigger
1 1 : Rising of TAi IN pin’s input signal : External trigger
16/8-bit PWM mode select bit
0 : Operates as 16-bit pulse width modulator
1 : Operates as 8-bit pulse width modulator
Count source select bits
b7 b6
0 0 : f2/f4
0 1 : f16/f32
1 0 : f64/f128
1 1 : f512/f1024
Setting PWM pulse’s period and “H” level width
● When operating as 16-bit pulse width modulator
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A 16)
Timer A3 register (Addresses 4D16, 4C 16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Can be set to “0000 16” to “FFFE16” (n)
● When operating as 8-bit pulse width modulator
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A 16)
Timer A3 register (Addresses 4D16, 4C 16)
Timer A4 register (Addresses 4F16, 4E 16)
Can be set to “00 16” to “FF16” (m)
Can be set to “00 16” to “FE16” (n)
Note: When operating as 8-bit pulse width modulator
(m+1) (2 8 – 1)
Period =
fi
“H” level width =
n(m+1)
Note: When operating as 16-bit pulse width modulator
(2 16 – 1)
Period =
fi
“H” level width =
n
fi
fi
fi : Frequency of count source
However, if n = “00 16”, the pulse width modulator
does not operate and the TAi OUT pin outputs “L”
level. At this time, no timer Ai request occurs.
fi : Frequency of count source
However, if n = “0000 16”, the pulse width modulator does
not operate and the TAi OUT pin outputs “L” level. At this time,
no timer Ai request occurs.
Continue to Figure 5.6.3 .
Fig. 5.6.2 Initial setting example for registers relevant to PWM mode (1)
7751 Group User’s Manual
5–41
TIMER A
5.6 Pulse width modulation (PWM) mode
From preceding Figure5.6.2.
Setting interrupt priority level
b7
b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 75 16 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits to
level 1 – 7.
When disabling interrupts, set these bits to
level 0.
When external
trigger is selected
When internal trigger is selected
Setting port P5 and port P6 direction registers
b7
Setting count start bit to “1”
b0
Port P5 direction register
(Address D 16)
b7
b0
Count start register (Address 4016)
TA0IN pin
TA1IN pin
TA2IN pin
TA3IN pin
b7
b0
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Port P6 direction
register (Address 1016)
Timer A4 count start bit
TA4IN pin
Clear the corresponding bit to “0.”
Setting count start bit to “1”
b7
b0
Count start register (Address 40 16)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Trigger input
to TAi IN pin
Trigger generated
Count starts
Fig. 5.6.3 Initial setting example for registers relevant to PWM mode (2)
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7751 Group User’s Manual
TIMER A
5.6 Pulse width modulation (PWM) mode
5.6.2 Count source
In the PWM mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A 16) select the count
source. Table 5.6.2 lists the count source frequency.
Table 5.6.2 Count source frequency
Count source
select bits
b7
0
b6
0
1
1
0
1
1
0
f(X IN) = 25 MHz
Clock source for peripheral
Clock source for peripheral
devices select bit = “0”
devices select bit = “1”
Count source
Count source
Frequency
Frequency
f4
f2
12.5 MHz
6.25 MHz
f 32
f 16
1.5625 MHz
781.25 kHz
f 128
f 1024
f(X IN) = 40 MHz
Clock source for peripheral
devices select bit = “0”
Count source
Frequency
f4
10 MHz
f 32
1.25 MHz
195.3125 kHz
f 64
390.625 kHz
f 128
312.5 kHz
24.4141 kHz
f 512
48.8281 kHz
f 1024
39.0625 kHz
Clock source for peripheral devices select bit : bit 2 at address 5F 16
5.6.3 Trigger
When a trigger is generated, the TAiOUT pin starts outputting PWM pulses. An internal or an external trigger
can be selected as that trigger.
An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 5A 16) are “002”
or “012”; an external trigger is selected when the bits are “102” or “11 2.”
A trigger generated during outputting of PWM pulses is ignored and it does not affect the pulse output
operation.
(1) When selecting internal trigger
A trigger is generated when writing “1” to the count start bit (at address 4016).
(2) When selecting external trigger
A trigger is generated at the falling of the TAiIN pin’s input signal when bit 3 at addresses 5616 to 5A16
is “0,” or at its rising when bit 3 is “1.” However, the trigger input is accepted only when the count
start bit is “1.”
When using an external trigger, set the port P5 and P6 direction registers’ bits which correspond to
the TAi IN pins for the input mode.
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TIMER A
5.6 Pulse width modulation (PWM) mode
5.6.4 Operation in PWM mode
➀ When the PWM mode is selected with the operating mode select bits, the TAiOUT pin outputs “L” level.
➁ When a trigger is generated, the counter (pulse width modulator) starts counting and the TAi OUT pin
outputs a PWM pulse (Notes 1 and 2).
➂ The timer Ai interrupt request bit is set to “1” each time the PWM pulse level goes from “H” to “L.”
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
➃ Each time a PWM pulse has been output for one period, the reload register’s contents are reloaded and
the counter continues counting.
The following explains operation of the pulse width modulator.
[16-bit pulse width modulator]
When the 16/8-bit PWM mode select bit is set to “0,” the counter operates as a 16-bit pulse width
modulator. Figures 5.6.4 and 5.6.5 show operation examples of the 16-bit pulse width modulator.
[8-bit pulse width modulator]
When the 16/8-bit PWM mode select bit is set to “1,” the counter is divided into 8-bit halves. Then, the
high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit
prescaler. Figures 5.6.6 and 5.6.7 show operation examples of the 8-bit pulse width modulator.
Notes 1: If a value “000016” is set into the timer Ai register when the counter operates as a 16-bit pulse
width modulator, the pulse width modulator does not operate and the output from the TAiOUT
pin remains “L” level. The timer Ai interrupt request does not occur. Similarly, if a value “0016”
is set into the high-order 8 bits of the timer Ai register when the counter operates as an 8bit pulse width modulator, the same is performed.
2: When the counter operates as an 8-bit pulse width modulator, the TAiOUT pin outputs “L” level
of the PWM pulse which has the same width as set “H” level of the PWM pulse after a trigger
generated. After that, the PWM pulse output starts from the TAiOUT pin.
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7751 Group User’s Manual
TIMER A
5.6 Pulse width modulation (PWM) mode
1 / fi ✕ (216 – 1)
Count source
“H”
TAiIN pin’s input signal
“L”
Trigger is not generated by this signal.
1 / fi ✕ (n)
PWM pulse output “H”
from TAiOUT pin
“L”
Timer Ai interrupt “1”
request bit
“0”
fi: Frequency of count source
(f2/f4, f16/f32, f64/f128, or f512/f1024)
Cleared to “0” when interrupt request is accepted
or cleared by software.
Note: The above applies when reload register (n) = “000316” and an external trigger (rising of TAiIN
pin’s input signal) is selected.
Fig. 5.6.4 Operation example of 16-bit pulse width modulator
n = Reload register’s contents
Counter contents (Hex.)
(1 / fi) ✕ (216 –1)
(1 / Pfi) ✕ (216 –1)
(1 / fi) ✕ (216 –1)
FFFE16
200016
(216 –1) – n
n
000116
Stops
counting.
Restarts counting.
Time
TAiIN pin’s “H”
input signal “L”
➀
PWM pulse
output from “H”
TAiOUT pin “L”
fi: Frequency of count source
(f2/f4, f16/f32, f64/f128, or f512/f1024)
“FFFE16” is set to timer Ai
register.
“000016” is set to timer Ai
register.
“200016” is set to timer Ai
register.
➀ When an arbitrary value is set to the timer Ai register after setting “000016” to it, the timing at which the PWM pulse goes “H”
depends on the timing at which the new value is set.
Note: The above applies when an external trigger (rising of TAiIN pin’s input signal) is selected.
Fig. 5.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during
pulse output)
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TIMER A
5.6 Pulse width modulation (PWM) mode
1 / fi ✕ (m+1) ✕ (28 –1)
➀ Count source
TAiIN pin’s “H”
input signal
“L”
1 / fi ✕ (m+1)
➁ 8-bit prescaler’s “H”
underflow signal
“L”
1 / fi ✕ (m+1) ✕ (n)
PWM pulse output “H”
from TAi OUT pin
“L”
Timer Ai interrupt “1”
request bit “0”
fi: Frequency of count source
(f2/f4, f16/f32 , f64 /f128 , or f512 /f1024 )
Cleared to “0” when interrupt request is accepted or cleared by software.
➀ The 8-bit prescaler counts the count source.
➁ The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal.
Note: The above applies when the reload register’s high-order 8 bits (n) = “02 16 ”
and low-order 8 bits (m) = “02 16” and an external trigger (falling of TAi IN pin input
signal) is selected.
Fig. 5.6.6 Operation example of 8-bit pulse width modulator
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7751 Group User’s Manual
7751 Group User’s Manual
0116
0416
0A16
0016
0216
“040216” is set to timer Ai register.
Restarts
counting.
(1 / fi) ✕ (m + 1) ✕ (28 –1)
“0A0216” is set to timer Ai register.
➀
Stops
counting.
m: Contents of reload register’s low-order 8 bits
“000216” is set to timer Ai register.
(1 / fi) ✕ (m+1) ✕ (28 –1)
Note: The above applies when an external trigger (falling of TAiIN pin’s input signal) is selected.
➀ When an arbitrary value is set to the timer Ai register after setting “0016” to it, the timing at which the PWM pulse level goes “H” depends on the timing at which the new value is set.
fi: Frequency of count source (f2/f4, f16/f32, f64/f128, or f512/f1024)
PWM pulse output “H”
from TAiOUT pin “L”
Counter’s contents (Hex.)
Prescaler's
contents (Hex.)
TAiIN pin’s input “H”
signal “L”
Count source
(1 / fi) ✕ (m+1) ✕ (28 –1)
Time
Time
TIMER A
5.6 Pulse width modulation (PWM) mode
Fig. 5.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during
pulse output)
5–47
TIMER A
5.6 Pulse width modulation (PWM) mode
[Precautions when operating in PWM mode]
1. If the count start bit is cleared to “0” while outputting PWM pulses, the counter stops counting. When the
TAiOUT pin was outputting “H” level at that time, the output level becomes “L” and the timer Ai interrupt
request bit is set to “1.” When the TAiOUT pin was outputting “L” level, the output level does not change
and the timer Ai interrupt request does not occur.
2. When setting the timer’s operating mode in one of the followings, the timer Ai interrupt request bit is set
to “1.”
●When the PWM mode is selected after a reset
●When the operating mode is switched from the timer mode to PWM mode
●When the operating mode is switched from the event counter mode to the PWM mode
Therefore, when using the timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt
request bit to “0” after the above setting.
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7751 Group User’s Manual
CHAPTER 6
TIMER B
6.1 Overview
6.2 Block description
6.3 Timer mode
6.4 Event counter mode
6.5 Pulse period/pulse width measurement mode
TIMER B
6.1 Overview 6.2 Block description
Timer B consists of three counters (Timers B0 to B2) each equipped with a 16-bit reload function. Timers
B0 to B2 have identical functions and operate independently with each other.
6.1 Overview
Timer Bi (i = 0 to 2) has three operating modes listed below.
● Timer mode
The timer counts an internally generated count source.
● Event counter mode
The timer counts an external signal.
● Pulse period/pulse width measurement mode
The timer measures an external signal’s pulse period or pulse width.
6.2 Block description
Figure 6.2.1 shows the block diagram of Timer B. Explanation of registers relevant to Timer B is described
below.
Data bus (odd)
Count source select bits
f 2/f 4
f 16/f 32
f 64/f 128
f 512/f 1024
Data bus (even)
(Low-order 8 bits)
Timer mode
Pulse period/Pulse width measurement mode
TBi IN
Polarity switching
and edge pulse
generating circuit
(High-order 8 bits)
Timer Bi reload register (16)
Event counter
mode
Timer Bi counter (16)
Count start bit
Counter reset circuit
Fig. 6.2.1 Block diagram of Timer B
6–2
7751 Group User’s Manual
Timer Bi
interrupt
request bit
Timer Bi
overflow
flag
TIMER B
6.2 Block description
6.2.1 Counter and reload register (timer Bi register)
Each of timer Bi counter and reload register consists of 16 bits and has the following functions.
(1) Functions in timer mode and event counter mode
The counter down-counts each time count source is input. The reload register is used to store the
initial value of the counter. When the counter underflows, the reload register’s contents are reloaded
into the counter.
Values are set to the counter and reload register by writing a value to the timer Bi register. Table
6.2.1 lists the memory assignment of the timer Bi register.
The value written into the timer Bi register when the counting is not in progress is set to the counter
and reload register. The value written into the timer Bi register when the counting is in progress is
set to only the reload register. In this case, the reload register’s updated contents are transferred to
the counter when the counter underflows next time. The counter value is read out by reading out the
timer Bi register.
Note: When reading and writing from/to the timer Bi register, perform them in a unit of 16 bits. For
more information about the value got by reading the timer Bi register, refer to “[Precautions
when operating in timer mode]” and “[Precautions when operating in event counter
mode].”
(2) Functions in pulse period/pulse width measurement mode
The counter up-counts each time count source is input. The reload register is used to retain the pulse
period or pulse width measurement result. When a valid edge is input to the TBi IN pin, the counter
value is transferred to the reload register. In this mode, the value got by reading the timer Bi register
is the reload register’s contents, so that the measurement result is obtained.
Note: When reading from the timer Bi register, perform it in a unit of 16 bits.
Table 6.2.1 Memory assignment of timer Bi registers
Timer Bi register
Timer B0 register
Timer B1 register
Timer B2 register
High-order byte
Address 5116
Address 5316
Address 5516
Low-order byte
Address 5016
Address 5216
Address 5416
Note: When reset, the contents of the timer Bi register are undefined.
7751 Group User’s Manual
6–3
TIMER B
6.2 Block description
6.2.2 Count start register
This register is used to start and stop counting. Each bit of this register corresponds each timer.
Figure 6.2.2 shows the structure of the count start register.
b7
b6
b5
b4
b3
b2
b1
b0
Count start register (Address 4016)
Bit
Bit name
Functions
0 : Stop counting
1 : Start counting
RW
0
RW
0
Timer A0 count start bit
1
Timer A1 count start bit
0
RW
2
Timer A2 count start bit
0
RW
3
Timer A3 count start bit
0
RW
4
Timer A4 count start bit
0
RW
5
Timer B0 count start bit
0
RW
6
Timer B1 count start bit
0
RW
7
Timer B2 count start bit
0
RW
: Bits 0 to 4 are not used for Timer B.
Fig. 6.2.2 Structure of count start register
6–4
At reset
7751 Group User’s Manual
TIMER B
6.2 Block description
6.2.3 Timer Bi mode register
Figure 6.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used
to select the operating mode of Timer Bi. Bits 2 and 3 and bits 5 to 7 have different functions according
to the operating mode. These bits are described in the paragraph of each operating mode.
b7 b6 b5 b4 b3 b2 b1 b0
Timer Bi mode register (i = 0 to 2) (Addresses 5B 16 to 5D 16)
Bit
0
Bit name
Operating mode select bits
1
2
Functions
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/Pulse width
measurement mode
1 1 : Not selected
These bits have different functions according to the operating mode.
3
At reset
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
–
5
These bits have different functions according to the operating mode.
Undefined
RO
(Note)
6
0
RW
7
0
RW
Note: Bit 5 is ignored in the timer mode and event counter mode; its value is undefined at reading.
Fig. 6.2.3 Structure of timer Bi mode register
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6–5
TIMER B
6.2 Block description
6.2.4 Timer Bi interrupt control register
Figure 6.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer
to “Chapter 4. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16)
Bit
0
Functions
Bit name
Interrupt priority level select bits
1
2
3
Interrupt request bit
7 to 4
Nothing is assigned.
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt request
1 : Interrupt request
0
RW
Undefined
–
b2 b1 b0
Fig. 6.2.4 Structure of timer Bi interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select a timer Bi interrupt’s priority level. When using timer Bi interrupts, select priority
levels 1 to 7. When the timer Bi interrupt request occurs, its priority level is compared with the
processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority
level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = “0.”) To disable
timer Bi interrupts, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when the timer Bi interrupt request occurs. This bit is automatically cleared to
“0” when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by
software.
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TIMER B
6.2 Block description
6.2.5 Port P6 direction register
Timer Bi’s input pins are shared with port P6. When using these pins as Timer Bi’s input pins, set the
corresponding bits of the port P6 direction register to “0” to set these pins for the input mode. Figure 6.2.5
shows the relationship between port P6 direction register and Timer Bi’s input pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P6 direction register (Address 10 16)
Bit
Corresponding pin name
0
TA4 OUT pin
1
TA4 IN pin
Functions
0: Input mode
1: Output mode
When using these pins as
Timer Bi's input pins, set the
corresponding bits to "0."
At reset
RW
0
RW
0
RW
0
RW
2
INT0 pin
3
INT1 pin
0
RW
4
INT2 pin
0
RW
5
TB0 IN pin
0
RW
6
TB1 IN pin
0
RW
7
TB2 IN pin
0
RW
: Bits 0 to 4 are not used for Timer B.
Fig. 6.2.5 Relationship between port P6 direction register and Timer Bi’s input pins
7751 Group User’s Manual
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TIMER B
6.3 Timer mode
6.3 Timer mode
In this mode, the timer counts an internally generated count source. (Refer to Table 6.3.1.) Figure 6.3.1
shows the structures of the timer Bi mode register and timer Bi register in the timer mode.
Table 6.3.1 Specifications of timer mode
Item
Specifications
Count source
f 2/f 4, f16 /f32, f 64/f 128, or f 512/f 1024
Count operation
•Down-count
•When the counter underflows, reload register’s contents are reloaded
and counting continues.
Count start condition
When count start bit is set to “1.”
Count stop condition
When count start bit is cleared to “0.”
Interrupt request occurrence timing When the counter underflows.
TBi IN pin function
Programmable I/O port
Read from timer Bi register
Counter value can be read out.
Write to timer Bi register
● While counting is stopped
When a value is written to the timer Bi register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to the timer Bi register, it is written to only
reload register. (Transferred to counter at next reload time.)
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TIMER B
6.3 Timer mode
b7
b6
b5
✕
b4
b3
b2
b1
b0
✕ ✕ 0 0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 0 : Timer mode
1
2
These bits are ignored in timer mode.
3
(b8)
b0 b7
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
–
5
This bit is ignored in timer mode.
Undefined
–
6
Count source select bits
0
RW
0
RW
At reset
RW
15 to 0 These bits can be set to “000016” to “FFFF16.” Undefined
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
RW
7
(b15)
b7
At reset
b0
b7 b6
0 0 : f2/f4
0 1 : f16/f32
1 0 : f64/f128
1 1 : f512/f1024
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Bit
Functions
Fig. 6.3.1 Structures of timer Bi mode register and timer Bi register in timer mode
7751 Group User’s Manual
6–9
TIMER B
6.3 Timer mode
6.3.1 Setting for timer mode
Figure 6.3.2 shows an initial setting example for registers relevant to the timer mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.”
Selecting timer mode and count source
b7
b0
✕
Timer Bi mode register (i = 0 to 2)
(Addresses 5B 16 to 5D 16)
✕ ✕ 0 0
Selection of timer mode
Count source select bits
b7 b6
0 0 : f2/f4
0 1 : f16/f32
1 0 : f 64/f128
1 1 : f 512/f1024
✕: It may be either “0” or “1.”
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 50 16)
Timer B1 register (Addresses 53 16, 52 16)
Timer B2 register (Addresses 55 16, 54 16)
Can be set to “0000 16” to “FFFF 16” (n).
Note: The counter divides the count source by n + 1.
Setting interrupt priority level
b7
b0
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A 16 to 7C 16)
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
Setting count start bit to “1”
b7
b0
Count start register (Address 40 16)
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
Count starts
Fig. 6.3.2 Initial setting example for registers relevant to timer mode
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TIMER B
6.3 Timer mode
6.3.2 Count source
In the timer mode, the count source select bits (bits 6 and 7 at addresses 5B16 to 5D 16) select the count
source. Table 6.3.2 lists the count source frequency.
Table 6.3.2 Count source frequency
Count source
select bits
b7
b6
0
0
0
1
0
1
1
1
f(X IN) = 25 MHz
Clock source for peripheral
Clock source for peripheral
devices select bit = “0”
devices select bit = “1”
Count source
Count
source
Frequency
Frequency
f4
f2
12.5 MHz
6.25 MHz
f 32
f 16
1.5625 MHz
781.25 kHz
f 128
f 64
390.625 kHz
195.3125 kHz
f 1024
24.4141 kHz
f 512
48.8281 kHz
f(X IN) = 40 MHz
Clock source for peripheral
devices select bit = “0”
Count source
Frequency
f4
10 MHz
f 32
f 128
1.25 MHz
312.5 kHz
f 1024
39.0625 kHz
Clock source for peripheral devices select bit : bit 2 at address 5F 16
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TIMER B
6.3 Timer mode
6.3.3 Operation in timer mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ When the counter underflows, the reload register’s contents are reloaded and counting continues.
➂ The timer Bi interrupt request bit is set to “1” when the counter underflows in ➁. The interrupt request
bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0”
by software.
Figure 6.3.3 shows an example of operation in the timer mode.
n = Reload register’s contents
Counter contents (Hex.)
FFFF16
Starts counting.
1 / fi ✕ (n+1)
Stops counting.
n
Restarts counting.
000016
Time
Set to “1” by software.
Count start bit
Cleared to “0” by software.
“1”
“0”
Timer Bi interrupt “1”
request bit “0”
fi = frequency of count source
(f2/f4, f16/f32, f64/f128, f512/f1024)
Cleared to “0” when interrupt request is
accepted or cleared by software.
Fig. 6.3.3 Example of operation in timer mode
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Set to “1” by software.
TIMER B
6.3 Timer mode
[Precautions when operating in timer mode]
By reading the timer Bi register, the counter value can be read out at any timing while counting is in
progress. However, if the timer Bi register is read at the reload timing shown in Figure 6.3.4, the value
“FFFF16” is read out. When reading the timer Bi register after setting a value to the register while counting
is not in progress and before the counter starts counting, the set value can be read out correctly.
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
n–1
FFFF n – 1
n = Reload register’s contents
Time
Fig. 6.3.4 Reading timer Bi register
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TIMER B
6.4 Event counter mode
6.4 Event counter mode
In this mode, the timer counts an external signal. (Refer to Table 6.4.1.) Figure 6.4.1 shows the structures
of the timer Bi mode register and the timer Bi register in the event counter mode.
Table 6.4.1 Specifications of event counter mode
Specifications
Item
•External signal input to the TBiIN pin
Count source
•The count source’s valid edge can be selected from the falling edge, the rising edge,
or both of the falling and rising edges by software.
•Down-count
Count operation
•When the counter underflows, reload register’s contents are reloaded
and counting continues.
When count start bit is set to “1.”
Count start condition
When count start bit is cleared to “0.”
Count stop condition
Interrupt request occurrence timing When the counter underflows.
Count source input
TBi IN pin function
Read from timer Bi register
Counter value can be read out.
Write to timer Bi register
● While counting is stopped
When a value is written to the timer Bi register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to the timer Bi register, it is written to only
reload register. (Transferred to counter at next reload time.)
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TIMER B
6.4 Event counter mode
b7
b6
b5
✕ ✕ ✕
b4
b3
b2
b1
b0
0 1
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
0 1 : Event counter mode
1
2
Count polarity select bit
b3 b2
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Counts at both falling and rising edges
of external signal
1 1 : Not selected
3
(b8)
b0 b7
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
—
5
This bit is ignored in event counter mode.
Undefined
—
6
These bits are ignored in event counter mode.
0
RW
0
RW
At reset
RW
Undefined
RW
7
(b15)
b7
At reset
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
Fig. 6.4.1 Structures of timer Bi mode register and timer Bi register in event counter mode
7751 Group User’s Manual
6–15
TIMER B
6.4 Event counter mode
6.4.1 Setting for event counter mode
Figure 6.4.2 shows an initial setting example for registers relevant to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4.
INTERRUPTS.”
Selecting event counter mode and count polarity
b7
b0
✕ ✕ ✕
0 1
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D 16)
Selection of event counter mode
Count polarity select bits
b3 b2
0
0
1
1
0 : Counts at falling of external signal.
1 : Counts at rising of external signal.
0 : Counts at both of falling and rising of external signal.
1 : Not selected.
✕: It may be either “0” or “1.”
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 50 16)
Timer B1 register (Addresses 53 16, 52 16)
Timer B2 register (Addresses 55 16, 54 16)
Can be set to “0000 16” to “FFFF 16” (n).
Note: The counter divides the count source by n + 1.
Setting interrupt priority level
b7
b0
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A 16 to 7C 16)
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
Setting port P6 direction register
b7
b0
Port P6 direction register (Address 1016)
TB0IN pin
TB1IN pin
Clear the corresponding bit to “0.”
TB2IN pin
Setting count start bit to “1”
b7
b0
Count start register (Address 40 16)
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
Fig. 6.4.2 Initial setting example for registers relevant to event counter mode
6–16
7751 Group User’s Manual
Count starts
TIMER B
6.4 Event counter mode
6.4.2 Operation in event counter mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ The counter counts the count source’s valid edges.
➂ When the counter underflows, the reload register’s contents are reloaded and counting continues.
➃ The timer Bi interrupt request bit is set to “1” when the counter underflows in ➂.
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
Figure 6.4.3 shows an example of operation in the event counter mode.
n = Reload register’s contents
Counter contents (Hex.)
FFFF16
Starts counting.
Stops counting.
n
Restarts counting .
000016
Time
Set to “1” by software.
Count start bit
Cleared to “0” by
software.
Set to “1” by software.
“1”
“0”
Timer Bi interrupt “1”
request bit “0”
Cleared to “0” when interrupt request is accepted or cleared by software.
Fig. 6.4.3 Example of operation in event counter mode
7751 Group User’s Manual
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TIMER B
6.4 Event counter mode
[Precautions when operating in event counter mode]
By reading the timer Bi register, the counter value can be read out at any timing while counting is in
progress. However, if the timer Bi register is read at the reload timing shown in Figure 6.4.4, the value
“FFFF16” is read out. When reading the timer Bi register after setting a value to the register while counting
is not in progress and before the counter starts counting, the set value can be read out correctly.
Reload
Counter value
(Hex.)
2
1
0
Read value
(Hex.)
2
1
0
n
FFFF n – 1
n = Reload register’s contents
Fig. 6.4.4 Reading timer Bi register
6–18
n–1
7751 Group User’s Manual
Time
TIMER B
6.5 Pulse period/pulse width measurement mode
6.5 Pulse period/pulse width measurement mode
In these mode, the timer measures an external signal’s pulse period or pulse width. (Refer to Table 6.5.1.)
Figure 6.5.1 shows the structures of the timer Bi mode register and timer Bi register in the pulse period/
pulse width measurement mode.
● Pulse period measurement
The timer measures the pulse period of the external signal that is input to the TBi IN pin.
● Pulse width measurement
The timer measures the pulse width (“L” level and “H” level widths) of the external signal that is input
to the TBi IN pin.
Table 6.5.1 Specifications of pulse period/pulse width measurement mode
Item
Specifications
Count source
f 2/f 4, f16 /f32, f 64/f128 , or f512 /f1024
Count operation
● Up-count
● Counter value is transferred to reload register at valid edge of measurement pulse, and counting continues after clearing the counter
value to “000016.”
Count start condition
When count start bit is set to “1.”
Count stop condition
When count start bit is cleared to “0.”
Interrupt request occurrence timing ● When valid edge of measurement pulse is input (Note 1).
TBiIN pin function
Read from timer Bi register
Write to timer Bi register
● When counter overflows (Timer Bi overflow flag✽ is set to “1” simultaneously).
Measurement pulse input
The value got by reading timer Bi register is the reload register’s
contents, measurement result (Note 2).
Impossible.
Timer Bi overflow flag✽: The bit used to identify the source of an interrupt request occurrence.
Notes 1: This interrupt request does not occur when the first valid edge is input after the timer starts
counting.
2: The value read out from the timer Bi register is undefined until the second valid edge is input after
the timer starts counting.
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TIMER B
6.5 Pulse period/pulse width measurement mode
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D 16)
Bit
0
Bit name
Functions
Operating mode select bits
b1 b0
Measurement mode select bits
b3 b2
1
2
3
1 0 : Pulse period/Pulse width
measurement mode
0 0 : Pulse period measurement
(Interval between falling edges
of measurement pulse)
0 1 : Pulse period measurement
(Interval between rising edges
of measurement pulse)
1 0 : Pulse width measurement
(Interval from falling edge to rising
edge, and from rising edge to falling
edge of measurement pulse)
1 1 : Not selected
4
Nothing is assigned.
5
Timer Bi overflow flag
(Note)
0 : No overflow
1 : Overflow
6
Count source select bits
b7 b6
7
0 0 : f2/f4
0 1 : f16/f32
1 0 : f64/f128
1 1 : f512/f1024
At reset
RW
0
RW
0
RW
0
RW
0
RW
Undefined
–
Undefined
RO
0
RW
0
RW
Note: The timer Bi overflow flag is cleared to “0” by writing to the timer Bi mode register with the
count start bit = “1.”
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 50 16)
Timer B1 register (Addresses 5316, 52 16)
Timer B2 register (Addresses 5516, 54 16)
Bit
Functions
15 to 0 The measurement result of pulse period or
pulse width is read out.
At reset
RW
Undefined
RO
Fig. 6.5.1 Structures of timer Bi mode register and timer Bi register in pulse period/pulse width
measurement mode
6–20
7751 Group User’s Manual
TIMER B
6.5 Pulse period/pulse width measurement mode
6.5.1 Setting for pulse period/pulse width measurement mode
Figure 6.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement
mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.”
7751 Group User’s Manual
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TIMER B
6.5 Pulse period/pulse width measurement mode
Selecting pulse period/pulse width measurement mode and each function
b7
b0
1 0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Selection of pulse period/pulse width measurement mode
Measurement mode select bits
b3 b2
0 0 : Pulse period measurement (Interval between falling edges
of measured pulse)
0 1 : Pulse period measurement (Interval between rising edges
of measured pulse)
1 0 : Pulse width measurement
1 1 : Not selected.
Timer Bi overflow flag (Note)
0: No overflow
1: Overflow
Count source select bits
b7 b6
0
0
1
1
0 : f 2/f4
1 : f 16/f32
0 : f 64/f128
1 : f 512/f1024
Setting interrupt priority level
b7
b0
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A 16 to 7C 16)
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
Setting port P6 direction register
b7
b0
Port P6 direction register (Address 10 16)
TB0 IN pin
TB1 IN pin
Clear the corresponding bit to “0.”
TB2 IN pin
Setting count start bit to “1”
b7
b0
Count start register (Address 4016)
Timer B0 count start bit
Count starts
Timer B1 count start bit
Timer B2 count start bit
Note: The timer Bi overflow flag is a read-only bit. This bit is undefined after reset. This bit is cleared to “0” by writing to the timer Bi mode
register with the count start bit = “1.”
Fig. 6.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement mode
6–22
7751 Group User’s Manual
TIMER B
6.5 Pulse period/pulse width measurement mode
6.5.2 Count source
In the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses
5B16 to 5D16 ) select the count source.
Table 6.5.2 lists the count source frequency.
Table 6.5.2 Count source frequency
Count source
select bits
b7
b6
0
0
0
1
1
0
1
1
f(X IN) = 25 MHz
Clock source for peripheral
Clock source for peripheral
devices select bit = “0”
devices select bit = “1”
Count source
Count
source
Frequency
Frequency
f4
f2
12.5 MHz
6.25 MHz
f 32
f 16
1.5625 MHz
781.25 kHz
f 128
f 64
390.625 kHz
195.3125 kHz
f 1024
24.4141 kHz
f 512
48.8281 kHz
f(X IN) = 40 MHz
Clock source for peripheral
devices select bit = “0”
Count source
Frequency
f4
10 MHz
f 32
1.25 MHz
f 128
312.5 kHz
f 1024
39.0625 kHz
Clock source for peripheral devices select bit : bit 2 at address 5F 16
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TIMER B
6.5 Pulse period/pulse width measurement mode
6.5.3 Operation in pulse period/pulse width measurement mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ The counter value is transferred to the reload register when an valid edge of the measurement pulse
is detected. (Refer to section “(1) Pulse period/pulse width measurement.”)
➂ The counter value is cleared to “000016” after the transfer in ➁, and the counter continues counting.
➃ The timer Bi interrupt request bit is set to “1” when the counter value is cleared to “0000 16” in ➂ (Note).
The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request
bit is cleared to “0” by software.
➄ The timer repeats operations ➁ to ➃ above.
Note: The timer Bi interrupt request does not occur when the first valid edge is input after the timer starts
counting.
(1) Pulse period/pulse width measurement
The measurement mode select bits (bits 2 and 3 at addresses 5B16 to 5D16) specify whether the pulse
period of an external signal is measured or its pulse width is done. Table 6.5.3 lists the relationship
between the measurement mode select bits and the pulse period/pulse width measurements.
Make sure that the measurement pulse interval from the falling to the rising, and from the rising to
the falling are two cycles of the count source or more. Additionally, use software to identify whether
the measurement result indicates the “H” level or the “L” level width.
Table 6.5.3 Relationship between measurement mode select bits and pulse period/pulse width measurements
b3
0
0
1
b2
0
1
0
Pulse period/pulse width measurement
Pulse period measurement
1
1
Not selected
6–24
Pulse width measurement
Measurement interval (Valid edges)
From falling to falling (Falling)
From rising to rising (Rising)
From falling to rising, and from rising to falling
(Falling and rising)
7751 Group User’s Manual
TIMER B
6.5 Pulse period/pulse width measurement mode
(2) Timer Bi overflow flag
The timer Bi interrupt request occurs when the measurement pulse’s valid edge is input or the
counter overflows. The timer Bi overflow flag is used to identify the cause of the interrupt request,
that is, whether it is an overflow occurrence or an effective edge input.
The timer Bi overflow flag is set to “1” by an overflow. Accordingly, the cause of the interrupt request
occurrence is identified by checking the timer Bi overflow flag in the interrupt routine. When a value
is written to the timer Bi mode register with the count start bit = “1,” the timer Bi overflow flag is
cleared to “0” at the next count timing of the count source
The timer Bi overflow flag is a read-only bit.
Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow
flag to do that.
Figure 6.5.3 shows the operation during pulse period measurement. Figure 6.5.4 shows the operation
during pulse width measurement.
Count source
Measurement pulse
“H”
“L”
Transferred
(undefined value)
Reload register
counter
transfer timing
➀
Transferred
(measured value)
➀
➁
Timing at which counter is
cleared to “000016”
Count start bit “1”
“0”
Timer Bi interrupt “1”
request bit
“0”
Timer Bi overflow flag
“1”
Cleared to “0” when interrupt request is accepted or
cleared by software.
“0”
➀ Counter is initialized by completion of measurement.
➁ Counter overflow.
Note: The above applies when measurement is performed for an interval from one falling to the next falling
of the measurement pulse.
Fig. 6.5.3 Operation during pulse period measurement
7751 Group User’s Manual
6–25
TIMER B
6.5 Pulse period/pulse width measurement mode
Count source
Measurement pulse
“H”
“L”
Reload register
counter
transfer timing
Transferred
(undefined
value)
➀
Transferred
Transferred (measured
(measured
value)
value)
➀
➀
Transferred
(measured
value)
➀
Timing at which counter is
cleared to “000016”
Count start bit
“1”
“0”
Timer Bi interrupt “1”
request bit “0”
Timer Bi overflow flag
“1”
Cleared to “0” when interrupt request is accepted or
cleared by software.
“0”
➀ Counter is initialized by completion of measurement.
➁ Counter overflow.
Fig. 6.5.4 Operation during pulse width measurement
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7751 Group User’s Manual
➁
TIMER B
6.5 Pulse period/pulse width measurement mode
[Precautions when operating in pulse period/pulse width measurement mode]
1. The timer Bi interrupt request occurs by the following two causes:
● Input of measured pulse’s valid edge
● Counter overflow
When the overflow is the cause of the interrupt request occurrence, the timer Bi overflow flag is set to
“1.”
2. After reset, the timer Bi overflow flag is undefined. When writing to the timer Bi mode register with the
count start bit = “1,” this flag can be cleared to “0” at the next count timing of the count source.
3. An undefined value is transferred to the reload register when the first valid edge is input after the counter
starts counting. In this case, the timer Bi interrupt request does not occur.
4. The counter value at start of counting is undefined. Accordingly, the timer Bi interrupt request may occur
by the overflow immediately after the counter starts counting.
5. If the contents of the measurement mode select bits are changed after the counter starts counting, the
timer Bi interrupt request bit is set to “1.” When writing the same value which has been set yet to the
measurement mode select bits, the timer Bi interrupt request bit is not changed, that is, the bit retains
the state.
6. If the input signal to the TBiIN pin is affected by noise, etc., the counter may not perform the exact
measurement. We recommend to verify, by software, that the measurement values are within a constant
range.
7751 Group User’s Manual
6–27
TIMER B
6.5 Pulse period/pulse width measurement mode
MEMORANDUM
6–28
7751 Group User’s Manual
CHAPTER 7
SERIAL I/O
7.1 Overview
7.2 Block description
7.3 Clock synchronous serial I/O mode
7.4 Clock asynchronous serial I/O (UART) mode
SERIAL I/O
7.1 Overview
This chapter describes the Serial I/O.
The Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer
for the exclusive use of them and can operate independently. UART0 and UART1 have the same functions.
7.1 Overview
UARTi (i = 0 and 1) has the following 2 operating modes:
●Clock synchronous serial I/O mode
Transmitter and receiver use the same clock as the transfer clock. Transfer data has the length of 8 bits.
●Clock asynchronous serial I/O (UART) mode
Transfer rate and transfer data format can arbitrarily be set. The user can select a 7-bit, 8-bit, or 9-bit
length as the transfer data length.
●Clock synchronous serial I/O mode
Transfer data length of 8 bits (LSB first)
Transfer data length of 8 bits (MSB first)
●UART mode
Transfer data length of 7 bits
Transfer data length of 8 bits
Transfer data length of 9 bits
Fig. 7.1.1 Transfer data formats in each operating mode
7–2
7751 Group User’s Manual
SERIAL I/O
7.2 Block description
7.2 Block description
Figure 7.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below.
Data bus (odd)
Data bus (even)
Bit converter
0
0
0
RxDi
0
0
0
D 8 D 7 D6 D5 D4 D3 D 2 D1 D 0
UARTi receive
buffer register
UARTi receive register
UART
1/16
BRG count source
select bits
f2/f4
f16/f32
f64/f128
f512/f1024
0
BRGi
1 / (n+1)
Clock
synchronous
Clock
synchronous
Clock synchronous
(internal clock selected)
Transfer clock
Transmit control
circuit
Transfer clock
UART
1/16
1/2
Receive
control circuit
Clock synchronous
(internal clock selected)
UARTi transmit register
Clock synchronous
(external clock selected)
D 8 D 7 D6 D5 D 4 D3 D2 D 1 D 0
CLKi
TxDi
UARTi transmit
buffer register
Bit converter
CTSi / RTSi
Data bus (odd)
n: Values set in UARTi baud rate register (BRGi)
Data bus (even)
Fig. 7.2.1 Block diagram of Serial I/O
7751 Group User’s Manual
7–3
SERIAL I/O
7.2 Block description
7.2.1 UARTi transmit/receive mode register
Figure 7.2.2 shows the structure of UARTi transmit/receive mode register. The serial I/O mode select bits
is used to select UARTi’s operating mode. Bits 4 to 6 are described in the section “7.4.2 Transfer data
format,” and bit 7 is done in the section “7.4.8 Sleep mode.”
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
Bit
0
Bit name
Serial I/O mode select bits
1
2
Functions
At reset
RW
0 0 0 : Serial I/O disabled
(P8 functions as a programmable
I/O port.)
0 0 1 : Clock synchronous serial I/O
mode
0 1 0 : Not selected
0 1 1 : Not selected
1 0 0 : UART mode
(Transfer data length = 7 bits)
1 0 1 : UART mode
(Transfer data length = 8 bits)
1 1 0 : UART mode
(Transfer data length = 9 bits)
1 1 1 : Not selected
0
RW
0
RW
0
RW
b2 b1 b0
3
Internal/External clock select bit
0 : Internal clock
1 : External clock
0
RW
4
Stop bit length select bit
(Valid in UART mode) ( Note)
0 : One stop bit
1 : Two stop bits
0
RW
5
Odd/Even parity select bit
(Valid in UART mode when
parity enable bit is “1”) (Note)
0 : Odd parity
1 : Even parity
0
RW
6
Parity enable bit
(Valid in UART mode) ( Note)
0 : Parity disabled
1 : Parity enabled
0
RW
7
Sleep select bit
(Valid in UART mode) ( Note)
0 : Sleep mode cleared (ignored)
1 : Sleep mode selected
0
RW
Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be either “0”
or “1.”) Additionally, fix bit 7 to “0.”
Fig. 7.2.2 Structure of UARTi transmit/receive mode register
7–4
7751 Group User’s Manual
SERIAL I/O
7.2 Block description
(1) Internal/External clock select bit (bit 3)
[Clock synchronous serial I/O mode]
By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 34 16, 3C16) becomes the count source of
BRGi (described later). The BRGi output of which frequency is divided by 2 becomes the transfer
clock. Additionally, the transfer clock is output from the CLK i pin.
By setting this bit to “1” in order to select an external clock, the clock input to the CLK i pin
becomes the transfer clock.
[UART mode]
By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 34 16, 3C16) becomes the count source of
the BRGi (described later). Then, the CLKi pin functions as a programmable I/O port.
By setting this bit to “1” in order to select an external clock, the clock input to the CLK i pin
becomes the count source of BRGi.
Always in the UART mode, the BRGi output of which frequency is divided by 16 is the transfer
clock.
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SERIAL I/O
7.2 Block description
7.2.2 UARTi transmit/receive control register 0
Figure 7.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to
“7.2.1 (1) Internal/External clock select bit.” For bit 7, refer to “7.2.2 transfer data format.”
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 0 (Address 3416 )
UART1 transmit/receive control register 0 (Address 3C16)
Bit
0
Bit name
BRG count source select bits
1
Functions
b1 b0
0 0 : f2 / f4
0 1 : f16 / f32
1 0 : f64 / f128
1 1 : f512 / f1024
At reset
RW
0
RW
0
RW
2
CTS/RTS select bit
0 : CTS function selected.
1 : RTS function selected.
0
RW
3
Transmit register empty flag
0 : Data present in transmit register.
(During transmitting)
1 : No data present in transmit register.
(Transmitting completed)
1
RO
Undefined
–
0
RW
6 to 4
7
Nothing is assigned.
Transfer format select bit
(Used in clock synchronous
serial I/O mode) (Note)
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
Note: Fix bit 7 to “0” in the UART mode or when Serial I/O is ignored.
Fig. 7.2.3 Structure of UARTi transmit/receive control register 0
____ ____
(1) CTS/RTS select bit (bit 2)
____
____
By clearing this bit to “0” in order to select the CTS function, pins P8 0 and P84 function as CTS input
pins, and the input signal of “L” level to these____
pins becomes one of the transmission conditions.
____
By setting this bit to “1” in order to select the RTS function, pins P80 and P8 4 become RTS output
____
pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is “0” (reception disabled), the RTS
output pin outputs “H” level.
The output level of this pin becomes “L” when the receive enable bit is set to “1.” It becomes “H”
when reception starts and it becomes “L” when reception is completed.
(2) Transmit register empty flag (bit 3)
This flag is cleared to “0” when the UARTi transmit buffer register’s contents are transferred to the
UARTi transmit register. When transmission is completed and the UARTi transmit register becomes
empty, this flag is set to “1.”
7–6
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SERIAL I/O
7.2 Block description
7.2.3 UARTi transmit/receive control register 1
Figure 7.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to each
operation mode’s description.
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Bit
Bit name
Functions
At reset
RW
0
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0
RW
1
Transmit buffer empty flag
0 : Data present in transmit buffer
register.
1 : No data present in transmit
buffer register.
1
RO
2
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0
RW
3
Receive complete flag
0 : No data present in receive
buffer register.
1 : Data present in receive buffer
register.
0
RO
4
Overrun error flag
(Note 1)
0 : No overrun error
1 : Overrun error detected
0
RO
5
Framing error flag (Notes 1, 2)
(Valid in UART mode)
0 : No framing error
1 : Framing error detected
0
RO
6
Parity error flag
(Notes 1, 2)
(Valid in UART mode)
0 : No parity error
1 : Parity error detected
0
RO
7
(Notes 1, 2) 0 : No error
Error sum flag
(Valid in UART mode)
1 : Error detected
0
RO
Notes 1: Bit 4 is cleared to “0” when clearing the receive enable bit to “0.”
Bits 5 and 6 are cleared to “0” when one of the following is performed:
•clearing the receive enable bit to “0.”
•reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out.
Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.”
2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode.
Fig. 7.2.4 Structure of UARTi transmit/receive control register 1
7751 Group User’s Manual
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SERIAL I/O
7.2 Block description
(1) Transmit enable bit (bit 0)
By setting this bit to “1,” UARTi enters the transmission enable state. By clearing this bit to “0” during
transmission, UARTi enters the transmission disable state after the transmission which is performed
at that time is completed.
(2) Transmit buffer empty flag (bit 1)
This flag is set to “1” when data set in the UARTi transmit buffer register is transferred from the
UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data
is set in the UARTi transmit buffer register.
(3) Receive enable bit (bit 2)
By setting this bit to “1,” UARTi enters the reception enable state. By clearing this bit to “0” during
reception, UARTi quits the reception then and enters the reception disable state.
(4) Receive complete flag (bit 3)
This flag is set to “1” when data is ready in the UARTi receive register and that is transferred to the
UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to “0” when the
low-order byte of the UARTi receive buffer register is read out or when the receive enable bit (bit 2)
is cleared to “0.”
7–8
7751 Group User’s Manual
SERIAL I/O
7.2 Block description
7.2.4 UARTi transmit register and UARTi transmit buffer register
Figure 7.2.5 shows the block diagram of transmit section; Figure 7.2.6 shows the structure of UARTi
transmit buffer register.
Data bus (odd)
Data bus (even)
Bit converter
D8
D7
D6
D5
D4
D3
D2
D1
SP : Stop bit
PAR : Parity bit
2SP
SP
SP
9-bit UART
Parity
enabled
Parity
disabled
UARTi transmit
buffer register
8-bit UART
9-bit UART
Clock sync.
UART
TxDi
PAR
1SP
D0
Clock sync.
7-bit UART
8-bit UART
Clock sync.
7-bit UART
UARTi transmit register
“0”
Fig. 7.2.5 Block diagram of transmit section
(b15)
(b8)
b7
b0
b7
b0
UART0 transmit buffer register (Addresses 3316, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
Bit
Functions
At reset
RW
8 to 0 Transmit data is set.
Undefined
WO
15 to 9 Nothing is assigned.
Undefined
–
Fig. 7.2.6 Structure of UARTi transmit buffer register
7751 Group User’s Manual
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SERIAL I/O
7.2 Block description
The UARTi transmit buffer register is used to set transmit data. Set the transmit data into the low-order
byte of this register when operating in the clock synchronous serial I/O mode or when a 7-bit or 8-bit length
of transfer data is selected in the UART mode. When a 9-bit length of transfer data is selected in the UART
mode, set the transmit data into the UARTi transmit buffer register as follows:
•Bit 8 of the transmit data into bit 0 of high-order byte of this register.
•Bits 7 to 0 of the transmit data into the low-order byte of this register.
The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit
register when the transmission conditions are satisfied, and then it is output from the TxDi pin synchronously
with the transfer clock. The UARTi transmit buffer register becomes empty when the data which is set in
the UARTi transmit buffer register is transferred to the UARTi transmit register. Accordingly, the user can
set next transmit data.
When selecting the “MSB first” in the clock synchronous serial I/O mode, the data of which bit position was
reversed is written, as a transmit data, into the UARTi transmit buffer register. (Refer to section “7.3.2
Transfer data format.”) Transmission operation itself is the same whichever format is selected, “LSB first”
or “MSB first.”
When quitting the transmission which is in progress and setting the UARTi transmit buffer register again,
follow the procedure described bellow:
➀ Clear the serial I/O mode select bits (bits 2 to 0 at addresses 30 16, 38 16) to “000 2” (Serial I/O disabled).
➁ Set the serial I/O mode select bits again.
➂ Set the transmit enable bit (bit 0 at addresses 35 16, 3D 16) to “1” (transmission enabled) and set transmit
data in the UARTi transmit buffer register.
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SERIAL I/O
7.2 Block description
7.2.5 UARTi receive register and UARTi receive buffer register
Figure 7.2.7 shows the block diagram of receive section; Figure 7.2.8 shows the structure of UARTi receive
buffer register.
Data bus (odd)
Data bus (even)
Bit converter
0
0
0
SP : Stop bit
PAR : Parity bit
Parity
enabled
2SP
RxDi
0
SP
SP
0
0
D8
9-bit UART
UART
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
8-bit UART
9-bit UART
Clock sync.
PAR
Parity
disabled
1SP
0
Clock sync.
7-bit UART
8-bit UART
Clock sync.
7-bit UART
UARTi receive register
Fig. 7.2.7 Block diagram of receive section
(b15)
(b8)
b7
b0
b7
b0
UART0 receive buffer register (Addresses 3716, 3616)
UART1 receive buffer register (Addresses 3F16, 3E16)
Bit
Functions
8 to 0 Receive data is read out from here.
15 to 9 Nothing is assigned.
The value is “0” at reading.
At reset
RW
Undefined
RO
0
–
Fig. 7.2.8 Structure of UARTi receive buffer register
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SERIAL I/O
7.2 Block description
The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data.
This register takes in the input signal to the RxD i pin synchronously with the transfer clock, one bit at a
time.
The UARTi receive buffer register is used to read out receive data. When reception is completed, receive
data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer
register. The contents of UARTi receive buffer register is updated when the next data is ready before
reading out the data which has been transferred to the UARTi receive buffer register (i.e., an overrun error
occurs).
When selecting the “MSB first” in the clock synchronous serial I/O mode, bit position of data in the UARTi
receive buffer register is reversed, and then the data of which bit position was reversed is read out, as
receive data. (Refer to section “7.3.2 Transfer data format.”) Reception operation itself is the same
whichever format is selected, “LSB first” or “MSB first.”
The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516,
3D 16 ) to “1” after clearing it to “0.”
Figure 7.2.9 shows the contents of UARTi receive buffer register when reception is completed.
Low-order byte
(addresses 3616, 3E16)
High-order byte
(addresses 3716, 3F16)
b7
In UART mode
(Transfer data length : 9 bits)
In clock synchronous
serial I/O mode
In UART mode
(Transfer data length : 8 bits)
In UART mode
(Transfer data length : 7 bits)
0
b0
0
0
0
0
0
b7
b0
0
Receive data (9 bits)
0
0
0
0
0
0
0
Same value as bit
7 in low-order byte
0
0
0
0
0
0
Receive data (8 bits)
0
Same value as bit
6 in low-order byte
Receive data (7 bits)
Fig. 7.2.9 Contents of UARTi receive buffer register when reception is completed
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SERIAL I/O
7.2 Block description
7.2.6 UARTi baud rate register (BRGi)
The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer
clock. It has a reload register. Assuming that a value set in the BRGi is “n” (n = “0016” to “FF 16”), the BRGi
divides the count source frequency by n + 1.
In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and a clock
of which frequency is the BRGi output’s frequency divided by 2 becomes the transfer clock. In the UART
mode, the BRGi is always valid, and a clock of which frequency is the BRGi output’s frequency divided by
16 becomes the transfer clock.
The data which is written to the addresses 3116 and 3916 is written to both the timer register and the reload
register whether transmission/reception is stopped or in progress. Accordingly, writing to their addresses,
perform it while that is stopped.
Figure 7.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 7.2.11 shows the block
diagram of transfer clock generating section.
b7
b0
UART0 baud rate register (Address 3116)
UART1 baud rate register (Address 3916)
Bit
Functions
At reset
RW
7 to 0
Can be set to “0016” to “FF16.”
Assuming that the set value = n, BRGi
divides the count source frequency by n + 1.
Undefined
WO
Fig. 7.2.10 Structure of UARTi baud rate register (BRGi)
<Clock synchronous serial I/O mode>
fi
1/2
BRGi
fEXT
Transmit control circuit
Transfer clock for transmit operation
Receive control circuit
Transfer clock for receive operation
<UART mode>
fi
fEXT
1/16
Transmit control circuit
Transfer clock for transmit operation
1/16
Receive control circuit
Transfer clock for receive operation
BRGi
fi : Clock selected by BRG count source select bits (f2/f4, f16/f32, f64/f128, or f512/f1024)
fEXT : Clock input to CLKi pin (external clock)
Fig. 7.2.11 Block diagram of transfer clock generating section
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SERIAL I/O
7.2 Block description
7.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers
When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be
used. Each interrupt has its corresponding interrupt control register. Figure 7.2.12 shows the structure of
UARTi transmit interrupt control and UARTi receive interrupt control registers.
For details about interrupts, refer to “Chapter 4. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit interrupt control register (Address 7116)
UART0 receive interrupt control register (Address 7216)
UART1 transmit interrupt control register (Address 7316)
UART1 receive interrupt control register (Address 7416)
Bit
Bit name
0
Interrupt priority level select bits
1
2
3
Interrupt request bit
Functions
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
0 : No interrupt request
1 : Interrupt request
0
RW
Undefined
–
b2 b1 b0
7 to 4 Nothing is assigned.
Fig. 7.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers
7–14
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SERIAL I/O
7.2 Block description
(1) Interrupt priority level select bits (bits 0 to 2)
These bits select the priority level of the UARTi transmit interrupt or UARTi receive interrupt. When
using UARTi transmit/receive interrupt, select priority levels 1 to 7. When the UARTi transmit/receive
interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL),
so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However,
this applies when the interrupt disable flag (I) = “0.”) To disable the UARTi transmit/receive interrupt,
set these bits to “000 2” (level 0).
(2) Interrupt request bit (bit 3)
The UARTi transmit interrupt request bit is set to “1” when data is transferred from the UARTi
transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit is set
to “1” when data is transferred from the UARTi receive register to the UARTi receive buffer register.
However, when an overrun error occurs, it does not change.
Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request is
accepted. This bit can be set to “1” or “0” by software.
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SERIAL I/O
7.2 Block description
7.2.8 Port P8 direction register
I/O pins of UARTi are shared with port P8. When using pins P8 2 and P8 6 as serial data input pins (RxD i),
set the corresponding bits of the port P8 direction register
to “0” to set these pins for the input mode. When
____ ____
using pins P80, P81, P83 to P85 and P87 as I/O pins (CTSi/RTSi, CLKi, TxDi) of UARTi, these pins are forcibly
set as I/O pins of UARTi regardless of port P8 direction register’s contents. Figure 7.2.13 shows the
relationship between the port P8 direction register and UARTi’s I/O pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P8 direction register (Address 1416)
Bit
Corresponding pin
0
CTS0/RTS0 pin
1
CLK0 pin
Functions
0 : Input mode
1 : Output mode
When using pins P82 and P86 as
serial data input pins (RxD0, RxD1),
set the corresponding bits to “0.”
RW
0
RW
0
RW
0
RW
0
RW
2
RxD0 pin
3
TxD0 pin
4
CTS1/RTS1 pin
0
RW
5
CLK1 pin
0
RW
6
RxD1 pin
0
RW
7
TxD1 pin
0
RW
Fig. 7.2.13 Relationship between port P8 direction register and UARTi’s I/O pins
7–16
At reset
7751 Group User’s Manual
SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3 Clock synchronous serial I/O mode
Table 7.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 7.3.2 lists
the functions of I/O pins in this mode.
Table 7.3.1 Performance overview in clock synchronous serial I/O mode
Item
Functions
Transfer data format
Transfer data has a length of 8 bits.
LSB first or MSB first can be selected by software.
Transfer rate When selecting internal clock
Clock which is BRGi output’s divided by 2.
When selecting external clock
Transmit/Receive control
____
Maximum 5 Mbps
____
CTS function or RTS function can be selected by software.
Table 7.3.2 Functions of I/O pins in clock synchronous serial I/O mode
Pin name
TxD i (P8 3, P8 7)
Functions
Serial data output
Method of selection
Fixed
(Dummy data is output when performing only reception.)
RxD i (P8 2, P8 6)
Serial data input
Port P8 direction register ✼1’s corresponding bit = “0”
CLKi (P8 1, P8 5)
Transfer clock output
Internal/External clock select bit✼2 = “0”
CTS i/RTS i
(P80, P84)
Transfer clock input
Internal/External clock select bit = “1”
____
____ ____
CTS input
CTS/RTS select bit✼3 = “0”
____
____ ____
RTS output
CTS/RTS select bit = “1”
✼1
Port P8 direction register : Address 14 16
Internal/External clock select bit ✼2: bit 3 at addresses 30 16, 38 16
____ ____
CTS/RTS select bit✼3: bit 2 at addresses 34 16, 3C 16
Notes 1: The TxDi pin outputs “H” level until transmission starts after UARTi’s operating mode is selected.
2: The RxD i pin can be used as a programmable I/O port when performing only transmission.
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.1 Transfer clock (synchronizing clock)
Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select
whether to generate the transfer clock internally or to input it from an external.
The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing
only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register
in order to make the transmit control circuit active.
(1) Generating transfer clock internally
The count source selected with the BRG count source select bits is divided by the BRGi, and its
BRGi output is further divided by 2. This is the transfer clock. The transfer clock is output from the
CLK i pin.
[Setting relevant registers]
•Select an internal clock (bit 3 at addresses 3016, 38 16 = “0”).
•Select the BRGi’s count source (bits 0 and 1 at addresses 3416, 3C16)
•Set “divide value – 1” (= n; 00 16 to FF 16 ) to the BRGi (addresses 31 16, 39 16).
Transfer clock frequency =
fi
2 (n+1)
f i: Frequency of BRGi’s count source (f2/f4, f16/f32, f64/f128 , f512/f1024)
•Enable transmission (bit 0 at addresses 3516, 3D 16 = “1”).
•Set data to the UARTi transmit buffer register (addresses 32 16, 3A 16)
[Pin’s state]
•A transfer clock is output from the CLKi pin.
•Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.)
(2) Inputting transfer clock from an external
A clock input from the CLK i pin is the transfer clock.
[Setting relevant registers]
•Select an external clock (bit 3 at addresses 3016, 38 16 = “1”).
•Enable transmission (bit 0 at addresses 3516, 3D 16 = “1”).
•Set data to the UARTi transmit buffer register (addresses 3216 , 3A16).
[Pin’s state]
•A transfer clock is input from the CLKi pin.
•Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.)
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.2 Transfer data format
LSB first or MSB first can be selected as the transfer data format. Table 7.3.3 lists the relationship between
the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register.
The transfer format select bit (bit 7 at addresses 34 16, 3C 16) selects the transfer data format. When this
bit is cleared to “0,” the set data is written to the UARTi transmit buffer register as the transmit data as
it is. Similarly, the data in the UARTi receive buffer register is read out as the receive data as it is. (Refer
to the upper row in Table 7.3.3.)
When this bit is set to “1,” each bit’s position of set data is reversed, and the resultant data is written to
the UARTi transmit buffer register as the transmit data. Similarly, each bit’s position of data in the UARTi
receive buffer register is reversed, and the resultant data is read out as the receive data. (Refer to the
lower row in Table 7.3.3.)
Note that only the method of writing/reading to and from the UARTi transmit/receive buffer register is
affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by
it.
Table 7.3.3 Relationship between transfer data format and writing/reading to and from UARTi transmit/
receive buffer register
Transfer format
select bit
Transfer data format
Writing to UARTi transmit buffer
register
Data bus
0
LSB
(Least Significant Bit)
first
1
Data bus
UARTi receive
buffer register
DB7
D7
DB7
D7
DB6
D6
DB6
D6
DB5
D5
DB5
D5
DB4
D4
DB4
D4
DB3
D3
DB3
D3
DB2
D2
DB2
D2
DB1
D1
DB1
D1
DB0
D0
DB0
D0
Data bus
MSB
(Most Significant Bit)
first
UARTi transmit
buffer register
Reading from UARTi receive
buffer register
UARTi transmit
buffer register
Data bus
UARTi receive
buffer register
DB7
D7
DB7
D7
DB6
D6
DB6
D6
DB5
D5
DB5
D5
DB4
D4
DB4
D4
DB3
D3
DB3
D3
D2
DB2
D2
DB2
DB1
D1
DB1
D1
DB0
D0
DB0
D0
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.3 Method of transmission
Figures 7.3.1 shows an initial setting example for relevant registers when transmitting. Transmission is
started when all of the following conditions (➀ to ➂) are satisfied. When an external clock is selected,
satisfy conditions ➀ to ➂ with the following precondition satisfied.
<Precondition>
The CLKi pin’s input is “H” level
Note: When an internal clock is selected, above precondition is ignored.
<Transmission conditions>
➀ Transmission is enabled (transmit enable bit = “1”).
➁ _____
Transmit data is present in the UARTi
transmit buffer register (transmit buffer empty flag = “0”)
____
➂ CTS i pin’s input
is
“L”
level
(when
CTS
function selected).
____
Note: When the CTS function is not selected, this condition is ignored.
When using interrupts, it is necessary to set the relevant register to enable interrupts. For details, refer to
“Chapter 4. INTERRUPTS.”
Figure 7.3.2 shows writing data after start of transmission, and Figure 7.3.3 shows detection of transmission’s
completion.
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7
b0
0 ✕ ✕ ✕
0 0 1
Clock synchronous serial I/O mode
Internal/External clock select bit
0: Internal clock
1: External clock
UART0 transmit buffer register (Address 3216)
UART1 transmit buffer register (Address 3A16)
b7
b0
✕: It may be either “0” or “1.”
Set transmit data here.
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
b0
1
BRG count source select bits
b1 b0
Transmit enable bit
1: Transmission enabled
0 0 : f2/f4
0 1 : f16 /f32
1 0 : f64 /f128
1 1 : f512 /f1024
CTS / RTS select bit
0: CTS function selected.
1: RTS function selected ( CTS function disabled).
Transfer format select bit
0: LSB first
1: MSB first
Transmission starts.
(In the case of selecting the CTS function, transmission starts
when the CTSi pin’s input level is “L.”)
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 39 16)
b7
b0
Set to “0016” to “FF 16.”
✽ Necessary only when internal clock is
selected.
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
b0
Interrupt priority level select bits
When using interrupts, set these bits to
level 1-7. When disabling interrupts, set
these bits to level 0.
Fig. 7.3.1 Initial setting example for relevant registers when transmitting
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
[When using interrupts]
[When not using interrupts]
The UARTi transmit interrupt request
occurs when the UARTi transmit buffer
register becomes empty.
Checking state of UARTi transmit buffer register
UART0 transmit/receive control register 1 (Address 3516 )
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
UARTi transmit interrupt
b0
1
Transmit buffer empty flag
0: Data present in transmit buffer register
1: No data present in transmit buffer register
(Writing of next transmit data is possible.)
Writing of next transmit data
UART0 transmit buffer register (Address 32 16)
UART1 transmit buffer register (Address 3A16)
b7
Note : This figure shows the bits and registers required
for processing.
Refer to Figure 7.3.5 about the change of flag state
and the occurrence timing of an interrupt request.
b0
Set transmit data here.
Fig. 7.3.2 Writing data after start of transmission
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
[When using interrupts]
[When not using interrupts]
The UARTi transmit interrupt request
occurs when the transmission starts.
Checking start of transmission
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
UARTi transmit interrupt
b0
Interrupt request bit
0: No interrupt request
1: Interrupt request
(Transmission has started.)
Checking completion of transmission
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
Note : This figure shows the bits and registers required
for processing.
Refer to Figure 7.3.5 about the change of flag state
and the occurrence timing of an interrupt request.
b0
Transmit register empty flag
0: During transmitting
1: Transmitting completed
Processing at completion of transmission
Fig. 7.3.3 Detection of transmission’s completion
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.4 Transmit operation
When the transmit conditions described in page 7-20 are satisfied, the following operations are automatically
performed simultaneously.
•The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
•8 transfer clocks are generated (when an internal clock is selected).
•The transmit buffer empty flag is set to “1.”
•The transmit register empty flag is cleared to “0.”
•The UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.”
The transmit operations are described below.
➀ Data in the UARTi transmit register is transmitted from the TxDi pin synchronously with the falling of the
transfer clock.
➁ This data is transmitted bit by bit sequentially beginning with the least significant bit.
➂ When 1-byte data has been transmitted, the transmit register empty flag is set to “1,” indicating completion
of the transmission.
Figure 7.3.4 shows the transmit operation.
In the case of an internal clock is selected, when the transmit conditions for the next data are satisfied at
completion of the transmission, the transfer clock is generated continuously. Accordingly, when performing
transmission continuously, set the next transmit data to the UARTi transmit buffer register during transmission
(when the transmit register empty flag = “0”). When the transmit conditions for the next data are not
satisfied, the transfer clock stops at “H” level.
Figures 7.3.5 shows an example of transmit timing (when selecting an internal clock).
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
b7
b0
Transmit data
UARTi transmit buffer register
MSB
UARTi transmit register
Transfer clock
LSB
D7 D6
D5 D4 D 3 D2
D7 D6
D1 D0
D5 D 4 D3 D2
D7 D6 D 5 D4
D1
D0
D3 D2
D1
D3
D2
c
c
• • •
• • •
D7 D 6 D5 D4
D7
Fig. 7.3.4 Transmit operation
Tc
Transfer clock
Transmit enable bit
“1”
“0”
Data is set in UARTi transmit buffer register.
Transmit buffer “1”
empty flag “0”
UARTi transmit register
UARTi transmit buffer register.
“H”
CTSi
TCLK
“L”
Stopped because CTSi = “H.”
Stopped because transmit enable bit = “0.”
CLKi
TENDi
TxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transmit register “1”
empty flag “0”
UARTi transmit “1”
interrupt request bit “0”
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies to
the following conditions:
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from an external.)
● Internal clock selected
● CTS function selected.
Tc = TCLK = 2(n+1) /fi
fi: BRGi count source frequency (f2/f4, f16/f32, f64/f128, f512/f1024)
n: Value set to BRGi
Fig. 7.3.5 Example of transmit timing (when selecting internal clock)
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.5 Method of reception
Figures 7.3.6 and 7.3.7 show initial setting examples for relevant registers when receiving. Reception is
started when all of the following conditions (➀ to ➂) are satisfied. When an external clock is selected,
satisfy conditions ➀ to ➂ with the following precondition satisfied.
<Precondition>
The CLK i pin’s input is “H” level.
Note: When an internal clock is selected, above precondition is ignored.
<Reception conditions>
➀ Reception is enabled (receive enable bit = “1”).
➁ Transmission is enabled (transmit enable bit = “1”).
➂ Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”)
When using interrupts, it is necessary to set the relevant register to enable interrupts. For details, refer to
“Chapter 4. INTERRUPTS.”
Figure 7.3.8 shows processing after reception’s completion.
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7
b0
0 ✕ ✕ ✕
0 0 1
Clock synchronous serial I/O mode
Internal/External clock select bit
0: Internal clock
1: External clock
✕: It may be either “0” or “1.”
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
BRG count source select bits
b1 b0
0 0 : f2 /f4
0 1 : f16 /f32
1 0 : f64 /f128
1 1 : f512 /f1024
CTS / RTS select bit
0: CTS function selected ( RTS function disabled).
1: RTS function selected.
Transfer format select bit
0: LSB first
1: MSB first
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b7
b0
Set to 00 16 to FF16 .
✽ Necessary only when an internal clock is selected.
Continued to Figure 7.3.7 on next page.
Fig. 7.3.6 Initial setting example for relevant registers when receiving (1)
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
From preceding Figure 7.3.6
Port P8 direction register (Address 1416)
b7
b0
0
0
RXD0 pin
RXD1 pin
UART0 receive interrupt control register (Address 7216)
UART1 receive interrupt control register (Address 7416)
b7
b0
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
UART0 transmit buffer register (Address 32 16)
UART1 transmit buffer register (Address 3A 16)
b7
b0
Set dummy data here.
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
1
1
Transmit enable bit
1 : Transmission enabled
Receive enable bit
1 : Reception enabled
Note: Set the receive enable bit and the transmit enable bit
to “1” simultaneously.
Reception starts.
Fig. 7.3.7 Initial setting example for relevant registers when receiving (2)
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
[When using interrupts]
[When not using interrupts]
The UARTi receive interrupt request
occurs when reception is completed.
Checking completion of reception
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
UARTi receive interrupt
b0
1
1
Receive complete flag
0: Reception not completed
1: Reception completed
Reading of receive data
UART0 receive buffer register (Address 3616)
UART1 receive buffer register (Address 3E16)
b0
b7
Read out receive data.
Checking error
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D 16)
b0
b7
1
1
Overrun error flag
0: No overrun error
1: Overrun error detected
Processing after reading out receive data
Note : This figure shows the bits and registers required
for processing.
Refer to Figure 7.3.11 about the change of flag
state and the occurrence timing of an interrupt
request.
Fig. 7.3.8 Processing after reception’s completion
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.6 Receive operation
When the receive conditions listed on page 7-26 are satisfied, the UARTi enters the receive enable state.
The receive operations are described below.
➀ The input signal of the RxD i pin is taken into the most significant bit of the UARTi receive register
synchronously with the rising of the transfer clock.
➁ The contents of the UARTi receive register are shifted by 1 bit to the right.
➂ Steps ➀ and ➁ are repeated at each rising of the transfer clock.
➃ When 1-byte data is prepared in the UARTi receive register, the contents of this register are transferred
to the UARTi receive buffer register.
➄ Simultaneously with step ➃, the receive complete flag is set to “1,” and the UARTi receive interrupt
request occurs and its interrupt request bit is set to “1.”
The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
is read out. Figure 7.3.10 shows the receive operation, and Figure 7.3.11 shows an example of receive
timing (when selecting an external clock).
When the transfer format select bit = “1” (MSB first), each bit’s position of this register’s contents is
reversed and the resultant data is read out.
Transmitter side
Receiver side
TxDi
TxDi
RxD i
RxD i
CLK i
CLK i
Fig. 7.3.9 Connection example
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
MSB
LSB
UARTi receive register
Transfer clock
D0
D0
D2
D1
D0
D7
D6
D5
• • •
• • •
D1
D4
D 3 D2
b7
UARTi receive buffer register
D1 D0
b0
Receive data
Fig. 7.3.10 Receive operation
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
Receive enable bit
“1”
“0”
“1”
Transmit enable bit
“0”
Dummy data is set to UARTi transmit buffer register.
Transmit buffer “1”
empty flag
“0”
UARTi transmit register¨← UARTi transmit buffer register
“H”
RTSi
“L”
1/fEXT
CLKi
Received data taken in
D 0 D1 D 2 D3 D4 D5 D6 D 7
RxDi
D 0 D1 D2 D3 D 4 D5
UARTi receive register → UARTi receive buffer register
Receive complete flag
UARTi receive buffer register is read out.
“1”
“0”
UARTi receive “1”
interrupt request bit “0”
The above timing diagram applies to the following
setting conditions:
● External clock selected.
● RTS function selected.
fEXT: Frequency of external clock
Cleared to “0” when interrupt request is accepted or
cleared by software.
: When the CLKi pin’s input level is “H,” satisfy the
following cinditions:
● Transmit enable bit → “1”
● Receive enable bit → “1”
● Writing of dummy data to UARTi transmit
buffer register
Fig. 7.3.11 Example of receive timing (when selecting external clock)
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.7 Process on detecting overrun error
In the clock synchronous serial I/O mode, an overrun error can be detected.
An overrun error occurs when the next data is prepared in the UARTi receive register with the receive
complete flag = “1” (data is present in the UARTi receive buffer register) and that is transferred to the
receive buffer register, in other words, when the next data is prepared before reading out the contents of
the UARTi receive buffer register. When an overrun error occurs, the next receive data is written into the
UARTi receive buffer register, and the UARTi receive interrupt request bit is not changed.
An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive
buffer register and the overrun error flag is set to “1.” The overrun error flag is cleared to “0” by clearing
the receive enable bit to “0.”
When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive
buffer register before performing reception again. When it is necessary to perform retransmission owing to
an overrun error which occurs in the receiver side, set the UARTi transmit buffer register again before
starting transmission again.
The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
➀ Clear the receive enable bit to “0” (reception disabled).
➁ Set the receive enable bit to “1” again (reception enabled).
(2) Method of setting UARTi transmit buffer register again
➀ Clear the serial I/O mode select bits to “000 2” (serial I/O ignored).
➁ Set the serial I/O mode select bits to “001 2” again.
➂ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
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SERIAL I/O
7.3 Clock synchronous serial I/O mode
[Precautions when operating in clock synchronous serial I/O mode]
1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when
performing only reception, transmit operation (setting for transmission) must be performed. In this case,
dummy data is output from the TxD i pin.
2. When receiving, simultaneously set the receive enable bit and the transmit enable bit to “1.”
3. When selecting an external clock, satisfy the following 3 conditions with the input to CLKi pin = “H” level.
<When transmitting>
➀ Set the transmit enable bit to “1.”
➁ Write transmit data to____
the UARTi transmit buffer register.
____
➂ Input “L” level to the CTS i pin (when selecting the CTS function).
<When receiving>
➀ Set the receive enable bit to “1.”
➁ Set the transmit enable bit to “1.”
➂ Write dummy data to the UARTi transmit buffer register.
4. When receiving data, write dummy data to the low-order byte of the UARTi transmission buffer register
for each reception of 1-byte data.
____
5. The output level of the RTSi pin becomes “L” simultaneously at setting the receive enable bit to “1.” The
output level of this pin becomes “H” when receive starts, and it becomes “L” when receive is completed.
The output level of this pin changes regardless of the contents of the transmit enable bit, the transmission
buffer empty flag, and the receive complete flag.
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4 Clock asynchronous serial I/O (UART) mode
Table 7.4.1 lists the performance overview in the UART mode, and Table 7.4.2 lists the functions of I/O pins
in this mode.
Table 7.4.1 Performance overview in UART mode
Item
Functions
Transfer data
Start bit
1 bit
format
Character bit (Transfer data)
Parity bit
7 bits, 8 bits, or 9 bits
Stop bit
1 bit or 2 bits
When selecting internal clock
When selecting external clock
Clock of BRGi output divided by 16
Transfer rate
Error detection
0 bit or 1 bit (Odd or even can be selected.)
Maximum 312.5 kbps
4 types (Overrun, Framing, Parity, and Summing)
Presence of error can be detected only by checking error sum flag.
Table 7.4.2 Functions of I/O pins in UART mode
Pin name
Functions
Fixed
TxD i (P8 3, P8 7)
Serial data output
Method of selection
Port P8 direction register ✼1’s corresponding bit = “0”
RxD i (P8 2, P8 6)
Serial data input
CLKi (P8 1, P8 5)
BRGi’s count source Internal/External clock select bit✼2 = “1”
input
____ ____
____
CTS/RTS select bit ✼3 = “0”
CTS input
____ ____
____ ____
CTSi/ RTSi (P8 0, P8 4)
____
CTS/RTS select bit = “1”
RTS output
✼1
Port P8 direction register : Address 14 16
Internal/External clock select bit ✼2: bit 3 at addresses 30 16, 3816
____ ____
CTS/RTS select bit ✼3: bit 2 at addresses 34 16, 3C 16
Notes 1:
2:
3:
4:
The TxD i pin outputs “H” level while not transmitting after selecting UARTi’s operating mode.
The RxDi pin can be used as a programmable I/O port when performing only transmission.
The CLK
i pin
can be used as a programmable I/O port when selecting internal clock.
___
___
___
The CTSi/RTSi pin can be ___
used as a input port when performing only reception and not using RTS
function (when selecting CTS function).
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.1 Transfer rate (frequency of transfer clock)
The transfer rate is determined by the BRGi (addresses 31 16, 39 16).
When setting “n” into BRGi (n = “00 16” to “FF16”), BRGi divides the count source frequency by n + 1. The
divided clock by BRGi is further divided by 16 and the resultant clock becomes the transfer clock. Accordingly,
the value “n” is expressed by the following formula.
n =
F
16 ✕ B
n: Value set into BRGi (00 16 to FF 16)
F: BRGi’s count source frequency
B: Transfer rate (bps)
— 1
An internal clock or an external clock can be selected as the BRGi’s count source with the internal/external
clock select bit (bit 3 at addresses 3016, 3816). When an internal clock is selected, the clock selected with
the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C 16) becomes the BRGi’s count source.
When an external clock is selected, the clock input to the CLKi pin becomes the BRGi’s count source.
Tables 7.4.3 to 7.4.5 are list the setting examples of transfer rate. Set the same transfer rate between the
transmitter and the receiver.
Table 7.4.3 Setting examples of transfer rate (1)
Transfer
rate (bps)
150
300
f(XIN ) = 25 MHz
Clock source for peripheral devices select bit = “0”
Clock source for peripheral devices select bit = “1”
Actual time
BRGi count BRGi setting
Actual time
BRGi count BRGi setting
value
:
n
(bps)
source
value : n
source
(bps)
150.70
80 (50 16)
f 128
162 (A216)
f 64
149.78
162 (A216)
299.56
80 (50 16)
f 64
f 32
301.41
f 16
162 (A216)
f 32
80 (50 16)
602.82
40 (28 16)
1190.93
162 (A216)
2396.47
4822.53
9527.44
80 (50 16)
599.12
1205.63
40 (28 16)
2381.86
f 32
f4
f2
162 (A216)
4792.94
f4
80 (50 16)
9600
f2
80 (50 16)
9645.06
f4
40 (28 16)
19200
f2
40 (28 16)
19054.88
31250
f2
24 (18 16)
31250.00
600
1200
2400
4800
f 16
f 16
Clock source for peripheral devices select bit : bit 2 at address 5F 16
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
Table 7.4.4 Setting examples of transfer rate (2)
f(X IN) = 24.576 MHz
Transfer
rate (bps)
150
Clock source for peripheral devices select bit = “1”
BRGi count BRGi setting
Actual time
value : n
source
(bps)
159 (9F16)
f 64
150.00
f 32
159 (9F16)
300.00
79 (4F 16)
600.00
1200.00
f 32
f 32
39 (27 16)
39 (27 16)
2400.00
f4
159 (9F16)
1200.00
2400.00
300
f 64
79 (4F 16)
600
f 16
f 16
159 (9F16)
300.00
600.00
79 (4F 16)
f 16
1200
2400
Clock source for peripheral devices select bit = “0”
Actual time
BRGi count BRGi setting
value : n
(bps)
source
79 (4F 16)
150.00
f 128
4800
f2
159 (9F16)
4800.00
f4
79 (4F 16)
4800.00
9600
f2
79 (4F 16)
9600.00
f4
39 (27 16)
9600.00
19200
f2
39 (27 16)
19200.00
f4
19 (13 16)
19200.00
31250
Clock source for peripheral devices select bit : bit 2 at address 5F16
Table 7.4.5 Setting examples of transfer rate (3)
Clock source for peripheral devices select bit = “0”
Transfer
rate (bps)
150
f(X IN) = 39.3216 MHz
Actual time
BRGi count BRGi setting
value : n
source
(bps)
127 (7F16)
150.00
f 128
BRGi count
source
f(XIN ) = 40 MHz
Actual time
BRGi setting
value : n
(bps)
f 128
129 (8116)
150.24
300.00
f 128
64 (40 16)
300
600
f 32
255 (FF16)
f 32
127 (7F16)
600.00
f 32
129 (8116)
300.48
600.96
1200
f 32
63 (3F 16)
1200.00
f 32
64 (40 16)
1201.92
2400
f4
255 (FF16)
2400.00
f 32
32 (20 16)
2367.42
4800
f4
127 (7F16)
f4
129 (8116)
4807.69
9600
f4
f4
63 (3F 16)
4800.00
9600.00
f4
f4
64 (40 16)
9615.38
32 (20 16)
f4
19 (13 16)
18939.39
31250.00
19200
31250
31 (1F 16)
19200.00
Clock source for peripheral devices select bit : bit 2 at address 5F 16
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.2 Transfer data format
The transfer data format can be selected from formats shown in Figure 7.4.1. Bits 4 to 6 at addresses 3016
and 3816 select the transfer data format. (Refer to Figure 7.1.1.) Set the same transfer data format for both
transmitter and receiver sides.
Figure 7.4.2 shows an example of transfer data format. Table 7.4.6 lists each bit in transmit data.
Transfer data length of 7 bits
1ST—7DATA
1SP
1ST—7DATA
2SP
1ST—7DATA—1PAR— 1SP
1ST—7DATA—1PAR— 2SP
Transfer data length of 8 bits
1ST—8DATA
1SP
1ST—8DATA
2SP
1ST—8DATA—1PAR— 1SP
1ST—8DATA—1PAR— 2SP
Transfer data length of 9 bits
1ST—9DATA
1SP
1ST—9DATA
2SP
1ST—9DATA—1PAR— 1SP
1ST—9DATA—1PAR— 2SP
Fig. 7.4.1 Transfer data format
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7751 Group User’s Manual
ST
DATA
PAR
SP
:
:
:
:
Start bit
Character bit (transfer data)
Parity bit
Stop bit
SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
•Example of 1ST–8DATA–1PAR–1SP
Time
Transmit/Receive data
Next transmit/receive data
(When continuously
transferring)
DATA (8 bits)
“H”
ST
LSB
MSB PAR
SP
ST
Fig. 7.4.2 Example of transfer data format
Table 7.4.6 Each bit in transmit data
Name
ST
Start bit
Functions
“L” signal equivalent to 1 character bit which is added immediately before the
character bits. It indicates start of data transmission.
DATA
Character bit
Transmit data which is set in the UARTi transmit buffer register.
PAR
A signal that is added immediately after the character bits in order to improve data
reliability. The level of this signal changes according to selection of odd/even parity
in such a way that the sum of “1”s in this bit and character bits is always an odd
or even number.
Parity bit
ST
Stop bit
“H” level signal equivalent to 1 or 2 character bits which is added immediately after
the character bits (or parity bit when parity is enabled). It indicates finish of data
transmission.
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.3 Method of transmission
Figure 7.4.3 shows an initial setting example for relevant registers when transmitting.
The difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length.
When selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the UARTi transmit
buffer register. When selecting a 9-bit data length, set the transmit data into that low-order byte and bit
0 of that high-order byte.
Transmission is started when all of the following conditions (➀ to ➂) are satisfied:
➀ Transmit is enabled (transmit enable bit = “1”).
➁ Transmit
data is present in the UARTi
transmit buffer register (transmit buffer empty flag = “0”).
____
____
➂ CTS i pin’s input
is
“L”
level
(when
CTS
function selected).
____
Note: When the CTS function is not selected, this condition is ignored.
When using interrupts, it is necessary to set the corresponding register to enable interrupts. For details,
refer to “Chapter 4. INTERRUPTS.”
Figure 7.4.4 shows writing data after start of transmission, and Figure 7.4.5 shows detection of transmission’s
completion.
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
UART0 transmit/receive mode register (Address 30 16)
UART1 transmit/receive mode register (Address 38 16)
b7
b0
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 39 16)
1
b7
b2 b1 b0
b0
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
Set to 00 16 to FF16.
Internal/External clock select bit
0: Internal clock
1: External clock
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
b0
Odd/Even parity select bit
0: Odd parity
1: Even parity
Interrupt priority level select bits
When using interrupts, set these bits to
level 1–7.
When disabling interrupts, set these
bits to level 0.
Parity enable bit
0: Parity disabled
1: Parity enabled
Sleep select bit
0: Sleep mode cleared (ignored)
1: Sleep mode selected
UART0 transmit buffer register (Addresses 33 16, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
b8
b7
b0
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
Set transmit data here.
0
BRG count source select bits
b1 b0
0
0
1
1
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
0: f2/f 4
1: f16/f32
0: f64/f128
1: f512 /f1024
b7
b0
1
CTS/RTS select bit
0: CTS function selected
1: RTS function selected (CTS
function disabled)
Transmit enable bit
1: Transmission enabled
Transmission starts.
(In the case of selecting the CTS function, transmission
starts when the CTSi pin’s input level is “L.”)
Fig. 7.4.3 Initial setting example for relevant registers when transmitting
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
[When using interrupts]
[When not using interrupts]
The UARTi transmit interrupt request
occurs when the UARTi transmit buffer
register becomes empty.
Checking state of UARTi transmit buffer register
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
UARTi transmit interrupt
b0
1
Transmit buffer empty flag
0: Data present in transmit buffer register
1: No data present in transmit buffer register
(Writing of next transmit data is possible.)
Writing of next transmit data
UART0 transmit buffer register (Addresses 33 16, 32 16)
UART1 transmit buffer register (Addresses 3B16, 3A 16)
b15
b8 b7
Note : This figure shows the bits and registers
required for processing.
Refer to Figures 7.4.6 and 7.4.7 about the
change of flag state and the occurrence
timing of an interrupt request.
b0
Set transmit data here.
Fig. 7.4.4 Writing data after start of transmission
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
[When using interrupts]
[When not using interrupts]
The UARTi transmit interrupt request
occurs when the transmission starts.
Checking start of transmission
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
UARTi transmit interrupt
b0
Interrupt request bit
0: No interrupt request
1: Interrupt request
(Transmission has started.)
Checking completion of transmission.
UART0 transmit/receive control register 0 (Address 34 16)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
Note : This figure shows the bits and registers required
for processing.
Refer to Figures 7.4.6 to 7.4.7 about the
change of flag state and the occurrence timing
of an interrupt request.
0
Transmit register empty flag
0: During transmitting
1: Transmitting completed
Processing at completion of transmission
Fig. 7.4.5 Detection of transmission’s completion
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.4 Transmit operation
Simultaneously when the transmit conditions listed on page 7-40 are satisfied, the following operations are
automatically performed.
•The
•The
•The
•The
UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
transmit buffer empty flag is set to “1.”
transmit register empty flag is cleared to “0.”
UARTi transmit interrupt request occurs and the interrupt request bit is set to “1.”
The transmit operations are described below.
➀ Data in the UARTi transmit register is transmitted from the TxDi pin.
➁ This data is transmitted bit by bit sequentially in order of ST→DATA (LSB)→•••→DATA (MSB)→PAR
→SP according to the set transfer data format.
➂ When the stop bit has been transmitted, the transmission register empty flag is set to “1,” indicating
completion of transmission.
When the transmit conditions for the next data are satisfied at completion of transmission, the start bit is
generated following the stop bit, and the next data is transmitted. When performing transmission continuously,
set the next transmit data in the UARTi transmit buffer register during transmission (when the transmit
register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the TxDi pin
outputs “H” level.
Figures 7.4.6 shows example of transmit timing when the transfer data length is 8 bits, and Figure 7.4.7
shows an example of transmit timing when the transfer data length is 9 bits.
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
“1”
Transmit enable bit
“0”
Data is set in UARTi transmit buffer register.
“1”
Transmit buffer
empty flag “0”
UARTi transmit register
“H”
CTSi
UARTi transmit buffer register
“L”
TENDi
Start bit
TxDi
Stopped because transmit enable bit = “0”
Parity bit Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP ST D0 D1
D 2 D3 D4 D5 D6 D 7
P SP
ST D0 D1
“1”
Transmit register
empty flag “0”
UARTi transmit
interrupt request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies to
the following conditions:
● Parity enabled
● 1 stop bit
● CTS function selected
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from an external.)
Tc: 16(n + 1)/fi or 16(n + 1)/fEXT
fi: BRGi count source frequency (f2/f4, f16/f32, f64/f128, f512/f1024)
fEXT: BRGi count source frequency (external clock)
n: Value set to BRGi
Fig. 7.4.6 Example of transmit timing when transfer data length is 8 bits (when parity enabled,
selecting 1 stop bit)
Tc
Transfer clock
“1”
Transmit enable bit
Data is set in UARTi transmit buffer register.
“0”
Transmit buffer
empty flag
“1”
“0”
UARTi transmit register
UARTi transmit buffer register
TENDi
Start bit
TxDi
Transmit register
empty flag
UARTi transmit
interrupt request bit
ST D0 D1
Stop bit Stop bit
Stopped because transmit enable bit = “0”
D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
“1”
“0”
“1”
“0”
Cleared to “0” when interrupt request is accepted or cleared by software.
The above timing diagram applies to
the following conditions:
● Parity disabled
● 2 stop bits
● CTS function disabled
TENDi: Next transmit conditions are examined when this signal level is “H.”
(TENDi is an internal signal. Accordingly, it cannot be read from an external.)
Tc: 16(n + 1)/fi or 16(n + 1)/fEXT
fi: BRGi count source frequency (f2/f4, f16/f32, f64/f128, f512/f1024)
fEXT: BRGi count source frequency (external clock)
n: Value set to BRGi
Fig. 7.4.7 Example of transmit timing when transfer data length is 9 bits (when parity disabled,
selecting 2 stop bits)
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.5 Method of reception
Figure 7.4.8 shows an initial setting example for relevant registers when receiving. Reception is started
when all of the following conditions (➀ and ➁) are satisfied:
➀ Reception is enabled (receive enable bit = “1”).
➁ The start bit is detected.
When using interrupts, it is necessary to set the corresponding register to enable interrupts. For details,
refer to “Chapter 4. INTERRUPTS.”
Figure 7.4.9 shows processing after reception’s completion.
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
UART0 transmit/receive mode register (Address 30 16)
UART1 transmit/receive mode register (Address 38 16)
b7
b0
1
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 39 16)
b2 b1 b0
b7
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
b0
Internal/External clock select bit
0: Internal clock
1: External clock
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Set to 0016 to FF16.
Port P8 direction register (Address 14 16)
b7
b0
0
0
Odd/Even parity select bit
0: Odd parity
1: Even parity
RxD0 pin
RxD1 pin
Parity enable bit
0: Parity disabled
1: Parity enabled
Sleep select bit
0: Sleep mode cleared (ignored)
1: Sleep mode selected
UART0 receive interrupt control register (Address 72 16)
UART1 receive interrupt control register (Address 7416)
b7
b0
Note: Set the transfer data format in
the same way as set on the
transmitter side.
Interrupt priority level select bits
When using interrupts, set these bits to
level 1–7.
When disabling interrupts, set these bits
to level 0.
UART0 transmit/receive control register 0 (Address 34 16)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
0
BRG count source select bits
b1b0
0 0 : f2/f 4
0 1 : f16/f32
1 0 : f64/f128
1 1 : f512 /f1024
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D 16)
b7
b0
1
Receive enable bit
1: Reception enabled
CTS/RTS select bit
0 : CTS function selected ( RTS
function disabled)
1 : RTS function selected
Reception starts when the start
bit is detected.
Fig. 7.4.8 Initial setting example for relevant registers when receiving
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
[When not using interrupts]
[When using interrupts]
The UARTi receive interrupt request
occurs when reception is completed.
Checking completion of reception
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D 16)
b7
UARTi receive interrupt
b0
1
Receive complete flag
0 : Reception not completed
1 : Reception completed
Checking error
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b0
b7
1
Framing error flag
Parity error flag
Error sum flag
0 : No error
1 : Error detected
Reading of receive data
UART0 receive buffer register (Addresses 3716, 3616)
UART1 receive buffer register (Addresses 3F16, 3E16)
b15
b8 b7
b0
0 0 0 0 0 0 0
Read out receive data.
Checking error
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b0
b7
1
Overrun error flag
0 : No overrun error
1 : Overrun error detected
Processing after reading out receive data
Note : This figure shows the bits and registers required
for processing.
Refer to Figure 7.4.11 about the change of flag
state and the occurrence timing of an interrupt
request.
Fig. 7.4.9 Processing after reception’s completion
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.6 Receive operation
When the receive enable bit is set to “1,” the UARTi enters the reception enabled state and reception starts
at detecting ST. The receive operation is described below.
➀ The input signal of the RxD i pin is taken into the most significant bit of the UARTi receive register
synchronously with the transfer clock’s rising.
➁ The contents of UARTi receive register are shifted by 1 bit to the right.
➂ Steps ➀ and ➁ are repeated at each rising of the transfer clock.
➃ When one set of data has been prepared, in other words, the shift according to the selected data format
has been completed; the UARTi receive register’s contents are transferred to the UARTi receive buffer
register.
➄ Simultaneously with step ➃, the receive complete flag is set to “1,” and the UARTi receive interrupt
request occurs and its interrupt request bit is set to “1.”
The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
is read out. Figure 7.4.11 shows an example of receive timing when the transfer data length is 8 bits.
Transmitter side
Receiver side
TxDi
TxDi
RxD i
RxD i
Fig. 7.4.10 Connection example
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
BRGi count
source
“1”
Receive enable bit
“0”
Stop bit
Start bit
RxDi
D1
D0
D7
Sampled “L”
Receive data taken in
Transfer clock
Reception started at falling of start bit
UARTi receive register
UARTi receive buffer register
Receive “1”
complete flag “0”
“H”
RTSi
“L”
UARTi receive interrupt “1”
request bit “0”
The above timinig diagram applies to
the following conditions:
● Parity disabled
● 1 stop bit
● RTS function selected
Cleared to “0” when interrupt request is accepted
or cleared by software.
Fig. 7.4.11 Example of receive timing when transfer data length is 8 bits (when parity disabled,
selecting 1 stop bit)
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.7 Process on detecting error
Errors listed below can be detected in the UART mode:
●Overrun error
An overrun error occurs when the next data is prepared in the UARTi receive register with the receive
completion flag = “1” (that is, data present in the UARTi receive buffer register) and that data is transferred
to the UARTi receive buffer register. In other words, when the next data is prepared before the contents
of the UARTi receive buffer register is read out, an overrun error occurs. When an overrun error occurs,
the next receive data is written into the UARTi receive buffer register, and the UARTi receive interrupt
request bit is not changed.
●Framing error
A framing error occurs when the number of detected stop bits does not match the number of stop bits set.
(The UARTi interrupt request bit becomes “1.”)
●Parity error
A parity error occurs when the sum of “1”s in the parity bit and character bits does not match the number
of “1”s set. (The UARTi interrupt request bit becomes “1.”)
Each error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer
register, and the corresponding error flag is set to “1.” Furthermore, when any of the above errors occurs,
the error sum flag is set to “1.” Accordingly, the error sum flag informs the user whether any error has
occurred or not.
The overrun error flag is cleared to “0” by clearing the receive enable bit to “0.”
The framing error flag and the parity error flag are cleared to “0” by reading the contents of the UARTi
receive buffer register low-order byte or clearing the receive enable bit to “0.” The error sum flag is cleared
to “0” by clearing the all error flags, which are overrun, framing, and parity.
When errors occur during reception, initialize the error flags and the UARTi receive buffer register, and
then perform reception again. When it is necessary to perform retransmission owing to an error which
occurs in the receiver side, set the UARTi transmit buffer register again, and then starts transmission
again.
The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
➀ Clear the receive enable bit to “0” (reception disabled).
➁ Set the receive enable bit to “1” again (reception enabled).
(2) Method of setting UARTi transmit buffer register again
➀ Clear the serial I/O mode select bits to “000 2” (serial I/O ignored).
➁ Set the serial I/O mode select bits again.
➂ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
7.4.8 Sleep mode
This mode is used to transfer data between the specified microcomputers, which are connected by using
UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016, 3816) to “1” when
receiving.
In the sleep mode, receive operation is performed when the MSB (D8 when the transfer data length is 9
bits, D7 when it is 8 bits, D6 when it is 7 bits) of the receive data is “1.” Receive operation is not performed
when the MSB is “0.” (The UARTi receive register’s contents are not transferred to the UARTi receive
buffer register. Additionally, the receive complete flag and error flags do not change and the UARTi receive
interrupt request does not occur.)
The following shows an usage example of sleep mode when the transfer data length is 8 bits.
➀ Set the same transfer data format for the master and slave microcomputers. Select the sleep mode for
the slave microcomputers.
➁ Transmit data, which has “1” in bit 7 and the address of the slave microcomputer with which communicates
in bits 0 to 6, from the master microcomputer to all slave microcomputers.
➂ All slave microcomputers receive data of step ➁. (At this time, the UARTi receive interrupt request
occurs.)
➃ In all slave microcomputers, check in the interrupt routine whether bits 0 to 6 in the receive data match
their addresses.
➄ In the slave microcomputer of which address matches bits 0 to 6 in the receive data, clear the sleep
mode. (Do not clear the sleep mode for the other slave microcomputers.)
By performing steps ➁ to ➄, “specification of the microcomputer performing transfer” is realized.
➅ Transmit data, which has “0” in bit 7, from the master microcomputer. (Only the microcomputer specified
in steps ➁ to ➄ can receive this data. The other microcomputers do not receive this data.)
➆ By repeating step ➅, transfer can be performed between the same microcomputers continuously. When
communicating with another microcomputer, perform steps ➁ to ➄ in order to specify the new slave
microcomputer.
Master
Slave A
Slave B
Transfer data between the master
microcomputer and one slave microcomputer
selected from multiple slave microcomputers.
Slave C
Fig. 7.4.12 Sleep mode
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Slave D
CHAPTER 8
A-D CONVERTER
8.1 Overview
8.2 Block description
8.3 A-D conversion method (succesive
approximation conversion method)
8.4 Absolute accuracy and differential
non-linearity error
8.5 Comparison voltage in 8-bit mode
8.6 One-shot mode
8.7 Repeat mode
8.8 Single sweep mode
8.9 Repeat sweep mode 0
8.10 Repeat sweep mode 1
A-D CONVERTER
8.1 Overview
8.1 Overview
The A-D converter has the performance specifications listed in Table 8.1.1.
Table 8.1.1 Performance specifications of A-D converter
Item
Performance specifications
A-D conversion method
Successive approximation conversion method
Resolution
Either 8 bits or 10 bits can be selected by software
Absolute accuracy
8-bit mode: ±2 LSB
10-bit mode: ±3 LSB
Analog input pin
8 pins (AN 0 to AN 7)
Conversion rate per analog input pin
8-bit mode: 49 φ AD✽ cycles
10-bit mode: 59 φAD✽ cycles
φ AD✽: A-D converter’s operation clock
The A-D converter has the 5 operation modes listed below.
•One-shot mode
This mode is used to perform the operation once for a voltage input from one selected analog input pin.
•Repeat mode
This mode is used to perform the operation repeatedly for a voltage input from one selected analog input
pin.
•Single sweep mode
This mode is used to perform the operation for voltages input from multiple selected analog input pins, one
at a time.
•Repeat sweep mode 0
This mode is used to perform the operation repeatedly for voltages input from multiple selected analog
input pins.
•Repeat sweep mode 1
This mode is used to perform the operation repeatedly for voltages input from all analog input pins. In this
mode, analog input pins are separated into two groups according to the frequency of use. One is the group
for more frequencies of use, and the other is the group for fewer frequencies of use.
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7751 Group User’s Manual
A-D CONVERTER
8.2 Block description
8.2 Block description
Figure 8.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are
described below.
A-D conversion frequency selected
AD
f2/f4
VREF
AVSS
1/2
1/2
Vref
Register
ladder network
Successive
approximation
register
A-D sweep pin select register 1
A-D control register 0
A-D register 0
A-D register 1
A-D register 2
A-D register 3
Decoder
A-D register 4
A-D register 5
A-D register 6
A-D register 7
Data bus (odd)
Data bus (even)
Comparator
AN0
AN1
AN2
AN3
VIN
AN4
AN5
AN6
AN7/ADTRG
Selector
Fig. 8.2.1 Block diagram of A-D converter
7751 Group User’s Manual
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A-D CONVERTER
8.2 Block description
8.2.1 A-D control register 0
Figure 8.2.2 shows the structure of the A-D control register 0. The A-D operation mode select bits 0 select
the operation mode of the A-D converter. The other bits are described below.
b7
b6
b5
b4
b3
b2
b1
b0
A-D control register 0 (Address 1E16)
Bit
0
Bit name
Analog input select bits
(Valid in one-shot and repeat
modes) (Note 1)
1
2
3
A-D operation mode select bits 0
4
Functions
At reset
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
RW
0
RW
b2 b1 b0
0 0 0 : AN 0 selected
0 0 1 : AN 1 selected
0 1 0 : AN 2 selected
0 1 1 : AN 3 selected
1 0 0 : AN 4 selected
1 0 1 : AN 5 selected
1 1 0 : AN 6 selected
1 1 1 : AN 7 selected (Note 2)
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 /
Repeat sweep mode 1 (Note 3)
5
Trigger select bit
0 : Internal trigger
1 : External trigger
0
RW
6
A-D conversion start bit
0 : Stop A-D conversion
1 : Start A-D conversion
0
RW
7
A-D conversion frequency
(φAD) select bit 0
Refer to Table 8.2.1
0
RW
Notes 1: These bits are ignored in the single sweep and repeat sweep mode 0 and repeat
sweep mode 1. (They may be either “0” or “1.”)
2: When selecting an external trigger, the AN 7 pin cannot be used as an analog input pin.
3: Use the A-D operation mode select bit 1 (bit 2 at address 1F16) to select either the
repeat sweep mode 0 or repeat sweep mode 1.
4: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while
the A-D converter halts.
Fig. 8.2.2 Structure of A-D control register 0
(1) Analog input select bits (bits 2 to 0)
These bits are used to select an analog input pin in the one-shot mode and repeat mode. Pins which
are not selected as analog input pins function as programmable I/O ports.
These bits must be set again when the user switches the A-D operation mode to the one-shot mode
or repeat mode after performing the operation in the single sweep mode, repeat sweep mode 0 or
repeat sweep mode 1.
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A-D CONVERTER
8.2 Block description
(2) Trigger select bit (bit 5)
This bit is used to select the source of trigger occurrence. (Refer to “(3) A-D conversion start bit.”)
(3) A-D conversion start bit (bit 6)
● When internal trigger is selected
Setting this bit to “1” generates a trigger, causing the A-D converter to start operating. Clearing
this bit to “0” causes the A-D converter to stop operating.
In the one-shot mode or single sweep mode, this bit is cleared to “0” after the operation is
completed. In the repeat mode, repeat sweep mode 0 or repeat sweep mode 1, the A-D converter
continues operating until this bit is cleared to “0” by software.
● When external
trigger is selected
______
When the ADTRG pin level goes from “H” to “L” with this bit = “1,” a trigger occurs, causing the
A-D converter to start operating. The A-D converter stops when this bit is cleared to “0.”
In the one-shot mode or single sweep mode, this bit remains set to “1” even after the operation
is completed. In the repeat mode, repeat sweep mode 0 or repeat sweep mode 1, the A-D
converter continues operating until this bit is cleared to “0” by software.
(4) A-D conversion frequency (φ AD) select bit 0 (bit 7)
The operating time of the A-D converter varies depending on the selected operating clock (φ AD) by
this bit and the A-D conversion frequency (φ AD) select bit 1 (bit 4 at address 1F 16; refer to Figure
8.2.3) as listed in Table 8.2.3.
Since the A-D converter’s comparator consists of capacity coupling amplifiers, keep that φ AD ≥ 250
kHz during A-D conversion.
Table 8.2.1 Time for performance to one analog input pin (unit: µs)
Clock source for peripheral devices select bit
A-D conversion frequency (φAD) select bit 1
A-D conversion frequency (φAD) select bit 0
φAD
f(X IN) = 25 MHz
f(X IN) = 40 MHz
8-bit resolution
0
0
0
0
1
1
f4 divided by 4 f4 divided by 2
31.36
15.68
10-bit resolution
37.76
8-bit resolution
10-bit resolution
1
0
0
f4
0
7.84
0
1
f2 divided by 4 f2 divided by 2
15.68
7.84
1
0
f2
3.92
18.88
9.44
18.88
9.44
4.72
19.60
9.80
4.90
–––
–––
–––
23.60
11.80
5.90
–––
–––
–––
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A-D CONVERTER
8.2 Block description
8.2.2 A-D control register 1
Figure 8.2.3 shows the structure of the A-D control register 1.
The A-D operation mode select bit 1 is used to select the operation mode of the A-D converter. The 8/10bit mode select bit is used to select the resolution. Refer to Table 8.2.1 for the A-D conversion frequency
(φ AD) select bit 1.
b7
b6
b5
b4
b3
b2
b1
b0
A-D control register 1 (Address 1F16)
Bit
0
Bit name
A-D sweep pin select bits
(Valid in single sweep, repeat sweep
mode 0 and repeat sweep mode 1)
(Note 1)
Functions
●Single sweep mode/Repeat sweep
mode 0
RW
1
RW
1
RW
b1 b0
0 0 : AN 0, AN1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins) (Note 2)
●Repeat sweep mode 1 (Note 3)
1
At reset
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN 2 (3 pins)
1 1 : AN0 to AN 3 (4 pins)
2
A-D operation mode select bit 1
(Use in repeat sweep mode 0
and repeat sweep mode 1)
(Note 4)
0 : Repeat sweep mode 0
1 : Repeat sweep mode 1
0
RW
3
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0
RW
4
A-D conversion frequency
(φAD) select bit 1
Refer to A-D conversion frequency
(φAD ) select bit 0 (bit 7 at address
1E16) ; See Table 8.2.1
0
RW
Undefined
–
7 to 5
Nothing is assigned.
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or
“1.”)
2: When selecting an external trigger, the AN 7 pin cannot be used as an analog input
pin.
3: Analog input pins which are frequently A-D converted are selected in the repeat
sweep mode 1.
4: Fix this bit to “0” in the one-shot, repeat, and single sweep modes.
5: Writing to each bit of the A-D control register 1 must be performed while the A-D
converter halts.
Fig. 8.2.3 Structure of A-D control register 1
(1) A-D sweep pin selection bits (bits 1 and 0)
These bits are used to select analog input pins in the single sweep mode, repeat sweep mode 0 and
repeat sweep mode 1. In the single sweep mode and repeat sweep mode 0, pins which are not
selected as analog input pins function as programmable I/O ports.
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A-D CONVERTER
8.2 Block description
8.2.3 A-D register i (i = 0 to 7)
Figure 8.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conversion
result (contents of the successive approximation register) is stored into this register. Each A-D register i
corresponds to an analog input pin (AN i). Table 8.2.2 lists the correspondence of an analog input pin to
A-D register i.
●8-bit mode
(b15)
(b8)
b7
b0
b7
b0
A-D register 0 (Addresses 21 16, 2016)
A-D register 1 (Addresses 23 16, 2216)
A-D register 2 (Addresses 25 16, 2416)
A-D register 3 (Addresses 27 16, 2616)
A-D register 4 (Addresses 29 16, 2816)
A-D register 5 (Addresses 2B 16, 2A 16)
A-D register 6 (Addresses 2D 16, 2C 16)
A-D register 7 (Addresses 2F 16, 2E16)
Functions
Bit
7 to 0
Reads an A-D conversion result.
15 to 8 The value is “0” at reading.
●10-bit mode
(b15)
(b10)
(b8)
b7
b2
b0
b7
b0
At reset
RW
Undefined
RO
0
RO
At reset
RW
Undefined
RO
0
RO
A-D register 0 (Addresses 21 16, 2016)
A-D register 1 (Addresses 23 16, 2216)
A-D register 2 (Addresses 25 16, 2416)
A-D register 3 (Addresses 27 16, 2616)
A-D register 4 (Addresses 29 16, 2816)
A-D register 5 (Addresses 2B 16, 2A 16)
A-D register 6 (Addresses 2D 16, 2C 16)
A-D register 7 (Addresses 2F 16, 2E16)
Functions
Bit
9 to 0
Reads an A-D conversion result.
15 to 10 The value is “0” at reading.
Fig. 8.2.4 Structure of A-D register i
Table 8.2.2 Correspondence of analog input pin
and A-D register i
Analog input pin
A-D register i where
conversion result is stored
AN 0 pin
A-D register 0
AN 1 pin
A-D register 1
AN 2 pin
A-D register 2
AN 3 pin
AN 4 pin
A-D register 3
AN 5 pin
A-D register 5
AN 6 pin
A-D register 6
AN 7 pin
A-D register 7
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A-D register 4
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A-D CONVERTER
8.2 Block description
8.2.4 A-D conversion interrupt control register
Figure 8.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts,
refer to “Chapter 4. INTERRUPTS.”
b7
b6
b5
b4
b3
b2
b1
b0
A-D conversion interrupt control register (Address 7016)
Bit
Bit name
0
Interrupt priority level select bits
1
2
3
Interrupt request bit
7 to 4
Nothing is assigned.
Functions
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0 : No interrupt request
1 : Interrupt request
At reset
RW
0
RW
0
RW
0
RW
Undefined
(Note)
RW
Undefined
–
Note : Clear the bit 3 to “0” by software when using A-D conversion interrupt.
Fig. 8.2.5 Structure of A-D conversion interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select the A-D conversion interrupt’s priority level. When using A-D conversion interrupts,
select priority levels 1 to 7. When an A-D conversion interrupt request occurs, its priority level is
compared with the processor interrupt priority level (IPL) and the requested interrupt is enabled only
when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag
(I) = “0.”) To disable the A-D conversion interrupt, set these bits to “000 2” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when an A-D conversion interrupt request occurs. This bit is automatically
cleared to “0” when the A-D conversion interrupt request is accepted. This bit can be set to “1” or
cleared to “0” by software.
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A-D CONVERTER
8.2 Block description
8.2.5 Port P7 direction register
The A-D converter and port P7 use the same pins in common. When using these pins as the A-D converter’s
input pins, set the corresponding bits of the port P7 direction register to “0” to set these ports for the input
mode. Figure 8.2.6 shows the relationship between the port P7 direction register and A-D converter’s input
pins.
b7
b6
b5
b4
b3
b2
b1
b0
Port P7 direction register (Address 1116)
Bit
Corresponding pin
0
AN0 pin
1
AN1 pin
Functions
0 : Input mode
1 : Output mode
When using these pins as A-D
converter’s input pins, set the
corresponding bits to “0.”
At reset
RW
0
RW
0
RW
0
RW
0
RW
2
AN2 pin
3
AN3 pin
4
AN4 pin
0
RW
5
AN5 pin
0
RW
6
AN6 pin
0
RW
7
AN7/ADTRG pin
0
RW
Fig. 8.2.6 Relationship between port P7 direction register and A-D converter’s input pins
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A-D CONVERTER
8.3 A-D conversion method (successive approximation conversion method)
8.3 A-D conversion method (successive approximation conversion method)
The A-D converter compares the comparison voltage (V ref), which is internally generated according to the
contents of the successive approximation register, with the analog input voltage (VIN), which is input from
the analog input pin (ANi). By reflecting the comparison result on the successive approximation register, VIN
is converted into a digital value. When a trigger is generated, the A-D converter performs the following
processing:
➀
Determining bit 9 of the successive approximation register
The A-D converter compares Vref with VIN. At this point, the contents of the successive approximation
register are “10000000002” (initial value).
Bit 9 of the successive approximation register changes according to the comparison result as follows:
When V ref < V IN, bit 9 = “1”
When V ref > V IN, bit 9 = “0”
➁
Determining bit 8 of the successive approximation register
After setting bit 8 of the successive approximation register to “1,” the A-D converter compares V ref
with V IN. Bit 8 changes according to the comparison result as follows:
When V ref < V IN, bit 8 = “1”
When V ref > V IN, bit 8 = “0”
➂
Determining bits 7 to 0 of the successive approximation register
Operation in ➁ are performed for bits 7 to 0 in the 10-bit mode.
Operation in ➁ are performed for bits 7 to 2 in the 8-bit mode.
When the LSB is determined, the contents (conversion result) of the successive approximation register
are transferred to the A-D register i.
The comparison voltage (Vref) is generated according to the latest contents of the successive approximation
register. Table 8.3.1 lists the relationship between the successive approximation register’s contents and Vref.
Table 8.3.2 and Table 8.3.3 list changes of the successive approximation register and Vref during the A-D
conversion. Figure 8.3.1 shows the ideal A-D conversion characteristics in the 10-bit mode.
Table 8.3.1 Relationship between successive approximation register’s contents and V ref
Successive approximation register’s contents: n
V ref (V)
0
0
✽
VREF
✕ (n – 0.5)
1 to 1023
1024
VREF✽: Reference voltage
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A-D CONVERTER
8.3 A-D conversion method (successive approximation conversion method)
Table 8.3.2 Change in successive approximation register and V ref during A-D conversion in 8-bit
mode
Change of V ref
Successive approximation register
b9
b0
A-D converter halt
1 0 0 0 0 0 0 0 0 0
VREF [V]
2
1st comparison
1 0 0 0 0 0 0 0 0 0
VREF – VREF
[V]
2
2048
2nd comparison
n9 1 0 0 0 0 0 0 0 0
VREF ± VREF
VREF [V]
–
2
4
2048
•n9=0
•n9=1
1st comparison result
3rd comparison
n9 n8 1 0 0 0 0 0 0 0
2nd comparison result
+ VREF
4
– VREF
VREF ± VREF ± VREF
VREF [V]
8 – 2048
2
4
4
•n8=1
•n8=0
:
:
:
:
:
:
8th comparison
n9 n 8 n7 n 6 n 5 n 4 n 3 1 0 0
Conversion complete
n9 n 8 n7 n 6 n 5 n 4 n 3 n 2 0 0
VREF
+ 8
VREF
– 8
VREF ± VREF ± VREF ±...... ± VREF
REF [V]
– V
8
2
4
256
2048
Table 8.3.3 Change in successive approximation register and Vref during A-D conversion in 10-bit
mode
Change of V ref
Successive approximation register
b9
b0
A-D converter halt
1 0 0 0 0 0 0 0 0 0
VREF [V]
2
1st comparison
1 0 0 0 0 0 0 0 0 0
VREF – VREF
[V]
2
2048
2nd comparison
n9 1 0 0 0 0 0 0 0 0
VREF ± VREF
REF
[V]
– V
2
4
2048
•n9=0
•n9=1
1st comparison result
3rd comparison
n9 n8 1 0 0 0 0 0 0 0
2nd comparison result
:
:
:
:
10th comparison
n9 n8 n7 n6 n5 n4 n3 n2 n1 1
Conversion complete
n9 n8 n7 n6 n5 n4 n3 n2 n1 n0
+ VREF
VREF ± VREF ± VREF
VREF [V]
8 – 2048
2
4
:
:
4
– VREF
4
•n8=1
•n8=0
VREF
+ 8
VREF
– 8
VREF ± VREF ± VREF ±...... ± VREF
REF [V]
– V
8
2
4
1024
2048
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A-D CONVERTER
8.3 A-D conversion method (successive approximation conversion method)
A-D conversion result
ldeal A-D conversion characteristics
3FF16
3FE16
3FD16
003 16
002 16
001 16
000 16
0
VREF
1024 ✕1
VREF
1024 ✕2
VREF
1024 ✕3
VREF
VREF
VREF
1024 ✕1021 1024 ✕1022 1024 ✕1023
VREF
1024 ✕0.5
Analog input voltage
Fig. 8.3.1 Ideal A-D conversion characteristics in 10-bit mode
8–12
VREF
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A-D CONVERTER
8.4 Absolute accuracy and differential non-linearity error
8.4 Absolute accuracy and differential non-linearity error
8.4.1 Absolute accuracy
The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result
and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring
the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code
from an A-D converter with ideal characteristics. For example, in the case of the 10-bit mode, when
VREF=5.12 V, 1 LSB width is 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ... are selected as the analog
input voltages.
The absolute accuracy = ±3 LSB indicates that when the analog input voltage is 25 mV, the output code
expected from an ideal A-D conversion characteristics is “00516,” but the actual A-D conversion result is
between “00216” to “00816.”
The absolute accuracy includes the zero error and the full-scale error.
The absolute accuracy degrades when VREF is lowered. The output code for analog input voltages V REF to
AVCC is “3FF 16.”
Output code
(A-D conversion result)
00B16
00A16
00916
+3 LSB
00816
Ideal A-D conversion
characteristics
00716
00616
00516
00416
00316
00216
–3 LSB
00116
00016
0
5
10
15
20
25
30
35
40
45
50
55
Analog input voltage (mV)
Fig. 8.4.1 Absolute accuracy of A-D converter in 10-bit mode
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A-D CONVERTER
8.4 Absolute accuracy and differential non-linearity error
8.4.2 Differential non-linearity error
The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog
input voltage width while the same output code is expected to output) of an A-D converter with ideal
characteristics and the actual measured step width (the actual analog input voltage width while the same
output code is output). For example, in the case of the 10-bit mode, when V REF=5.12 V, the 1 LSB width
of an A-D converter with ideal characteristics is 5 mV, but if the differential non-linearity error is ±1 LSB,
the actual measured 1 LSB width is 0 to 10 mV.
Output code
(A-D conversion result)
00916
1 LSB width with ideal
A-D conversion characteristics
00816
00716
00616
00516
00416
00316
00216
00116
Differential non-linearity error
00016
0
5
10
15
20
25
30
35
Analog input voltage (mV)
Fig. 8.4.2 Differential non-linearity error in 10-bit mode
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40
45
A-D CONVERTER
8.5 Comparison voltage in 8-bit mode
8.5 Comparison voltage in 8-bit mode
In the 8-bit mode, the M37751 treats the high-order 8 bits of the 10-bit successive approximation register
as the conversion result. Accordingly, when compared with the 8-bit A-D converter, the A-D conversion of
the M37751 is performed by using a comparison reference voltage that is different by 3V REF/2048 (refer to
the underlined portions in the Table 8.5.1). The difference of the output code change point is generated as
shown in Figure 8.5.1.
Table 8.5.1 Comparison reference voltage of the M37751’s 8-bit mode and 8-bit A-D converter
Comparison reference
voltage V ref
M37751’s 8-bit mode
8-bit A-D converter
V REF/2 8 ✕ n — V REF/2 10 ✕ 0.5
VREF /2 8 ✕ n — V REF /2 8 ✕ 0.5
VREF: Reference voltage
n : Contents of successive approximation register
●8-bit A-D converter with ideal characteristics (In the case of VREF = 5.12 V)
Output code
(A-D conversion result)
02
01
00
10
30
Analog input voltage (mV)
●M37751’s A-D converter with ideal characteristics (In the case of VREF = 5.12 V)
Output code
(A-D conversion result)
8-bit mode 10-bit mode
02
01
00
09
08
07
06
05
04
03
02
01
00
10-bit mode
8-bit mode
(Note)
(Note)
17.5
37.5
Analog input voltage (mV)
Note: Difference from output code change point
VREF: Reference voltage
Fig. 8.5.1 Difference of output code change point
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A-D CONVERTER
8.6 One-shot mode
8.6 One-shot mode
In the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed
once, and an A-D conversion interrupt request occurs when the operation is completed.
8.6.1 Settings for one-shot mode
Figure 8.6.1 shows an initial setting example of the one-shot mode.
When using an interrupt, it is necessary to set the corresponding register to enable interrupts. Refer to
“Chapter 4. INTERRUPTS” for more descriptions.
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A-D CONVERTER
8.6 One-shot mode
●A-D control register 0 and A-D control register 1
b7
b0
0
0 0
b7
A-D control register 0 (address 1E16)
b0
0 ✕ ✕ A-D control register 1 (address 1F 16)
Analog input select bits
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AN 0 selected
1 : AN 1 selected
0 : AN 2 selected
1 : AN 3 selected
0 : AN 4 selected
1 : AN 5 selected
0 : AN 6 selected
1 : AN 7 selected
A-D conversion frequency ( φAD)
select bit 1
Refer to A-D conversion frequency
(φAD) select bit 0.
One-shot mode
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0 : Stop A-D conversion
A-D conversion frequency ( φAD) select bit 0
A-D conversion frequency ( φAD) select bit 1 = “0”
0 : f 2/f4 divided by 4
1 : f 2/f4 divided by 2
A-D conversion frequency ( φAD) select bit 1 = “1”
0 : f 2/f4
1 : Not selected
✕ : “0” or “1”
●Interrupt priority level
b7
b0
0
A-D conversion interrupt control register (address 7016)
Interrupt priority level select bits
Set to a level between 1 to 7 when using this interrupt.
Set to a level 0 when disabling this interrupt.
Interrupt request bit
“0” : No interrupt request
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
●Set A-D conversion start bit to “1”
b7
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
b0
A-D control register 0 (address 1E16)
1
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
A-D conversion start bit
Selecting external trigger
Selecting internal trigger
Input falling edge to
ADTRG pin
Trigger occur
Operation start
Note: Write the following registers when the A-D conversion stops (before trigger occurs).
• Each bit of A-D control register 0 (except bit 6)
• Each bit of A-D control register 1
Fig. 8.6.1 Initial setting example of one-shot mode
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A-D CONVERTER
8.6 One-shot mode
8.6.2 One-shot mode operation description
(1) When an internal trigger is selected
➀ The A-D converter starts operation when the A-D conversion start bit is set to “1.”
➁ The A-D conversion is completed after 49 cycles of φ AD in the 8-bit mode, or 59 cycles of φ AD in
the 10-bit mode. Then, the contents of the successive approximation register (conversion result) are
transferred to the A-D register i.
➂ At the same time as step ➁, the A-D conversion interrupt request bit is set to “1.”
➃ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation.
(2) When an external trigger is selected
______
➀ The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L”
while the A-D conversion start bit is “1.”
➁ The A-D conversion is completed after 49 cycles of φ AD in the 8-bit mode, or 59 cycles of φ AD in
the 10-bit mode. Then, the contents of the successive approximation register (conversion result) are
transferred to the A-D register i.
➂ At the same time as step ➁, the A-D conversion interrupt request bit is set to “1.”
➃ The A-D conversion stops operation.
The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly,
the
______
operation of the A-D converter can be performed again from step ➀ when the level of the ADTRG
pin changes from “H”______
to “L.”
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 8.6.2 shows the conversion operation in the one-shot mode.
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A-D CONVERTER
8.6 One-shot mode
Trigger occur
Conversion result
Convert input voltage from
ANi pin
A-D register i
A-D converter interrupt
request occur
A-D converter halt
Fig. 8.6.2 Conversion operation in one-shot mode
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A-D CONVERTER
8.7 Repeat mode
8.7 Repeat mode
In the repeat mode, the operation for the input voltage from the one selected analog input pin is performed
repeatedly.
In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at
address 1E 16 ) remains set to “1” until it is cleared to “0” by software, and the operation is performed
repeatedly while the A-D conversion start bit is “1.”
8.7.1 Settings for repeat mode
Figure 8.7.1 shows an initial setting example of repeat mode.
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A-D CONVERTER
8.7 Repeat mode
●A-D control register 0 and A-D control register 1
b7
b0
0
0 1
b7
b0
0 ✕ ✕ A-D control register 1 (address 1F16)
A-D control register 0 (address 1E16)
Analog input select bits
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AN 0 selected
1 : AN 1 selected
0 : AN 2 selected
1 : AN 3 selected
0 : AN 4 selected
1 : AN 5 selected
0 : AN 6 selected
1 : AN 7 selected
A-D conversion frequency ( φAD)
select bit 1
Refer to A-D conversion frequency
(φAD) select bit 0.
Repeat mode
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0: Stop A-D conversion
A-D conversion frequency ( φAD) select bit 0
A-D conversion frequency ( φAD) select bit 1 = “0”
0 : f 2/f4 divided by 4
1 : f 2/f4 divided by 2
A-D conversion frequency ( φAD) select bit 1 = “1”
0 : f 2/f4
1 : Not selected
✕ : “0” or “1”
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
●Set A-D conversion start bit to “1”
b7
b0
1
A-D control register 0 (address 1E 16)
A-D conversion start bit
Selecting external trigger
Input falling edge to
ADTRG pin
Selecting internal trigger
Trigger occur
Operation start
Note: Write the following registers when the A-D conversion stops (before trigger occurs).
• Each bit of A-D control register 0 (except bit 6)
• Each bit of A-D control register 1
Fig. 8.7.1 Initial setting example of repeat mode
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A-D CONVERTER
8.7 Repeat mode
8.7.2 Repeat mode operation description
(1) When an internal trigger is selected
➀ The A-D converter starts operation when the A-D conversion start bit is set to “1.”
➁ The first A-D conversion is completed after 49 cycles of φ AD in the 8-bit mode, or 59 cycles of φAD
in the 10-bit mode. Then, the contents of the successive approximation register (conversion result)
are transferred to the A-D register i.
➂ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software.
The conversion result is transferred to the A-D register i each time the conversion is completed.
(2) When an external trigger is selected
______
➀ The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L”
while the A-D conversion start bit is “1.”
➁ The first A-D conversion is completed after 49 cycles of φ AD in the 8-bit mode, or 59 cycles of φAD
in the 10-bit mode. Then, the contents of the successive approximation register (conversion result)
are transferred to the A-D register i.
➂ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software.
The conversion result is transferred to the A-D register i each time the conversion is completed.
When the comparator function is selected, the comparison result is stored in the ANi pin comparator
result bit each time the comparison is completed.
______
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 8.7.2 shows the conversion operation in the repeat mode.
Trigger occur
Conversion result
Convert input voltage from
ANi pin
Fig. 8.7.2 Conversion operation in repeat mode
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A-D register i
A-D CONVERTER
8.8 Single sweep mode
8.8 Single sweep mode
In the single sweep mode, the operation for the input voltage from multiple selected analog input pins is
performed, one at a time. The A-D converter is operated in ascending sequence from the AN 0 pin. An
A-D conversion interrupt request occurs when the operation for all selected input pins are completed.
8.8.1 Settings for single sweep mode
Figure 8.8.1 shows an initial setting example of single sweep mode.
When using an interrupt, it is necessary to set the corresponding register to enable interrupts. Refer to
“Chapter 4. INTERRUPTS” for more information.
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A-D CONVERTER
8.8 Single sweep mode
●A-D control register 0 and A-D control register 1
b7
b0
0
b7
b0
1 0 ✕ ✕ ✕ A-D control register 0 (address 1E16)
0
A-D control register 1 (address 1F 16)
A-D sweep pin select bits
Single sweep mode
b1 b0
0
0
1
1
Trigger select bit
0 : Internal trigger
1 : External trigger
0 : AN 0, AN1 (2 pins)
1 : AN 0 to AN 3 (4 pins)
0 : AN 0 to AN 5 (6 pins)
1 : AN 0 to AN 7 (8 pins)
A-D conversion start bit
0: Stop A-D conversion
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
A-D conversion frequency ( φAD) select bit 0
A-D conversion frequency ( φAD) select bit 1 = “0”
0 : f 2/f4 divided by 4
1 : f 2/f4 divided by 2
A-D conversion frequency ( φAD) select bit 1 = “1”
0 : f 2/f4
1 : Not selected
A-D conversion frequency ( φAD)
select bit 1
Refer to A-D conversion frequency
(φAD) select bit 0.
✕ : “0” or “1”
●Interrupt priority level
b7
b0
0
A-D conversion interrupt control register (address 7016)
Interrupt priority level select bits
Set to a level between 1 to 7 when using this interrupt.
Set to a level 0 when disabling this interrupt.
Interrupt request bit
“0” : No interrupt request
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
●Set A-D conversion start bit to “1”
b7
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
b0
1
A-D control register 0 (address 1E16)
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
A-D conversion start bit
Selecting external trigger
Selecting internal trigger
Trigger occur
Operation start
Note: Write the following registers when the A-D conversion stops (before trigger occurs).
• Each bit of A-D control register 0 (except bit 6)
• Each bit of A-D control register 1
Fig. 8.8.1 Initial setting example of single sweep mode
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Input falling edge to
ADTRG pin
A-D CONVERTER
8.8 Single sweep mode
8.8.2 Single sweep mode operation description
(1) When an internal trigger is selected
➀ The A-D converter starts conversion for the input voltage from the AN0 pin starts when the A-D
conversion start bit is set to “1.”
➁ The A-D conversion of the input voltage from the AN 0 pin is completed after 49 cycles of φ AD in
the 8-bit mode, or 59 cycles of φ AD in the 10-bit mode. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register 0.
➂ The operation to all selected analog input pins is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ When the step ➂ is completed, the A-D conversion interrupt request bit is set to “1.”
➄ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation.
(2) When an external trigger is selected
➀ The ______
A-D converter starts conversion for the input voltage from the AN0 pin when the input level to
the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.”
➁ The A-D conversion of the input voltage from the AN 0 pin is completed after 49 cycles of φ AD in
the 8-bit mode, or 59 cycles of φ AD in the 10-bit mode. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register 0.
➂ The operation to all selected analog input pins is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ When the step ➂ is completed, the A-D conversion interrupt request bit is set to “1.”
➄ The A-D conversion stops operation.
The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly,
the
______
operation of the A-D converter can be performed again from step ➀ when the level of the ADTRG
pin changes from “H”______
to “L.”
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 8.8.2 shows the conversion operation in the single sweep mode.
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A-D CONVERTER
8.8 Single sweep mode
Trigger occur
Convert input voltage from
AN0 pin
Conversion result
Convert input voltage from
AN1 pin
Conversion result
Convert input voltage from
ANi pin
Conversion result
A-D register 0
A-D register 1
A-D register i
A-D converter interrupt
request occur
A-D converter halt
Fig. 8.8.2 Conversion operation in single sweep mode
8–26
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A-D CONVERTER
8.9 Repeat sweep mode 0
8.9 Repeat sweep mode 0
In the repeat sweep mode 0, the operation for the input voltage from the multiple selected analog input pins
is performed repeatedly. The A-D converter is operated in ascending sequence from the AN 0 pin.
In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at
address 1E 16) remains set to “1” until it is cleared to “0” by software, and the operation is performed
repeatedly while the A-D conversion start bit is “1.”
8.9.1 Settings for repeat sweep mode 0
Figure 8.9.1 shows an initial setting example of repeat sweep mode 0.
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A-D CONVERTER
8.9 Repeat sweep mode 0
●A-D control register 0 and A-D control register 1
b7
b0
0
b7
b0
0
1 1 ✕ ✕ ✕ A-D control register 0 (address 1E16)
A-D control register 1 (address 1F16)
A-D sweep pin select bits
Repeat sweep mode 0
b1 b0
0
0
1
1
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0: Stop A-D conversion
0 : AN 0, AN1 (2 pins)
1 : AN 0 to AN 3 (4 pins)
0 : AN 0 to AN 5 (6 pins)
1 : AN 0 to AN 7 (8 pins)
Repeat sweep mode 0
A-D conversion frequency ( φAD) select bit 0
A-D conversion frequency ( φAD) select bit 1 = “0”
0 : f 2/f4 divided by 4
1 : f 2/f4 divided by 2
A-D conversion frequency ( φAD) select bit 1 = “1”
0 : f 2/f4
1 : Not selected
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
A-D conversion frequency ( φAD)
select bit 1
Refer to A-D conversion frequency
(φAD) select bit 1.
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Set the bits corresponding
to analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
●Set A-D conversion start bit to “1”
b7
b0
1
A-D control register 0 (address 1E16)
A-D conversion start bit
Selecting external trigger
Selecting internal trigger
Input falling edge to
ADTRG pin
Trigger occur
Operation start
Note: Write the following registers when the A-D conversion stops (before trigger occurs).
• Each bit of A-D control register 0 (except bit 6)
• Each bit of A-D control register 1
Fig. 8.9.1 Initial setting example of repeat sweep mode 0
8–28
7751 Group User’s Manual
✕ : “0” or “1”
A-D CONVERTER
8.9 Repeat sweep mode 0
8.9.2 Repeat sweep mode 0 operation description
(1) When an internal trigger is selected
➀ The A-D converter starts conversion for the input voltage from the AN0 pin starts when the A-D
conversion start bit is set to “1.”
➁ The A-D conversion of the input voltage from the AN 0 pin is completed after 49 cycles of φ AD in
the 8-bit mode, or 59 cycles of φ AD in the 10-bit mode. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register 0.
➂ The operation to all selected analog input pins is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ The operation to all selected analog input pins is performed again.
➄ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software.
(2) When an external trigger is selected
➀ The ______
A-D converter starts conversion for the input voltage from the AN0 pin when the input level to
the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.”
➁ The A-D conversion of the input voltage from the AN 0 pin is completed after 49 cycles of φ AD in
the 8-bit mode, or 59 cycles of φ AD in the 10-bit mode. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register 0.
➂ The operation to all selected analog input pins is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ The operation to all selected analog input pins is performed again.
➄ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software.
______
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
Figure 8.9.2 shows the conversion operation in the repeat sweep mode 0.
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A-D CONVERTER
8.9 Repeat sweep mode 0
Trigger occur
Conversion result
Convert input voltage from
AN0 pin
A-D register 0
Conversion result
Convert input voltage from
AN1 pin
Convert input voltage from
ANi pin
A-D register 1
Conversion result
Fig. 8.9.2 Conversion operation in repeat sweep mode 0
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A-D register i
A-D CONVERTER
8.10 Repeat sweep mode 1
8.10 Repeat sweep mode 1
In the repeat sweep mode 1, the operation for the input voltage from all selected analog input pins is
performed repeatedly.
In this mode, analog input pins are separated into two groups according to the frequency of use. One is the
group for more frequencies of use. The other is the group for few frequencies of use. First, the operations
to all analog input pins in the group of more frequencies of use are performed. Next, the operation to one
of analog input pins in the group of fewer frequencies of use is operated.
Figure 8.10.1 shows the analog input pin sweep operation. As shown in Figure 8.10.1, the pin to be
executed in the group of fewer frequencies changes sequently.
In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at
address 1E 16) remains set to “1” until it is cleared to “0” by software, and the operation is performed
repeatedly while the A-D conversion start bit is “1.”
8.10.1 Settings for repeat sweep mode 1
Figure 8.10.2 shows an initial setting example of repeat sweep mode 1.
Select the analog input pins in the group of more frequencies of use by the A-D sweep pin select bits (bits
1 and 0 at address 1F16). Pins which are not selected by the A-D sweep pin select bits belong to the group
of fewer frequencies of use.
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A-D CONVERTER
8.10 Repeat sweep mode 1
● A-D sweep pin select bit: bits 1, 0 at address 1F16 = “002”
(Group of more frequencies of use: AN0 pin)
AN0 → AN1 → AN0 → AN2 → AN0 → AN3 → AN0 → AN4 → AN0 → AN5 → AN0 → AN6 → AN0
→ AN7 → AN0 → AN1 → AN0 → AN2 → .........
● A-D sweep pin select bit: bits 1, 0 at address 1F16 = “012”
(Group of more frequencies of use: pins AN0 and AN1 )
AN0
AN0
AN0
AN1
→ AN6 →
AN0
AN1
→ AN7 →
AN0
→
AN1
→ AN5 →
→
AN1
→ AN4 →
→
AN1
AN0
→
AN0
→
→ AN2 →
AN1
→ AN3 →
→
AN1
AN0
→
→
→ AN2 →
AN1
→ AN3 → .........
● A-D sweep pin select bit: bits 1, 0 at address 1F16 = “102”
(Group of more frequencies of use: pins AN0–AN2 )
AN0
AN0
AN0
AN0
AN0
AN0
→
→
→
→
→
→
→
AN0
→
→
→
→
→
→
→
AN1 → AN3 → AN1 → AN4 → AN1 → AN5 → AN1 → AN6 → AN1 → AN7 → AN1 → AN3 → AN1
AN2
AN2
AN2
AN2
AN2
AN2
AN2
→ AN4 → .........
● A-D sweep pin select bit: bits 1, 0 at address 1F16 = “112”
(Group of more frequencies of use: pins AN0–AN3 )
AN0
AN0
→
AN1
AN1
→ AN4 →
AN2
AN2
AN2
AN2
AN2
AN2
AN3
AN3
AN3
AN3
AN3
AN3
→ : This symbol expresses the order of performance
: Group of more frequencies of use
Fig. 8.10.1 Analog input pin sweep operation in repeat sweep mode 1
8–32
AN1
→ →
→ AN7 →
→ →
→ →
→ AN6 →
→
AN1
→ →
→ AN5 →
AN0
→
AN1
AN0
→
→ AN4 →
→ →
→ →
AN1
AN0
→
→
AN0
7751 Group User’s Manual
→ AN5 → .........
A-D CONVERTER
8.10 Repeat sweep mode 1
●A-D control register 0 and A-D control register 1
b7
b0
0
b7
1 1 ✕ ✕ ✕ A-D control register 0 (address 1E16)
b0
1
A-D control register 1 (address 1F 16)
A-D sweep pin select bits
Repeat sweep mode 1
b1 b0
0
0
1
1
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0: Stop A-D conversion
0 : AN 0 (1 pin)
1 : AN 0, AN1 (2 pins)
0 : AN 0 to AN 2 (3 pins)
1 : AN 0 to AN 3 (4 pins)
Repeat sweep mode 1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
A-D conversion frequency ( φAD) select bit 0
A-D conversion frequency ( φAD) select bit 1 = “0”
0 : f 2/f4 divided by 4
1 : f 2/f4 divided by 2
A-D conversion frequency ( φAD) select bit 1 = “1”
0 : f 2/f4
1 : Not selected
A-D conversion frequency ( φAD)
select bit 1
Refer to A-D conversion frequency
(φAD) select bit 0.
✕ : “0” or “1”
●Port P7 direction register
b7
b0
Port P7 direction register (address 1116)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Set the bits corresponding to
analog input pins to “0.”
Set bit 7 to “0” when
selecting external trigger.
●Set A-D conversion start bit to “1”
b7
b0
1
A-D control register 0 (address 1E16)
A-D conversion start bit
Selecting external trigger
Selecting internal trigger
Input falling edge to
ADTRG pin
Trigger occur
Operation start
Note: Write the following registers when the A-D conversion stops (before trigger occurs).
• Each bit of A-D control register 0 (except bit 6)
• Each bit of A-D control register 1
Fig. 8.10.2 Initial setting example of repeat sweep mode 1
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A-D CONVERTER
8.10 Repeat sweep mode 1
8.10.2 Repeat sweep mode 1 operation description
(1) When an internal trigger is selected
➀ The A-D converter starts conversion for the input voltage from the AN0 pin when the A-D conversion
start bit is set to “1.”
➁ The A-D conversion of the input voltage from the AN 0 pin is completed after 49 cycles of φ AD in
the 8-bit mode, or 59 cycles of φ AD in the 10-bit mode. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register 0.
➂ The operations to all analog input pins in the group of more frequencies of use are performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ The operation to one (refer to Figure 8.10.1) of analog input pins in the group of fewer frequencies
of use is performed.
➄ The operations to all analog input pins in the group of more frequencies of use are performed again.
➅ The operation to another one, which is different from the one selected in step ➃, of analog input
pins in the group of fewer frequencies of use is performed. (Refer to Figure 8.10.1.)
➆ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software.
(2) When an external trigger is selected
➀ The______
A-D converter starts conversion for the input voltage from the AN0 pin when the input level to
the AD TRG pin changes from “H” to “L” while the A-D conversion start bit is set to “1.”
➁ The A-D conversion of the input voltage from the AN0 pin is completed after 49 cycles of φ AD in
the 8-bit mode, or 59 cycles of φ AD in the 10-bit mode. Then, the contents of the successive
approximation register (conversion result) are transferred to the A-D register 0.
➂ The operations to all analog input pins in the group of more frequencies of use are performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
➃ The operation to one (refer to Figure 8.10.1) of analog input pins in the group of fewer frequencies
of use is performed.
➄ The operations to all analog input pins in the group of more frequencies of use are performed again.
➅ The operation to another one, which is different from the one selected in step ➃, of analog input
pins in the group of fewer frequencies of use is performed. (Refer to Figure 8.10.1.)
➆ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software.
______
When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point
is cancelled and is restarted from step ➀.
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A-D CONVERTER
[Precautions when using A-D converter]
[Precautions when using A-D converter]
1. Write to the following bits and registers before a trigger occurs (while the A-D converter stops operation).
• A-D control register 0 (except bit 6)
• A-D control register 1
______
2. When an external______
trigger is selected, the AN7 / AD TRG pin cannot be used as the analog input pin. It is
because the AN7/ADTRG pin is not connected to the comparator. When an external trigger is selected and
the AN 7 pin is selected as the analog input pin, the A-D converter is operated and the A-D register 7
contains an undefined value.
3. Refer to “Appendix.8 Examples of noise immunity improvement” when using the A-D converter.
7751 Group User’s Manual
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A-D CONVERTER
[Precautions when using A-D converter]
MEMORANDUM
8–36
7751 Group User’s Manual
CHAPTER 9
WATCHDOG TIMER
9.1 Block description
9.2 Operation description
9.3 Precautions when using watchdog timer
WATCHDOG TIMER
9.1 Block description
This chapter describes Watchdog timer.
Watchdog timer has the following functions:
● Detection of a program runaway.
● Measurement of a certain time when oscillation starts owing to terminating Stop mode.
(Refer to “Chapter 10. STOP MODE.”)
9.1 Block description
Figure 9.1.1 shows the block diagram of the watchdog timer.
Watchdog timer
frequency select bit
f2/f4
Wf32/Wf64
1/16
Hold request
Wf512/Wf1024
1/16
Watchdog timer
“FFF16”
is set.
Writing to watchdog timer
register (address 6016)
RESET
STP instruction
2Vcc
detection
circuit
S
Q
R
Fig. 9.1.1 Block diagram of watchdog timer
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7751 Group User’s Manual
Watchdog timer
interrupt request
WATCHDOG TIMER
9.1 Block description
9.1.1 Watchdog timer
Watchdog timer is a 12-bit counter that down-counts the count source which is selected with the watchdog
timer frequency select bit (bit 0 at address 61 16). A value “FFF 16” is automatically set in Watchdog timer
in the cases listed below. An arbitrary value cannot be set to Watchdog timer.
●
●
●
●
When dummy data is written to the watchdog timer register (Refer to Figure 9.1.2.)
When the most significant bit of Watchdog timer becomes “0”
When the STP instruction is executed (Refer to “Chapter 10. STOP MODE.”)
At reset
b7
b0
Watchdog timer register (Address 6016)
Bit
7 to 0
Functions
Initializes the watchdog timer.
When a dummy data is written to this register, the watchdog
timer’s value is initialized to “FFF16.” (Dummy data: 0016 to FF16)
At reset
RW
Undefined
–
Fig. 9.1.2 Structure of watchdog timer register
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9–3
WATCHDOG TIMER
9.1 Block description
9.1.2 Watchdog timer frequency select register
This is used to select the watchdog timer’s count source. Figure 9.1.3 shows the structure of the watchdog
timer frequency select register.
b7
b6
b5
b4
b3
b2
b1
b0
Watchdog timer frequency select register (Address 6116)
Bit
0
7 to 1
Bit name
Watchdog timer frequency select 0 : Wf512/Wf1024
bit
1 : Wf32/Wf64
Nothing is assigned.
Fig. 9.1.3 Structure of watchdog timer frequency select register
9–4
Functions
7751 Group User’s Manual
At reset
RW
0
RW
Undefined
–
WATCHDOG TIMER
9.2 Operation description
9.2 Operation description
The operation of Watchdog timer is described below.
9.2.1 Basic operation
➀ Watchdog timer starts down-counting from “FFF16.”
➁ When the Watchdog timer’s most significant bit becomes “0” (counted 2048 times), the watchdog timer
interrupt request occurs. (Refer to Table 9.2.1.)
➂ When the interrupt request occurs at above ➁, a value “FFF 16” is set to Watchdog timer.
The watchdog timer interrupt is a nonmaskable interrupt. When the watchdog timer interrupt request is
accepted, the processor interrupt priority level (IPL) is set to “1112.”
Table 9.2.1 Occurrence interval of watchdog timer interrupt request
Watchdog timer
frequency
select bit
0
f(X IN) = 25 MHz
f(X IN) = 40 MHz
Clock source for peripheral
Clock
source for peripheral
Clock source for peripheral
devices select bit = “0”
devices select bit = “0”
devices select bit = “1”
Count source Occurrence interval Count source Occurrence interval Count source Occurrence interval
41.94 ms
Wf1024
Wf 512
52.43 ms
83.89 ms
Wf1024
2.62 ms
Wf32
5.24 ms
Wf 64
1
Clock source for peripheral devices select bit : bit 2 at address 5F 16
7751 Group User’s Manual
Wf 64
3.28 ms
9–5
WATCHDOG TIMER
9.2 Operation description
(1) Example of program runaway detection
Write to the address 6016 (watchdog timer register) before the most significant bit of Watchdog timer
becomes “0.” In the case that Watchdog timer is used to detect a program runaway, if writing to
address 60 16 is not performed owing to a program runaway, the watchdog timer interrupt request
occurs when the most significant bit of Watchdog timer becomes “0.” It means that a program
runaway has occurred.
To reset the microcomputer after a program runaway, write “1” to the software reset bit (bit 3 at
address 5E 16) in the watchdog timer interrupt routine.
Main routine
Watchdog timer register
(Address 6016)
8-bit dummy data
Watchdog timer initialized
Value of watchdog timer :
“FFF16” (Note 1)
Watchdog timer
interrupt request occur
(program runaway detected)
Watchdog timer interrupt routine
Software reset bit
(Address 5E16, b3)
“1” (Note 2)
Reset microcomputer
RTI
Notes 1: Initialize (write to address 6016) Watchdog timer before the most significant bit of
Watchdog timer becomes “0” (the watchdog timer interrupt request occurs).
2: When the program runaway occurs, values of the data bank register (DT) and direct
page register (DPR) may be changed. When “1” is written to the software reset bit by
the addressing mode using DT and DPR, set values to DT and DPR again.
Fig. 9.2.1 Example of program runaway detection by Watchdog timer
9–6
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WATCHDOG TIMER
9.2 Operation description
9.2.2 Operation in Stop mode
In Stop mode, Watchdog timer stops operating. Immediately after Stop mode is terminated, Watchdog timer
operates as follows.
(1) When Stop mode is terminated by a hardware reset
Supply of the φ CPU and φBIU starts immediately after Stop mode is terminated, and the microcomputer
performs the “operation after a reset.” (Refer to “Chapter 13. RESET.”) The watchdog timer frequency
select bit becomes “0,” and Watchdog timer starts counting of Wf 1024 from “FFF 16.”
(2) When Stop mode is terminated by an interrupt request occurrence
Immediately after Stop mode is terminated, Watchdog timer starts counting of the count source Wf32/
Wf 64 from “FFF16.” Supply of the φ CPU and φ BIU starts when the Watchdog timer’s most significant bit
becomes “0.” (At this time, the watchdog timer interrupt request does not occur.)
Supply of the φ CPU and φBIU starts immediately after Stop mode is terminated, and the microcomputer
executes the routine of the interrupt which is used to terminate Stop mode. Watchdog timer restarts
counting of the count source (Note) from “FFF 16.”
Note: Clock Wf 32/Wf64 or Wf512/Wf 1024 which was counted just before executing the STP instruction.
9.2.3 Operation in Hold state
Watchdog timer stops operating in Hold state. When Hold state✽ is terminated, Watchdog timer restarts
counting in the same state where it stopped operating.
Hold state✽: Refer to section “12.4 Hold function.”
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WATCHDOG TIMER
9.3 Precautions when using watchdog timer
9.3 Precautions when using watchdog timer
1. When a dummy data is written to address 6016 with the 16-bit data length, writing to address 61 16 is
simultaneously performed. Accordingly, when the user does not want to change a value of the watchdog
timer frequency select bit (bit 0 at address 6116), write the previous value to the bit simultaneously with
writing to address 6016.
2. When the STP instruction (refer to “Chapter 10. STOP MODE”) is executed, Watchdog timer stops.
When Watchdog timer is used to detect the program runaway, select “STP instruction disable” with mask
option.
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CHAPTER 10
STOP MODE
10.1 Clock generating circuit
10.2 Operation description
10.3 Precautions for Stop mode
STOP MODE
10.1 Clock generating circuit
This chapter describes Stop mode.
Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU).
The microcomputer enters Stop mode when the STP instruction is executed.
Stop mode can be terminated by an interrupt request occurrence or the hardware reset.
10.1 Clock generating circuit
Figure 10.1.1 shows the clock generating circuit.
XIN
Interrupt request
XOUT
1/2
S Q
f2/f4
1 Clock source for
f16/f32
peripheral devices
select bit
1/2
0
f64/f128
1/8
1/4
1
STP instruction
R
1/16
Hold request
1/16
Reset
1/8
Operation clock for
internal peripheral devices
f512/f1024
Wf32/Wf64
Wf512/Wf1024
1
Watchdog
timer
0
Watchdog timer frequency
select bit
S Q
(Note)
R
S Q
WIT instruction
BIU
Ready request
Request of CPU wait
from BIU
CPU
R
Clock source for peripheral devices select bit : Bit 2 at address 5F16
Watchdog timer frequency select bit : Bit 0 at address 6116
CPU : Central processing unit
BIU : Bus interface unit
Note: This is the signal generated when the watchdog timer’s most significant bit becomes “0.”
Fig. 10.1.1 Clock generating circuit
10–2
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STOP MODE
10.2 Operation description
10.2 Operation description
When the STP instruction is executed, the oscillator stops oscillating. This state is called “Stop mode.”
In Stop mode, the contents of the internal RAM can be retained intact when the Vcc, power source voltage,
is 2 V or more. Additionally, the microcomputer’s power consumption is reduced. It is because the CPU and
all internal peripheral devices using clocks f2/f 4 to f 512/f 1024 stop the operation.
Table 10.2.1 lists the microcomputer state and operation in and after Stop mode.
Table 10.2.1 Microcomputer state and operation in and after Stop mode
Item
State and Operation
State in
Stopped
Oscillation
Stop mode
φ CPU, φ BIU, φ, clock φ 1,
devices
Internal peripheral
f 2 /f 4 to f 512 /f 1024, Wf 32/Wf 64,
Wf 512/Wf1024
Timer A
Operating enabled only in event counter mode
Timer B
Serial I/O
Operating enabled only when selecting external clock
A-D converter
Stopped
Watchdog timer
Pins
Operation
By interrupt request
after terminating occurrence
Stop mode
By hardware reset
Retains the same state in which the STP instruction was executed
Supply of φ CPU and φ BIU starts after a certain time measured by
watchdog timer has passed.
Operates in the same way as hardware reset
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10–3
STOP MODE
10.2 Operation description
10.2.1 Termination by interrupt request occurrence
When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time
measured by the watchdog timer has passed.
➀ When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of φ, clock φ1,
f 2/f4 to f 512/f 1024, Wf 32/Wf 64, and Wf 512/Wf1024 starts.
➁ The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts Wf32/Wf64.
➂ When the watchdog timer’s MSB becomes “0,” supply of φCPU, φBIU starts. At the same time, the watchdog
timer’s count source returns to Wf32/Wf64 or Wf512/Wf1024 that is selected by the watchdog timer frequency
select bit (bit 0 at address 61 16).
➃ The interrupt request which occurs in ➀ is accepted.
Table 10.2.2 lists the interrupts used to terminate Stop mode.
Table 10.2.2 Interrupts used to terminate Stop mode
Interrupt
Conditions for using each function to generate interrupt request
____
INT i interrupt (i = 0 to 2)
Timer Ai interrupt (i = 0 to 4)
Enabled in event counter mode
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
Enabled when selecting external clock
UARTi receive interrupt (i = 0, 1)
Notes 1: Since the oscillator has stopped oscillating, each function does not work unless they are operated
under the above condition. Also, the A-D converter does not work.
2: Since the oscillator has stopped oscillating, no interrupts other than those above can be used.
3: Refer to “Chapter 4. INTERRUPT” and the description of each internal peripheral device for
details about each interrupt.
Before executing the STP instruction, enable interrupts used to terminate Stop mode.
In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the
processor interrupt priority level (IPL) of the routine where the STP instruction is executed. When multiple
interrupts in Table 10.2.2 are enabled, Stop mode is terminated by the first interrupt request.
There is possibility that all interrupt requests occur after the oscillation starts in ➀ and until supply of φ CPU
and φ BIU starts in ➂. The interrupt requests which occur during this time are accepted in order of priority
(Note) after the watchdog timer’s MSB becomes “0.”
For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before
executing the STP instruction.
Note : The interrupt request which has the highest priority is accepted first.
10–4
7751 Group User’s Manual
STOP MODE
10.2 Operation description
Stop mode
f(XIN)
C PU ,
.......
BIU
Interrupt request
used to terminate
Stop mode
(Interrupt request bit)
“1”
“0”
Wf32/Wf64 ✕ 2048 counts
“FFF16”
Value of watchdog timer
“7FF16”
C PU
Operating
Stopped
Stopped
Operating
Internal peripheral devices
Operating
Stopped
Operating
Operating
●STP instruction ●Interrupt request used to
terminate Stop mode
is executed
occurs.
●Oscillation starts.(When
an external clock is input
from the XIN pin, clock
input starts.)
●Watchdog timer starts
counting.
●Watchdog timer’s MSB = “0”
(However, watchdog timer interrupt
request does not occur.)
●Supply of CPU, BIU starts.
●Interrupt request which has been
used to terminate Stop mode is
accepted.
Fig. 10.2.1 Stop mode terminating sequence by interrupt request occurrence
10.2.2 Termination by hardware
reset
______
Supply “L” level to the RESET pin by using the external circuit until the oscillation of the oscillator is
stabilized.
The CPU and the SFR area are initialized in the same way as the system reset. However, the internal RAM
area retains the same contents as that before executing the STP instruction. The termination sequence is
the same as the internal processing sequence which is performed after a reset.
To determine whether a hardware reset was performed to terminate Stop mode or a system reset was
performed, use software after a reset.
Refer to “Chapter 13. RESET” for details about a reset.
7751 Group User’s Manual
10–5
STOP MODE
10.3 Precautions for Stop mode
10.3 Precautions for Stop mode
1. When using the STP instruction with the mask ROM version, select “STP instruction enable” with the STP
instruction option on the MASK ROM ORDER CONFIRMATION FORM.
The STP instruction is always enabled in the built-in PROM version and the flash memory version.
2. When executing the STP instruction after writing to the internal area or an external area, the three NOP
instructions must be inserted to complete the write operation before the STP instruction is executed.
STA A, ✕✕✕✕ ; Writing instruction
NOP
; NOP instruction insertion
NOP
;
NOP
;
STP
; STP instruction
Fig. 10.3.1 NOP instruction insertion example
10–6
7751 Group User’s Manual
CHAPTER 11
WAIT MODE
11.1 Clock generating circuit
11.2 Operation description
11.3 Precautions for Wait mode
WAIT MODE
11.1 Clock generating circuit
This chapter describes Wait mode.
Wait mode is used to stop CPU and BIU when there is no need to operate the central processing unit (CPU).
The microcomputer enters Wait mode when the WIT instruction is executed.
Wait mode can be terminated by an interrupt request occurrence or the hardware reset.
11.1 Clock generating circuit
Figure 11.1.1 shows the clock generating circuit.
XIN
Interrupt request
S
XOUT
1/2
Q
f2/f4
1 Clock source for
f16/f32
peripheral devices
select bit
1/2
0
f64/f128
1/8
1/4
1
STP instruction
R
1/16
Hold request
1/16
Reset
S
1/8
Operation clock for
internal peripheral devices
f512/f1024
Wf32/Wf64
Wf512/Wf1024
1
Watchdog
timer
0
Watchdog timer frequency
select bit
Q
(Note)
R
S
WIT instruction
BIU
Q
Ready request
Request of CPU wait
from BIU
CPU
R
Clock source for peripheral devices select bit : Bit 2 at address 5F16
Watchdog timer frequency select bit : Bit 0 at address 6116
CPU : Central processing unit
BIU : Bus interface unit
Note : This is the signal generated when the watchdog timer’s most significant bit becomes “0.”
Fig. 11.1.1 Clock generating circuit
11–2
7751 Group User’s Manual
WAIT MODE
11.2 Operation description
11.2 Operation description
When the WIT instruction is executed, CPU and BIU stop. The oscillator’s oscillation is not stopped. This
state is called “Wait mode.”
In Wait mode, the microcomputer’s power consumption is reduced though the Vcc, power source voltage,
is maintained.
Table 11.2.1 lists the microcomputer state and operation in and after Wait mode.
Table 11.2.1 Microcomputer state and operation in and after Wait mode
Item
State and Operation
State in
Operating
Oscillation
Wait mode
Stopped
CPU ,
BIU
Clock , 1, f2/f4 to f512/f1024, Operating
Timer A
Operating
Timer B
Serial I/O
devices
Internal peripheral
Wf 32/Wf64, Wf 512/Wf1024
A-D converter
Watchdog timer
Pins
By interrupt request
Operation
after termi- occurrence
nating Wait By hardware reset
Retains the same state in which the WIT instruction was executed
Supply of
CPU
and
BIU
starts just after the termination.
Operates in the same way as hardware reset
mode
7751 Group User’s Manual
11–3
WAIT MODE
11.2 Operation description
11.2.1 Termination by interrupt request occurrence
➀ When an interrupt request occurs, supply of clock CPU and BIU starts.
➁ The interrupt request which occurs in ➀ is accepted.
Table 11.2.2 shows the interrupts used to terminate Wait mode.
The occurrence of the watchdog timer interrupt request also terminates Wait mode.
Table 11.2.2 Interrupts used to terminate Wait mode
Interrupt
____
•INT i interrupt (i = 0 to 2)
•Timer Ai interrupt (i = 0 to 4)
•Timer Bi interrupt (i = 0 to 2)
•UARTi transmit interrupt (i = 0, 1)
•UARTi receive interrupt (i = 0, 1)
•A-D converter interrupt
Note : Refer to “Chapter 4. INTERRUPTS” and each
functional description about interrupts.
Before executing the WIT instruction, enable interrupts used to terminate Wait mode.
In addition, the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the
processor interrupt priority level (IPL) of the routine where the WIT instruction is executed. When the
multiple interrupts in Table 11.2.2 are enabled, Wait mode is terminated by the first interrupt request.
11.2.2 Termination by hardware reset
The CPU and the SFR area are initialized in the same way as a system reset. However, the internal RAM
area retains the same contents as that before executing the WIT instruction. The termination sequence is
the same as the internal processing sequence which is performed after a reset.
To determine whether a hardware reset was performed to terminate Wait mode or a system reset was
performed, use software after a reset.
Refer to “Chapter 13. RESET” for details about a reset.
11–4
7751 Group User’s Manual
WAIT MODE
11.3 Precautions for Wait mode
11.3 Precautions for Wait mode
When executing the WIT instruction after writing to the internal area or an external area, the three NOP
instructions must be inserted to complete the write operation before the WIT instruction is executed.
STA A, ✕✕✕✕ ; Writing instruction
NOP
; NOP instruction insertion
NOP
;
NOP
;
WIT
; WIT instruction
Fig. 11.3.1 NOP instruction insertion example
7751 Group User’s Manual
11–5
WAIT MODE
11.3 Precautions for Wait mode
MEMORANDUM
11–6
7751 Group User’s Manual
CHAPTER 12
CONNECTION WITH
EXTERNAL DEVICES
12.1 Signals required for accessing
external devices
12.2 Bus cycle
12.3 Ready function
12.4 Hold function
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
This chapter describes functions to connect devices externally.
12.1 Signals required for accessing external devices
The functions and operation of the signals which are required for accessing external devices are described
below.
When connecting an external device that requires a long access time, refer to sections “12.2 Bus cycle,”
“12.3 Ready function,” and “12.4 Hold function,” as well as this section.
12.1.1 Descriptions of signals
When an external device is connected, operate the microcomputer in the memory expansion or microprocessor
_
mode. (Refer to section “2.5 Processor modes.”) In these modes, pins P0 to P4 and the E pin function
as I/O pins for the signals required for accessing external devices.
Figure 12.1.1 shows the pin configuration in the _
memory expansion and microprocessor modes. Table
12.1.1 lists the functions of pins P0 to P4 and the E pin in the memory expansion and the microprocessor
modes.
12–2
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
A0
A1
A2
A3
A4
A5
A6
A7
A8/D8
A9/D9
A10/D10
A11/D11
A12/D12
A13/D13
A14/D14
A15/D15
A16/D0
A17/D1
A18/D2
A19/D3
●External data bus width = 16 bits (BYTE = “L”)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
65
40
66
39
67
38
68
37
69
36
70
35
A20/D4
A21/D5
A22/D6
A23/D7
R/W
BHE
ALE
HLDA
Vss
E
XOUT
XIN
RESET
CNVSS
BYTE
HOLD
34
71
M37751M6C-XXXFP
72
73
33
32
74
31
75
30
76
29
77
28
78
27
79
26
80
25
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
✽ P42/ 1
RDY
1
✽ : As
1
in microprocessor mode
: External address bus, external data bus,
bus control signal
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16/D0
A17/D1
A18/D2
A19/D3
●External data bus width = 8 bits (BYTE = “H”)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
65
40
66
39
67
38
68
37
69
36
70
35
71
M37751M6C-XXXFP
72
73
34
33
32
74
31
75
30
76
29
77
28
78
27
79
26
80
25
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
✽ P42/ 1
RDY
1
A20/D4
A21/D5
A22/D6
A23/D7
R/W
BHE
ALE
HLDA
Vss
E
XOUT
XIN
RESET
CNVSS
BYTE
HOLD
✽ : As
1
in microprocessor mode
: External address bus, external data bus,
bus control signal
Fig. 12.1.1 Pin configuration in memory expansion and microprocessor modes (top view)
7751 Group User’s Manual
12–3
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
_
Table 12.1.1 Functions of pins P0 to P4 and E pin in memory expansion and microprocessor modes
External data bus
width
Pin
A7 to A0
(P0)
A15/D15 to A8/D8
(P1)
8 bits
(BYTE = “H”)
16 bits
(BYTE = “L”)
A7 — A0
A15/D15 —
A8/D8
A7 — A0
A15 — A8
A15 — A8
D(odd)
A15— A8
D(odd): Data at odd address
A23/D7 to A16/D0
(P2)
A23/D7 —
A16/D0
A23 — A16
A23/D7 —
A16/D0
D(even)
D(even): Data at even address
HLDA (P33)
HLDA
ALE (P32)
ALE
BHE (P31)
BHE
BHE
R/W (P30)
R/W
R/W
P47 to P43
P47 — P43
A23— A16
D
D: Data
HLDA
ALE
P
P: Functions as a programmable I/O port.
1
(P42)
1
RDY (P41)
RDY
HOLD (P40)
HOLD
1
(Note 1)
RDY
HOLD
E
E
E
Notes 1: In the memory expansion mode, this pin functions as a programmable I/O port and can be programmed as the clock
output pin by software.
2: This table shows the pins’ functions. Refer to the following about the input/output timing of each signal:
“12.1.2 Operation of bus interface unit (BIU)”; “12.2 Bus cycle”; “12.3 Ready function”; “12.4 Hold function”;
“Chapter 15. ELECTRICAL CHARACTERISTICS.”
12–4
7751 Group User’s Manual
1
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
(1) External bus (A 0 to A7, A 8/D 8 to A 15/D 15, A 16/D 0 to A 23/D 7)
External areas are specified by the address (A0 to A23) output. Figure 12.1.2 shows the external area.
Pins A 8 to A 23 of the external address bus and pins D 0 to D15 of the external data bus are assigned
to the same pins. When the BYTE pin level, described later, is “L” (i.e., external data bus width is
16 bits), the A 8/D8 to A 15/D 15 and A16/D0 to A23/D7 pins perform address output and data input/output
with time-sharing. When the BYTE pin level is “H” (i.e., external data bus width is 8 bits), the
A16/D0 to A23/D7 pins perform address output and data input/output with time-sharing, and pins A 8 to
A15 output addresses.
Memory expansion mode
00000016
Microprocessor mode
00000016
SFR area
(Note)
SFR area
(Note)
00008016
00008016
Internal RAM
area
Internal RAM
area
00088016
00088016
00400016
Internal ROM
area
01000016
FFFFFF16
FFFFFF16
: External area
Note: Addresses 216 to 916 become an external area.
Fig. 12.1.2 External area
7751 Group User’s Manual
12–5
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
(2) External data bus width switching signal (BYTE pin level)
This signal is used to select the external data bus width between 8 bits and 16 bits. When this signal
level is “L,” the external data bus width is 16 bits; when the level is “H,” the bus width is 8 bits (refer
to Table 12.1.1.)
Fix this signal to either “H” or “L” level.
This signal is valid only for the external areas. When accessing the internal areas, the data bus width
is always 16 bits.
__
(3) Enable signal (E)
This signal becomes “L” level while reading or writing data to and from the data bus. (See Table
12.1.2.)
__
(4) Read/Write signal (R/W)
This signal indicates the state of the data bus. This signal becomes “L”
level while
writing to the data
_
__
bus. Table 12.1.2 lists the state of the data bus indicated with the E and R/W signals.
_
Table 12.1.2 State of
data bus indicated with E
__
and R/W signals
__
_
E
H
R/W
State of data bus
H
Not used
L
H
Read data
L
Write data
L
____
(5) Byte high enable signal (BHE)
This signal indicates the access to an odd address. This signal becomes “L” level when accessing
an only odd address or when simultaneously accessing odd and even addresses.
This signal is used to connect memories or I/O devices of which data bus width is 8 bits when the
external data bus width is 16 bits.
____
Table 12.1.3 lists levels of the external address bus A 0 and the BHE signal and access addresses.
____
Table 12.1.3 Levels of A 0 and BHE signal and access addresses
Access address
A0
____
BHE
Even and odd addresses
Even address
Odd address
(Simultaneous 2-byte access)
(1-byte access)
(1-byte access)
L
L
L
H
H
L
(6) Address latch enable signal (ALE)
This signal is used to obtain the address from the multiplexed signal of address and data that is input
and output to and from the A8/D8 to A15/D15 and A16/D 0 to A23/D7 pins. Make sure that when this signal
is “H,” latch the address and simultaneously output the addresses. When this signal is “L,” retain the
latched address.
____
(7) Ready function-related signal ( RDY)
This is the signal to use the Ready function. (Refer to section “12.3 Ready function.”)
_____
_____
(8) Hold function-related signals ( HOLD, HLDA)
These are the signals to use the Hold function. (Refer to section “12.4 Hold function.”)
12–6
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
(9) Clock φ 1
This signal has the same period as φ .
In the memory expansion mode, this signal is output externally by setting the clock φ1 output select
bit (bit 7 at address 5E 16) to “1.” Figure 12.1.3 shows the output start timing of clock φ 1.
In the microprocessor mode, this signal is always output externally.
Note: Even in the single-chip mode, the clock φ 1 can be output externally. This signal is output
externally by setting the clock φ 1 output select bit to “1” just as in the memory expansion
mode.
Writing “1” to clock
1
output select bit
E
Clock
1(P42)
Notes 1: The 1st cycle of clock 1 may be shortened; indicated by
.
2: This applies when writing to clock 1 output select bit while
P42 pin is outputting “L” level.
Fig. 12.1.3 Output start timing of clock φ 1
b7
b6
0
b5
b4
b3
b2
0
b1
b0
Processor mode register 0 (Address 5E16)
Bit
0
Bit name
Processor mode bits
1
2
Fix this bit to “0.”
3
Software reset bit
4
Interrupt priority detection time
select bits
5
6
Fix this bit to “0.”
7
Clock
1 output select bit
(Note 2)
Functions
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not selected
At reset
RW
0
RW
0
RW
(Note 1)
0
RW
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0
WO
b5 b4
0
RW
0
RW
0
RW
0
RW
0 0 : 7 cycles of
0 1 : 4 cycles of
1 0 : 2 cycles of
1 1 : Not selected
0 : Clock 1 output disabled
(P42 functions as a programmable
I/O port.)
1 : Clock 1 output enabled
(P42 functions as a clock 1 output pin.)
Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1.” (Fixed to “1.”)
2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”)
: Bits 0 to 6 are not used for setting of clock
1
output.
Fig. 12.1.4 Structure of processor mode register
7751 Group User’s Manual
12–7
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
12.1.2 Operation of bus interface unit (BIU)
Figures 12.1.5 and 12.1.6 show the examples of operating waveforms of the signals input and output to
/from externals when accessing external devices. The following explains these waveforms compared with
the basic operating waveform (refer to section “2.2.3 Operation of bus interface unit (BIU).”)
(1) When fetching instructions into instruction queue buffer
➀ When the instruction which is next fetched is located at an even address in the 16-bit external data
bus width, the BIU fetches 2 bytes at a time with the waveform (a). When in the 8-bit external data
bus width, the BIU fetches only 1 byte with the first half of waveform (e).
➁ When the instruction which is next fetched is located at an odd address in the 16-bit external data
bus width, the BIU fetches only 1 byte with the waveform (d). When in the 8-bit external data bus
width, the BIU fetches only 1 byte with the first half of waveform (f).
When a branch to an odd address is caused by a branch instruction and others in the 16-bit external
data bus width, the BIU first fetches 1 byte in waveform (d), and after that, fetches each two bytes
at a time in waveform (a).
(2) When reading or writing data to and from memory•I/O device
➀ When accessing 16-bit data which begins at an even address, waveform (a) or (e) is applied.
➁ When accessing 16-bit data which begins at an odd address, waveform (b) or (f) is applied.
➂ When accessing 8-bit data at an even address, waveform (c) or the first half of (e) is applied.
➃ When accessing 8-bit data at an odd address, waveform (d) or the first half of (f) is applied.
For instructions that are affected by the data length flag (m) and the index register length flag (x),
operation ➀ or ➁ is applied when flag m or x = “0”; operation ➂ or ➃ is applied when flag m or x
= “1.”
The setup of flags m and x and the selection of the external data bus width do not affect each other.
12–8
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
● External data bus width = 16 bits (BYTE = “L”)
<16-bit data access>
(a) Access from even address
E
ALE
Address
A0 to A7
A8 /D8 to A15 /D15
Address
Data(odd)
A16 /D0 to A23 /D7
Address
Data(even)
A0
BHE
(b) Access from odd address
E
ALE
Address
A0 to A7
A8 /D8 to A15 /D15
Address
A16 /D0 to A23 /D7
Address
Address
Data(odd)
Address
Data(even)
Address
A0
BHE
<8-bit data access>
(c) Access to even address
(d) Access to odd address
E
E
ALE
ALE
A0 to A7
Address
A8 /D8 to A15 /D15
Address
A16 /D0 to A23 /D7
Address
A0 to A7
Data(even)
Address
A8 /D8 to A15 /D15
Address
A16 /D0 to A23 /D7
Address
A0
A0
BHE
BHE
Data(odd)
Fig. 12.1.5 Example of operating waveforms of signals input and output to/from externals (1)
7751 Group User’s Manual
12–9
CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
● External data bus width = 8 bits (BYTE = “H”)
<8/16-bit data access>
(e) Access from even address
E
ALE
A0 to A7
Address
Address
A8 to A15
Address
Address
A16 /D0 to A23 /D7
Address
Data
Address
Data
A0
BHE
8-bit data access
16-bit data access
(f) Access from odd address
E
ALE
A0 to A7
Address
Address
A8 to A15
Address
Address
A16 /D0 to A23 /D7
Address
Data
Address
Data
A0
BHE
8-bit data access
16-bit data access
Note: When accessing 16-bit data, 2 times of access are performed in
the sequence of the low-order 8 bits and high-order 8 bits.
Fig. 12.1.6 Example of operating waveforms of signals input and output to/from externals (2)
12–10
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CONNECTION WITH EXTERNAL DEVICES
12.2 Bus cycle
12.2 Bus cycle
The bus cycle can be selected to make it easy to access the external devices which require a long access
time. The bus cycle is selected with the bus cycle select bits (bits 4 and 5 at address 5F16).
The selectable bus cycle depends on the CPU running speed. The CPU running speed is selected with the
CPU running speed select bit (bit 3 at address 5F16).
Table 12.2.1 lists the selection of CPU running speed and bus cycle. Figure 12.2.1 shows the structure of
the processor mode register 1 (address 5F 16). Table 12.2.2 lists each bus cycle.
The selection of bus cycle is valid only for external areas.
For the internal area, the access is performed with the fixed bus cycle.
Table 12.2.1 Selection of CPU running speed and bus cycle
Processor mode register 1
(address 5F16)
b5
1
b4
1
b3
1
1
0
1
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
Access to internal area
Access to external area
(Note)
2 φ access in low-speed running
2 φ access in low-speed running
3 φ access in low-speed running
4 φ access in low-speed running
High-speed running
3 φ access in high-speed running
RAM: 2 φ access
4 φ access in high-speed running
ROM, SFR: 3 φ access
5 φ access in high-speed running
Not selected
7751 Group User's Manual
12–11
CONNECTION WITH EXTERNAL DEVICES
12.2 Bus cycle
b7
b6
0 0
b5
b4
b3
b2
b1
b0
0 0
Processor mode register 1 (Address 5F16)
Bit
1, 0
Functions
Bit name
Fix these bits to “0.”
At reset
RW
0
RW
0
RW
2
Clock source for peripheral
devices select bit
(Note)
0:
1:
3
CPU running speed select bit
(Note)
0 : High-speed running
1 : Low-speed running
0
RW
4
Bus cycle select bits
In high-speed running
0
RW
0
RW
0
RW
divided by 2
b5 b4
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
In low-speed running
5
b5 b4
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
7, 6
Fix these bits to “0.”
Note: Fix this bit to “0” when f(XIN) > 25 MHz.
: Bits 0 to 2, 6 and 7 are not used to select the bus cycle.
Fig. 12.2.1 Structure of the processor mode register 1
12–12
7751 Group User's Manual
CONNECTION WITH EXTERNAL DEVICES
12.2 Bus cycle
Table 12.2.2 Bus cycle
High-speed running [ f (X IN) ≤ 40 MHz ]
Low-speed running [ f (X IN) ≤ 25 MHz ]
Internal area access
External area access
Internal area access
2 access in
low-speed running
1 bus cycle = 2
2 access in
low-speed running
2 access in
high-speed running
(RAM)
1 bus cycle = 2
1 bus cycle = 2
E
E
E
ALE
ALE
ALE
Reading
Writing
A
A W
External area access
(Note)
(Note)
Reading
Writing
R
Reading
A
A W
Writing
A
A
3 access in
low-speed running
?
3 access in high-speed
running (ROM, SFR)
3 access in high-speed
running
1 bus cycle = 3
1 bus cycle = 3
1 bus cycle = 3
E
E
E
ALE
ALE
ALE
Reading
A
Writing
A
R
W
Reading
A
Writing
A
4 access in
low-speed running
W
Reading
A
Writing
A
R
W
4 access in high-speed running
1 bus cycle = 4
1 bus cycle = 4
E
E
ALE
Reading
A
Writing
A
R
W
Reading
A
Writing
A
R
W
5 access in high-speed running
1 bus cycle = 5
E
ALE
Reading
A
Writing
A
R
WW
Note : Signals when accessing an internal area means signals which are output from pins
externally when accessing an internal area in the memory expansion mode.
A: Address
R: Data to be read
W: Data to be written
?: Undefined value
7751 Group User's Manual
12–13
CONNECTION WITH EXTERNAL DEVICES
12.3 Ready function
12.3 Ready function
Ready function provides the function
to facilitate access to external devices that require a long access time.
____
By supplying “L” level to the RDY pin in the memory
expansion or microprocessor mode, the microcomputer
____
enters Ready state and retains this state while the RDY pin is at “L” level. Table 12.3.1 lists the microcomputer’s
state in Ready state.
In Ready state, the oscillator’s oscillation does not stop, so that the internal peripheral devices can operate.
Ready function is valid for the internal and external areas.
Table 12.3.1 Microcomputer’s state in Ready state
Item
State
Oscillation,_ φ
Operating
φ CPU, φ BIU, E
Stopped at “L”
Pins A 0 to A 7, A 8/D 8 to __ Retains the state when Ready request was accepted.
A15/D15, A16/D0 to A23/D7, R/W,
____ _____
BHE, HLDA, ALE
Pins P43 to P4 7,
P5 to P8 (Note)
P42/φ 1
In the memory expansion mode:
•When clock φ 1 output select bit✽ = “1,” this pin outputs clock φ 1.
•When clock φ 1 output select bit = “0,” this pin retains the state when
Ready request was accepted.
In the microprocessor mode:
•This pin outputs clock φ 1.
Watchdog timer
Operating
Clock φ 1 output select bit : Bit 7 at address 5E 16
Note: When this functions as a programmable I/O port.
✽
12–14
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.3 Ready function
12.3.1 Operation description
____
The input level of the RDY pin is judged at the last falling of the clock φ 1 in each bus cycle. Then, when
“L” level is detected, the microcomputer
enters Ready state. (This is called acceptance of Ready request.)
____
In Ready state, the input level of the RDY pin is judged at every falling of the clock φ1. Then, when “H”
level is detected, the microcomputer terminates Ready state next rising of the clock φ1.
Figures 12.3.1 and 12.3.2 show timing of acceptance of Ready request and termination of Ready state.
Refer also to section “17.1 Memory expansion” about usage of the Ready function.
7751 Group User’s Manual
12–15
CONNECTION WITH EXTERNAL DEVICES
12.3 Ready function
● 2 access in low-speed running, 2 access in high-speed running
➀
➁
Judgment timing of input level to RDY pin
Clock
1
BIU
CPU
High-speed 2
E
Low-speed 2
ALE
RDY
Term unusing bus
Term using bus
● 3 access in low-speed running, 3 access in high-speed running
Judgment timing of input level to RDY pin
➀
➁
Clock 1
BIU
CPU
High-speed 3
E
Low-speed 3
ALE
RDY
Term using bus
➀ By accepting an Ready request, “L” level of E signal stops for 1 cycle with the clock
by
, and clocks BIU and CPU stop at “L” level.
➁ Ready state is terminated.
1,
indicated
✽ Input level to the RDY pin is not judged during the term unusing the bus or before the condition
above ➀.
Notes 1: The timing of ALE signal differs depending on low-speed running or high-speed running,
and accessing an internal area or an external area. For more information, refer to section
“Chapter 15. ELECTRICAL CHARACTERISTICS.”
2: The dotted lines of signals BIU, CPU and E indicate the waveform when input level to the
RDY pin is “H”, no Ready request.
3: In high-speed running, the internal RAM is accessed by 2 access in high-speed running.
Fig. 12.3.1 Timings of acceptance of Ready request and termination of Ready state (1)
12–16
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.3 Ready function
●4
access in low-speed running, 4 access in high-speed running
➀
➁
Judgment timing of input level to RDY pin
Clock
1
BIU
CPU
E
ALE
RDY
Term using bus
● 5 access in high-speed running
➀
Judgment timing of input level to RDY pin
Clock
➁
1
BIU
CPU
E
ALE
RDY
Term using bus
➀ By accepting an Ready request, “L” level of E signal stops for 1 cycle with the clock
by
, and clocks BIU and CPU stop at “L” level.
➁ Ready state is terminated.
1,
indicated
✽ Input level to the RDY pin is not judged during the term unusing the bus or before the condition
above ➀.
Notes 1: The timing of ALE signal differs depending on low-speed running or high-speed running,
and accessing an internal area or an external area. For more information, refer to section
“Chapter 15. ELECTRICAL CHARACTERISTICS .”
2: The dotted lines of signals BIU, CPU and E indicate the waveform when input level to
the RDY pin is “H”, no Ready request.
Fig. 12.3.2 Timings of acceptance of Ready request and termination of Ready state (2)
7751 Group User’s Manual
12–17
CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
12.4 Hold function
When composing the external circuit (DMA) which accesses the bus without using the central processing
unit (CPU), the Hold function is used to generate a timing for transferring the right to use the bus from the
CPU to the external circuit.
In the memory
expansion or microprocessor mode, the microcomputer
enters Hold state by input of “L” level
_____
_____
to the HOLD pin and retains this state while the level of the HOLD pin is at “L.” Table 12.4.1 lists the
microcomputer’s state in Hold state.
In Hold state, the oscillation of the oscillator does not stop. Accordingly, the internal peripheral devices can
operate. However, Watchdog timer stops operating.
Table 12.4.1 Microcomputer’s state in Hold state
Item
State
Oscillation
Operating
φCPU
φ_BIU, φ
E
Pins A 0 to A7, A 8/D 8 to __
A15/D___
15,
A16/D 0 to A 23/D 7, R/W, BHE
_____
Pins HLDA, ALE
Pin P42/ φ 1
Stopped at “L”
Operating
Stopped at “H”
Floating
Outputs “L” level.
In the memory expansion mode:
•When clock φ 1 output select bit✼ = “1,” this pin outputs clock φ 1.
•When clock φ 1 output select bit = “0,” this pin retains the state when Hold
request was accepted.
In the microprocessor mode:
•This pin outputs clock φ 1.
Pins P4 3 to P4 7, P5 to P8 (Note)
Retains the state when Hold request was accepted.
Watchdog timer
Stopped
Clock φ 1 output select bit✼ : Bit 7 at address 5E 16
Note: When this functions as a programmable I/O port.
12–18
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
12.4.1 Operation description
_____
Judgment timing of the input level of the HOLD pin depends on the state using the bus. While the bus is
judgment timing
not in use, the judgment is performed at every falling of φBIU. While the bus is in use, the_____
depends on the bus cycle. Table 12.4.2 lists the judgment timing of the input level of the HOLD pin during
the used bus.
Additionally, when accessing word data beginning from an odd address with 2-bus cycle, the judgment is
performed only at the second bus cycle. (See Figure 12.4.1.)
When “L” level is detected at judgment of the input level, the microcomputer enters Hold state. (This is
called acceptance of Hold request.)
_____
When the Hold request is accepted, φ CPU stops next rising of φBIU. At the_____
same time, the HLDA pin’s level
__
changes
“H”
to
“L”.
When
1
cycle
of
φ
BIU
has
passed
after
the
level
of
HLDA
pin becomes “L”, pins R/W,
___
BHE, and the external bus become floating state.
_____
In Hold state,_____
the input level of the HOLD pin is judged at every falling of φ BIU. Then, when “H” level is
detected, the_____
HLDA pin’s level changes “L” to “H” next rising of φ BIU. When 1 cycle of φBIU has passed after
the level of HLDA pin becomes “H”, the microcomputer terminates Hold state.
Figures 12.4.2 to 12.4.4 show timing of acceptance of Hold request and termination of Hold state.
Note: φ BIU has a same polarity and a same frequency as the clock φ 1. However, φ BIU stops by acceptance
of the Ready_____
request, or executing the STP or WIT instruction. Accordingly, judgment of the input
level of the HOLD pin is not performed during Ready state.
Judge
No judge
Judgment timing of input level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
Writing
A
A
W
A
W
Accessing word data with 2-bus cycle.
(Example of 2 access in low-speed running)
Fig. 12.4.1 Judgment when accessing word data beginning from odd address with 2-bus cycle
7751 Group User’s Manual
12–19
CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
_____
Table 12.4.2 Judgment timing of input level of HOLD pin during used bus
High-speed running [ f (X IN) ≤ 40 MHz ]
Low-speed running [ f (X IN) ≤ 25 MHz ]
Internal area access
External area access
Internal area access
2
access in low-speed running
Judgment timing of input
level to HOLD pin
Clock
2
access in low-speed running
Clock
1
2
access in high-speed running
(RAM)
Judgment timing of input
level to HOLD pin
BIU
Judgment timing of input
level to HOLD pin
Clock
1
BIU
1
BIU
E
E
E
ALE
ALE
ALE
Reading
Writing
External area access
(Note)
(Note)
Reading
A
Writing
A W
R
Reading
A
A W
Writing
A
A
3 access in low-speed running
Judgment timing of input
level to HOLD pin
Clock
Clock
1
BIU
BIU
1
BIU
E
E
E
ALE
ALE
ALE
Reading
Writing
4
3 access in high-speed running 3 access in high-speed running
(ROM, SFR)
Judgment timing of input
Judgment timing of input
level to HOLD pin
level to HOLD pin
Clock
1
?
A
R
A
W
Reading
A
Writing
A
access in low-speed running
Judgment timing of input
level to HOLD pin
Clock
Reading
W
Writing
1
E
E
ALE
ALE
Writing
R
W
BIU
BIU
Reading
A
4 access in high-speed running
Judgment timing of input
level to HOLD pin
Clock
1
A
A
A
R
W
Reading
A
Writing
A
R
W
5 access in high-speed running
Judgment timing of input
level to HOLD pin
Clock
1
BIU
E
ALE
Reading
A
Writing
A
R
W
Note : Signals when accessing an internal area means signals which are output from pins
externally when accessing an internal area in the memory expansion mode.
A: Address
R: Data to be read
12–20
W: Data to be written
?: Undefined value
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
<When inputting “L” level to HOLD pin during term unusing bus>
● State when inputting “L” level to HOLD pin
External data bus
Unused
Data length
External data bus width
8
8, 16
16
8, 16
Judgment timing of input
level to HOLD pin
Clock
1
✽
ALE
E
Floating
R/W
External address bus /
External data bus
➀
Floating
Address A
Address B
Floating
External address bus
BHE
HOLD
1
✕1
1
✕1
HLDA
Hold state
Term using bus
Term unusing bus
➀ This is the term in which the bus is not used, so that not a new
address but an address output just before is output again.
✽ Clock 1 has the same polarity and the same frequency as BIU.
Signals timing to be input or output externally is ordained by clock
1
as a basis.
Fig. 12.4.2 Timing of acceptance of Hold request and termination of Hold state (1)
7751 Group User’s Manual
12–21
CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
<When inputting “L” level to HOLD pin during term using bus; when data access is
completed with 1-bus cycle>
● State when inputting “L” level to HOLD pin
External data bus
Data length
External data bus width
8
8, 16
16
16 (Access from even address)
Using
✽
Judgment timing of input
level to HOLD pin
Clock
1
ALE
E
Floating
R/W
Address A
External address bus /
External data bus
Address A
➀
Floating
Data
Address B
Floating
External address bus
BHE
HOLD
1✕ 1
1✕ 1
HLDA
(Note 3)
Hold state
Term using bus
Term using bus
➀ When accepting a Hold request, not a new address but an address
output just before is output again.
Notes 1: This figure shows the case of 2 access in low-speed running.
2: Clock 1 has the same polarity and the same frequency as BIU.
Signals timing to be input or output externally is ordained by clock 1 as a basis.
3: This term indicated by Note 3 becomes 1.5 cycles in 5 access in high-speed
running. It is because the level judgment timing becomes the 1.5 cycles before the
end of the term using bus (See Table 12.4.2.)
Fig. 12.4.3 Timing of acceptance of Hold request and termination of Hold state (2)
12–22
7751 Group User’s Manual
CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
<When inputting “L” level to HOLD pin during term using bus; when data access is
completed with continuous 2-bus cycle>
● State when inputting “L” level to HOLD pin
External data bus
Data length
External data bus width
8
16
Using
16 (Access from odd address)
✽
Judgment timing of input
level to HOLD pin
Clock
1
ALE
E
Floating
R/W
Address A
Address A+1
➀
External address bus /
External data bus
Data
Floating
Data
Address B
Floating
External address bus
BHE
HOLD
1
✕1
1
✕1
Not accepted ➁
HLDA
(Note 3)
Hold state
Term using bus
Term using bus
➀ When accepting a Hold request, not a new address but an
address output just before is output again.
➁ Hold request cannot be accepted before input/output of 16-bit
data is completed.
Notes 1: This figure shows the case of 2 access in low-speed running.
2: Clock 1 has the same polarity and the same frequency as BIU.
Signals timing to be input or output externally is ordained by clock 1 as a basis.
3: This term indicated by Note 3 becomes 1.5 cycles in 5 access in high-speed
running. It is because the level judgment timing becomes the 1.5 cycles before the
end of the term using bus (See Table 12.4.2.)
Fig. 12.4.4 Timing of acceptance of Hold request and termination of Hold state (3)
7751 Group User’s Manual
12–23
CONNECTION WITH EXTERNAL DEVICES
12.4 Hold function
MEMORANDUM
12–24
7751 Group User’s Manual
CHAPTER 13
RESET
13.1 Hardware reset
13.2 Software reset
RESET
13.1 Hardware reset
This chapter describes the method to reset the microcomputer. There are two methods to do that: Hardware
reset and Software reset.
13.1 Hardware reset
When the power source voltage satisfies the microcomputer’s
recommended operating conditions, the
______
microcomputer is reset by supplying “L” level to the RESET pin. This is called a hardware reset. Figure
13.1.1 shows an example of hardware reset timing.
“H”
RESET
“L”
2 µ s or more
4 to 5 cycles of φ
Internal processing
sequence after a
reset
➁
Program is executed.
➂
➃
➀
Note: When the clock is stably supplied. (Refer to “13.1.4 Time supplying “L” level to RESET pin.”)
Fig. 13.1.1 Example of hardware reset timing
The following explains how the microcomputer operates for terms ➀ to ➃ above.
______
➀ After supplying “L” level to the RESET pin, the microcomputer initializes pins within a term of several ten
ns. (Refer ______
to Table 13.1.1.)
the
RESET pin is “L” level and within the term of 4 to 5 cycles of the internal clock φ after the
➁ While
______
RESET pin goes from “L” to “H,” the microcomputer initializes the central processing unit (CPU) and SFR
area. At this time, the contents of the internal RAM area become undefined (except when Stop or Wait
mode is terminated). (Refer to Figures 13.1.2 to 13.1.6.)
➂ After ➁, the microcomputer performs “Internal processing sequence after reset.” (Refer to Figure 13.1.7.)
➃ The microcomputer executes a program beginning with the address set into the reset vector addresses
which are FFFE 16 and FFFF 16.
13–2
7751 Group User’s Manual
RESET
13.1 Hardware reset
13.1.1 Pin state
______
Table 13.1.1 lists the microcomputer’s pin state while the RESET pin is “L” level.
______
Table 13.1.1 Pin state while RESET pin is “L” level
Mask ROM version
PROM version
(Including One time PROM
and EPROM versions)
CNVSS pin level
Vss or Vcc
Vss
Vcc (Note 1)
Pin (Port) name
P0
to P8
_
E
P0
to P8
_
E
P0, P1, P3 to P8
P2
_
Flash memory version
E
P0
to P8
_
Vss
Vcc (Note 2)
E
P0, P1, P3 to P8
P2
_
VPPH (Note 2)
E
P0, P1, P3, P4 0,
P4 1 , P4 3,P4 5 to P4 7,
P5 to P8
P2
P4 2
P4 4
_
Pin state
Floating.
Outputs “H” level.
Floating.
Outputs “H” level.
Floating.
Floating while supplying “H” level
to two pins of P51 and P52, or one
of them.
Outputs “H” or “L” level while supplying “L” level to two pins of P5 1
and P5 2.
Outputs “H” level.
Floating.
Outputs “H” level.
Floating.
Floating while supplying “H” level
to two pins of P51 and P5 2, or one
of them.
Outputs “H” or “L” level while supplying “L” level to two pins of P51
and P5 2.
Outputs “H” level.
Floating.
Floating while supplying “H” level
to two pins of P5 1 and P5 2, or one
of them.
Outputs “H” or “L” level while supplying “L” level to two pins of P51
and P5 2.
Outputs clock φ 1.
Floating while supplying “L” level to
one or more pins of P45, P46 and P51.
Outputs “H” or “L” level while supplying “H” level to three pins of P45,
P4 6 and P5 1.
Outputs “H” level.
E
Notes 1: Each pin becomes the above state. It is because the microcomputer enters the EPROM mode.
Refer to “Chapter 18. PROM VERSION.”
2: Each pin becomes the above state. It is because the microcomputer enters the Flash memory
mode. Refer to “Chapter 19. FLASH MEMORY VERSION.”
7751 Group User’s Manual
13–3
RESET
13.1 Hardware reset
13.1.2 State of CPU, SFR area, and internal RAM area
Figure 13.1.2 shows the state of the CPU registers immediately after reset. Figures 13.1.3 to 13.1.6 show
the state of the SFR area and internal RAM areas immediately after reset.
0 : “0” immediately after a reset.
1 : “1” immediately after a reset.
? : Undefined immediately after a reset.
0 : “0” immediately after a reset. Fix to “0.”
(Do not write “1” into this.
State immediately after a reset
Register name
b15
b8 b7
Accumulator A (A)
b0
?
?
b15
b8
Accumulator B (B)
b7
b0
?
?
b15
b8
Index register X (X)
b7
b0
?
?
b15
b8
Index register Y (Y)
b7
b0
?
?
b15
b8 b7
Stack pointer (S)
b0
?
?
b7
b0
Data bank register (DT)
0016
b7
b0
0016
Program bank register (PG)
b15
Program counter (PC)
b8 b7
Contents at address FFFF16
b15
b8 b7
Direct page register (DPR)
0016
0
0
0
0
0
0
0
IPL
Fig. 13.1.2 State of CPU registers immediately after reset
13–4
b0
0016
b15
Processor status register (PS)
b0
Contents at address FFFE16
7751 Group User’s Manual
b8
b7
0
?
?
0
0
0
1
?
b0
?
N
V
m
x
D
I
Z
C
RESET
13.1 Hardware reset
●SFR area (016 to 7F16)
RW : It is possible to read the bit state at reading. The written value becomes valid data.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid data. It is not possible to read the bit state.
: Nothing is assigned. It is not possible to read the bit state. The written value becomes invalid.
0 : “0” immediately after a reset.
1 : “1” immediately after a reset.
? : Undefined immediately after
a reset.
Address Register name
016
116
216
316
416
516
616
716
816
916
A16
B16
C16
D16
E16
F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
1E16
1F16
b7
0
: Always “0” at reading.
?
: Always undefined at reading.
0 : “0” immediately after a reset. Fix to “0.”
(Do not write “1” into this.)
Access characteristics
State immediately after a reset
b0
b0
b7
?
?
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
@
Port P7 direction register
Port P8 register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port P8 direction register
RW
A-D control register 0
RW
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
A-D control register 1
?
0016
0016
?
RW
0
0
0
RW
0
0
0
0
?
0
?
0
?
RW
Port P2 direction register
Port P3 direction register
Port P4 register
?
RW
RW
RW
RW
RW
Port P0 register
RW
0
0016
0 0
?
?
0016
0016
?
?
0016
0016
?
?
0016
?
?
?
?
?
?
?
?
?
0 0
0 0
?
0
0
0
0
?
1
1
Fig. 13.1.3 State of SFR and internal RAM areas immediately after reset (1)
7751 Group User’s Manual
13–5
RESET
13.1 Hardware reset
Address
2016
2116
2216
2316
2416
2516
2616
2716
2816
2916
2A16
2B16
2C16
2D16
2E16
2F16
3016
3116
3216
3316
3416
3516
3616
3716
3816
3916
3A16
3B16
3C16
3D16
3E16
3F16
Register name
b7
Access characteristics
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
UART0 transmit/receive mode register
UART0 baud rate register
UART0 transmit buffer register
RO
RW
RO
UART0 transmit/receive control register 1
0
0
UART1 baud rate register
UART1 transmit buffer register
RO
RW
RO
0
0
0
?
0
0
?
0
0
?
0
0
?
0
0
?
0
0
?
0
0
?
0 0
0016
?
?
?
? 1
0 0
?
0 0
0016
?
?
?
? 1
0 0
?
0 0
0
?
?
0
0
0
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
WO
RW
RW RO RW
0
0
?
0
?
0
RO
0
0
0
WO
RW
RW RO RW
0
0
?
0
?
0
RO
0
0
0
RO
Fig. 13.1.4 State of SFR and internal RAM areas immediately after reset (2)
13–6
0
RW
WO
WO
UART1 transmit/receive mode register
UART1 receive buffer register
b0
RO
UART0 receive buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
State immediately after a reset
b7
?
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
WO
WO
A-D register 0
UART0 transmit/receive control register 0
b0
7751 Group User’s Manual
0
0
0
1
0
0
0
0
?
0
0
0
1
0
0
0
0
?
RESET
13.1 Hardware reset
Address
Access characteristics
Register name
b7
Count start register
4016
4116
4216 One-shot start register
4316
Up-down register
4416
4516
4616
Timer A0 register
4716
4816
Timer A1 register
4916
4A16
Timer A2 register
4B16
4C16
Timer A3 register
4D16
4E16
Timer A4 register
4F16
5016
Timer B0 register
5116
5216
Timer B1 register
5316
5416
Timer B2 register
5516
5616 Timer A0 mode register
5716 Timer A1 mode register
5816 Timer A2 mode register
5916 Timer A3 mode register
5A16 Timer A4 mode register
5B16 Timer B0 mode register
5C16 Timer B1 mode register
5D16 Timer B2 mode register
5E16 Processor mode register 0
5F16 Processor mode register 1
State immediately after a reset
b0
b7
b0
RW
?
WO
WO
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
0
0
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
RW
RW
RW
RW
RW
RW
RW
RW
(Note 3)
(Note 3)
(Note 3)
RW
RW
RW
RW
WO RW (Note 4) RW
RW
0016
?
0 0
?
0 0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0016
0016
0016
0016
0016
? 0
? 0
? 0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Note 4)
0
Notes 1: The access characteristics at addresses 46 16 to 4F16 vary according to Timer A’s operating
mode. (Refer to “Chapter 5. TIMER A.”)
2: The access characteristics at addresses 50 16 to 5516 vary according to Timer B’s operating
mode. (Refer to “Chapter 6. TIMER B.”)
3: The access characteristics for bit 5 at addresses 5B 16 to 5D16 vary according to Timer B’s
operating mode. (Refer to “Chapter 6. TIMER B.”)
4: The access characteristics for bit 1 at address 5E 16 and its state immediately after a reset vary
according to the voltage level supplied to the CNVss pin. (Refer to section “2.5 Processor
modes.”)
Fig. 13.1.5 State of SFR and internal RAM areas immediately after reset (3)
7751 Group User’s Manual
13–7
RESET
13.1 Hardware reset
Address
Register name
Watchdog timer register
6016
6116 Watchdog timer frequency select register
6216
6316
6416
6516
6616
6716
6816
6916
6A16
6B16
6C16
6D16
6E16
6F16
7016 A-D conversion interrupt control register
7116 UART0 transmit interrupt control register
7216 UART0 receive interrupt control register
7316 UART1 transmit interrupt control register
7416 UART1 receive interrupt control register
Timer A0 interrupt control register
7516
Timer A1 interrupt control register
7616
Timer A2 interrupt control register
7716
Timer A3 interrupt control register
7816
Timer A4 interrupt control register
7916
Timer B0 interrupt control register
7A16
Timer B1 interrupt control register
7B16
Timer B2 interrupt control register
7C16
INT0 interrupt control register
7D16
INT1 interrupt control register
7E16
INT2 interrupt control register
7F16
b7
Access characteristics
b0
State immediately after a reset
b7
b0
(Note 1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
?
?
?
?(Note 2)
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
0 0 0
0 0 0
0 0 0
0
(Note 3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes 1: By writing dummy data to address 60 16, a value “FFF 16” is set to the watchdog timer.
The dummy data is not retained anywhere.
2: The value “FFF16” is set to the watchdog timer. (Refer to “ Chapter 9. WATCHDOG TIMER.”)
●Internal RAM area; addresses 80 16 to 87F16 in M37751M6C-XXXFP)
•At hardware reset
(Except the case that Stop or Wait mode is terminated)...............................................
Undefined.
•At software reset.......................................................... Retaining the state immediately before a reset
•At terminating Stop or Wait mode
(Hardware reset is used to terminate it)............... Retaining the state immediately before the STP or
WIT instruction is executed
Fig. 13.1.6 State of SFR and internal RAM areas immediately after reset (4)
13–8
7751 Group User’s Manual
RESET
13.1 Hardware reset
13.1.3 Internal processing sequence after reset
Figure 13.1.7 shows the internal processing sequence after reset.
(1) In single-chip and memory expansion modes (CNVss = Vss)
C PU
AH(CPU)
AMAL(CPU)
DATA(CPU)
Undefined
0016
0016
0016
000016
FFFE16
ADM, ADL
IPL, reset vector address
ADM, ADL
Next op-code
E
ALE
Note: The only E signal is output externaly.
(2) In microprocessor mode (CNVss = Vcc)
1
C PU
A19–A16
016
000016
A15–A0
D15–D0
Undefined
016
016
FFFE16
ADM, ADL
IPL, reset vector address
ADM, ADL
Next op-code
E
ALE
Note: The
CPU
signal is not output
Fig. 13.1.7 Internal processing sequence after reset
7751 Group User’s Manual
13–9
RESET
13.1 Hardware reset
______
13.1.4 Time supplying “L” level
to RESET pin
______
Time supplying “L” level to the RESET pin varies according to the state of the clock oscillation circuit.
●When the oscillator is stably oscillating or a stable clock is input from the X IN pin, supply “L” level for
2 µ s or more.
●If the oscillator is not stably oscillating (including a power-on reset and In Stop mode), supply “L” level
until the oscillation is stabilized.
The time to stabilize oscillation varies according to the oscillator. For details, contact the oscillator
manufacturer.
Figure 13.1.8 shows the power-on reset condition. Figure 13.1.9 shows an example of a power-on reset
circuit.
✽ For details about Stop mode, refer to “Chapter 10. STOP MODE.” For details about clocks, refer to
“Chapter 14. CLOCK GENERATING CIRCUIT.”
Powered on here
4.5V
Vcc
0V
RESET
0.9V
0V
Fig. 13.1.8 Power-on reset condition
13–10
7751 Group User’s Manual
RESET
13.1 Hardware reset
5V
M37751
1 M51957AL
27kΩ
2
10k Ω
Vcc
Vcc
IN
OUT
5
Delay 4
capacity
GND
3
RESET
47 Ω
Vss
Cd
SW
GND
✽ The delay time is about 11 ms when Cd = 0.033 µF.
td ≈ 0.34 ✕ Cd [ µs], Cd: [ pF ]
Fig. 13.1.9 Example of power-on reset circuit
7751 Group User’s Manual
13–11
RESET
13.2 Software reset
13.2 Software reset
When the power source voltage satisfies the microcomputer’s recommended operating conditions, the
microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E 16). This is called a
software reset. In this case, the microcomputer initializes pins, CPU, and SFR area just as in the case of
a hardware reset. However, the microcomputer retains the contents of the internal RAM area. (Refer to
Table 13.1.1 and Figures 13.1.2 to 13.1.6.) Figure 13.2.1 shows the structure of processor mode register 0.
After completing initialization, the microcomputer performs the internal processing sequence after a reset.
(Refer to Figure 13.1.7.) After that, it executes a program beginning from the address set into the reset
vector addresses which are FFFE16 and FFFF 16.
b7
b6
0
b5
b4
b3
b2
0
b1
b0
Processor mode register 0 (Address 5E16)
Bit
0
Bit name
Processor mode bits
1
2
Fix this bit to “0.”
3
Software reset bit
4
Interrupt priority detection time
select bits
5
6
Fix this bit to “0.”
7
Clock
1 output select bit
(Note 2)
Functions
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not selected
At reset
RW
0
RW
0
RW
(Note 1)
0
RW
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0
WO
b5 b4
0
RW
0
RW
0
RW
0
RW
0 0 : 7 cycles of
0 1 : 4 icycles of
1 0 : 2 cycles of
1 1 : Not selected
0 : Clock 1 output disabled
(P42 functions as a programmable
I/O port.)
1 : Clock 1 output enabled
(P42 functions as a clock 1 output pin.)
Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1.” (Fixed to “1.”)
2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”)
: Bits 0 to 2, and bits 4 to 7 are not used for software reset.
Fig. 13.2.1 Structure of processor mode register 0
13–12
7751 Group User’s Manual
CHAPTER 14
CLOCK GENERATING
CIRCUIT
14.1 Oscillation circuit example
14.2 Clock
CLOCK GENERATING CIRCUIT
14.1 Oscillation circuit example
This chapter describes a clock generating circuit which supplies the operating clock of the central processing
unit (CPU), bus interface unit (BIU), or internal peripheral devices.
The clock generating circuit contains the oscillation circuit.
14.1 Oscillation circuit example
To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock
which is externally generated can be input. The example of the oscillation circuit is described below.
14.1.1 Connection example using resonator/oscillator
Figure 14.1.1 shows an example when connecting
a ceramic resonator/quartz-crystal oscillator between
pins X IN and X OUT.
The circuit constants such as Rf, Rd, CIN, and C OUT
(shown in Figure 14.1.1) depend on the resonator/
oscillator. These values shall be set to the resonator/
oscillator manufacturer’s recommended values.
M37751
XIN
XOUT
Rf
Rd
CIN
COUT
Fig. 14.1.1 Connection example using resonator/oscillator
14.1.2 Input example of externally generated clock
Figure 14.1.2 shows an input example of the clock
which is externally generated. The external clock
must be input from the X IN pin, and the X OUT pin
must be left open.
M37751
XIN
XOUT
Open
Externally generated clock
VCC
VSS
Fig. 14.1.2 Externally generated clock input example
14–2
7751 Group User’s Manual
CLOCK GENERATING CIRCUIT
14.2 Clock
14.2 Clock
Figure 14.2.1 shows the clock generating circuit block diagram.
XIN
Interrupt request
S
Q
f2/f4
1
XOUT
Clock source for
peripheral devices
select bit
“0”
1/2
1/2
f16/f32
f64/f128
1/8
1/4
“1”
STP instruction
Reset
R
S
Hold request
Watchdog
timer
BIU
(Note)
Ready request
Request of CPU
wait from BIU
WIT instruction
f512/f1024
Wf32/Wf64 “1”
1/16 Wf512/Wf1024
“0”
Watchdog timer
frequency
select bit
Q
R
S
1/16
1/8
Operation clock for
internal peripheral devices
C PU
Q
R
CPU
: Central Processing Unit
BIU
: Bus Interface Unit
Clock source for peripheral devices select bit: Bit 2 at address 5F16
Watchdog timer frequency select bit
: Bit 0 at address 6116
Note: This is the signal generated when the watchdog timer’s most significant bit becomes “0.”
Fig. 14.2.1 Clock generating circuit block diagram
7751 Group User’s Manual
14–3
CLOCK GENERATING CIRCUIT
14.2 Clock
14.2.1 Clock generated in clock generating circuit
(1) φ
This is the clock source of φ CPU, φ BIU clock φ 1, f2/f 4 to f512/f 1024, Wf 32/Wf64 and Wf512/Wf1024.
(2) φCPU
This is the operation clock of CPU.
(3) φBIU
This is the operation clock of BIU.
(4) Clock φ 1
This has the same period as φ and is output to the external.
(5) f2/f4 to f 512/f1024
Each of them is the operation clock for the
internal peripheral devices, and its clock source
is φ or φ divided by 2.
(Refer to “14.2.2 Operation clock for internal
peripheral devices.”)
(6) Wf 32/Wf64, Wf512/Wf 1024
This is the operation clock of Watchdog timer,
and its clock source is φ or φ divided by 2.
(Refer to “14.2.2 Operation clock for internal
peripheral devices.”)
14–4
Table 14.2.1 Operation clock for internal peripheral devices
Operation clock
Clock source for peripheral
devices select bit (See Fig. 14.2.2)
1
0
f2/f4
f2
f4
f16/f32
f16
f 32
f64/f128
f512/f1024
f64
f512
f 128
f 1024
Table 14.2.2 Operation clock for Watchdog timer
Operation clock
Clock source for peripheral
devices select bit (See Fig. 14.2.2)
1
0
Wf 32/Wf64
Wf32
Wf 64
Wf 512/Wf1024
Wf512
Wf 1024
7751 Group User’s Manual
CLOCK GENERATING CIRCUIT
14.2 Clock
14.2.2 Operation clock for internal peripheral devices
The operation clock for the internal peripheral devices uses φ or φ divided by 2 as its clock source.
The clock source of the operation clock for internal peripheral devices is selected by the clock source for
peripheral devices select bit (bit 2 at address 5F 16).
Figure 14.2.2 shows the structure of processor mode register 1 (address 5F 16).
When f(X IN) > 25 MHz, fix the clock source for peripheral devices select bit to “0.”
b7
b6
0 0
b5
b4
b3
b2
b1
b0
0 0
Processor mode register 1 (Address 5F16)
Bit
1, 0
Functions
Bit name
Fix these bits to “0.”
At reset
RW
0
RW
0
RW
2
Clock source for peripheral
devices select bit
(Note)
0:
1:
3
CPU running speed select bit
(Note)
0 : High-speed running
1 : Low-speed running
0
RW
4
Bus cycle select bits
In high-speed running
0
RW
0
RW
0
RW
divided by 2
b5 b4
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
In low-speed running
5
b5 b4
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
7, 6
Fix these bits to “0.”
Note: Fix this bit to “0” when f(XIN) > 25 MHz.
: Bits 0, 1, and bits 3 to 7 are not used for the clock generating circuit.
Fig. 14.2.2 Structure of processor mode register 1
7751 Group User’s Manual
14–5
CLOCK GENERATING CIRCUIT
14.2 Clock
MEMORANDUM
14–6
7751 Group User’s Manual
CHAPTER 15
ELECTRICAL
CHARACTERISTICS
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Absolute maximum ratings
Recommended operating conditions
Electrical characteristics
A-D converter characteristics
Internal peripheral devices
Ready and Hold
Single-chip mode
Memory expansion mode and microprocessor
mode : When 2-φ access in low-speed running
15.9 Memory expansion mode and microprocessor
mode : When 3-φ access in low-speed running
15.10 Memory expansion mode and microprocessor
mode : When 4-φ access in low-speed running
15.11 Memory expansion mode and microprocessor
mode : When 3-φ access in high-speed running
15.12 Memory expansion mode and microprocessor
mode : When 4-φ access in high-speed running
15.13 Memory expansion mode and microprocessor
mode : When 5-φ access in high-speed running
15.14 Memory expansion mode and microprocessor
mode : When 2-φ access in high-speed running
(Internal RAM access)
15.15 Testing circuit
for ports P0 to P8,
_
φ 1, and E
ELECTRICAL CHARACTERISTICS
15.1 Absolute maximum ratings
This chapter describes electrical characteristics of the M37751M6C-XXXFP.
For the latest data, inquire of addresses described last (☞“CONTACT ADDRESSES FOR FURTHER
INFORMATION”).
15.1 Absolute maximum ratings
Absolute maximum ratings
Parameter
Symbol
Power source voltage
VCC
Analog power source voltage
AVCC
VI
Input voltage
VI
Input voltage
Conditions
______
RESET , CNV SS, BYTE
Ratings
Unit
–0.3 to 7
V
–0.3 to 7
–0.3 to 12
V
–0.3 to V CC+0.3
V
–0.3 to V CC+0.3
V
V
P0 0–P0 7, P10–P1 7, P20–P27,
P3 0–P3 3, P4 0–P4 7, P5 0–P5 7,
P6 0–P6 7, P7 0–P7 7, P8 0–P8 7,
VREF, XIN
VO
Output voltage
P0 0–P0 7, P10–P1 7, P20–P27,
P3 0–P3 3, P4 0–P4 7, P5 0–P5 7,
P6 0–P6
7, P7 0–P7 7, P8 0–P8 7,
_
XOUT, E
Ta = 25 °C
Pd
Topr
Power dissipation
300
–20 to 85
mW
Operating temperature
Tstg
Storage temperature
–40 to 150
°C
15–2
7751 Group User’s Manual
°C
ELECTRICAL CHARACTERISTICS
15.2 Recommended operating conditions
15.2 Recommended operating conditions
Recommended operating conditions (V CC = 5 V±10%, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Max.
Typ.
VCC
4.5
5.5
Power source voltage
5.0
V
AVCC
Analog power source voltage
VCC
V
VSS
Power source voltage
0
V
AVSS
Analog power source voltage
0
V
High-level input voltage
P00–P07, P30–P33, P40–P47,
P50–P57, P60–P6
7, P70–P77,
______
VIH
V
0.8 VCC
VCC
P80–P87, XIN, RESET, CNVSS,
BYTE
High-level input voltage
P10–P17, P20–P27
VIH
V
0.8 VCC
VCC
(in single-chip mode)
P10–P17, P20–P27
High-level input voltage
VIH
V
(in memory expansion mode and 0.5 VCC
VCC
microprocessor mode)
Low-level input voltage
P00–P07, P30–P33, P40–P47,
P50–P57, P60–P6
7, P70–P77,
______
VIL
0
V
0.2 VCC
P80–P87, XIN, RESET, CNVSS,
BYTE
Low-level input voltage
P10–P17, P20–P27
VIL
0
V
0.2 VCC
(in single-chip mode)
Low-level input voltage
P10–P17, P20–P27
VIL
0
(in memory expansion mode and
0.16 VCC
V
microprocessor mode)
High-level peak output current
P00–P07, P10–P17, P20–P27,
IOH (peak)
mA
P30–P33, P40–P47, P50–P57,
–10
P60–P67, P70–P77, P80–P87
High-level average output current P00–P07, P10–P17, P20–P27,
IOH (avg)
mA
P30–P33, P40–P47, P50–P57,
–5
P60–P67, P70–P77, P80–P87
Low-level peak output current
P00–P07, P10–P17, P20–P27,
IOL (peak)
mA
P30–P33, P40–P47, P50–P57,
10
P60–P67, P70–P77, P80–P87
Low-level average output current P00–P07, P10–P17, P20–P27,
IOL (avg)
mA
P30–P33, P40–P47, P50–P57,
5
P60–P67, P70–P77, P80–P87
f(XIN)
Operating clock frequency
MHz
40
Notes 1: Average output current is the average value of a 100 ms interval.
2: The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 80 mA or less, and
the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.
7751 Group User’s Manual
15–3
ELECTRICAL CHARACTERISTICS
15.3 Electrical characteristics
15.3 Electrical characteristics
Electrical characteristics (V CC = 5 V, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 40 MHz, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min. Typ. Max.
High-level output voltage P00–P07, P10–P17, P20–P27,
P30, P31, P33, P40–P47,
IOH = –10 mA
V
VOH
3
P50–P57, P60–P67, P70–P77,
P80–P87
High-level output voltage P00–P07, P10–P17, P20–P27,
IOH = –400 µA
V
VOH
4.7
P30, P31, P33
High-level output voltage P32
IOH = –10 mA
3.1
V
VOH
IOH = –400 µA
4.8
High-level output voltage E
IOH = –10 mA
3.4
V
VOH
IOH = –400 µA
4.8
Low-level output voltage P00–P07, P10–P17, P20–P27,
P30, P31, P33, P40–P47,
IOL = 10 mA
VOL
2 V
P50–P57, P60–P67, P70–P77,
P80–P87
Low-level output voltage P00–P07, P10–P17, P20–P27,
IOL = 2 mA
VOL
0.45 V
P30, P31, P33
Low-level output voltage P32
IOL = 10 mA
VOL
1.9
V
IOL = 2 mA
0.43
Low-level output voltage E
IOL = 10 mA
VOL
1.6
V
IOL = 2 mA
0.4
HOLD, RDY, TA0IN–TA4IN, TB0IN–TB2IN,
VT+–VT– Hysteresis
1 V
0.4
INT0–INT2, ADTRG, CTS0, CTS1, CLK0, CLK1
VT+–VT– Hysteresis
0.5 V
0.2
RESET
VT+–VT– Hysteresis
0.3 V
0.1
XIN
High-level input current
P00–P07, P10–P17, P20–P27,
P30–P33, P40–P47, P50–P57,
VI = 5 V
5 µA
IIH
P60–P67, P70–P77, P80–P87,
XIN, RESET, CNVSS, BYTE
Low-level input current
P00–P07, P10–P17, P20–P27,
P30–P33, P40–P47, P50–P57,
VI = 0 V
–5 µA
IIL
P60–P67, P70–P77, P80–P87,
XIN, RESET, CNVSS, BYTE
When clock is stopped.
V
2
RAM hold voltage
VRAM
In single-chip mode, f(XIN) = 40 MHz
25
50 mA
Power source current
ICC
output pins are
open, and the other
pins are connected
to VSS.
15–4
7751 Group User’s Manual
Ta = 25°C, when
clock is stopped
Ta = 85°C, when
clock is stopped
1
µA
20
µA
ELECTRICAL CHARACTERISTICS
15.4 A-D converter characteristics
15.4 A-D converter characteristics
A-D CONVERTER CHARACTERISTICS (V CC = AV CC = 5 V±10%, VSS = AV SS = 0 V, Ta = –20 to 85 °C, unless otherwise
Limits
Test conditions
Parameter
Symbol
M i n . Typ. M a x .
V REF = V CC
10
—
Resolution
±3
Absolute accuracy
V REF = V CC
—
Resolution 10 bit
±2
Resolution 8 bit
V REF = V CC
RLADDER Ladder resistance
5
Resolution 10 bit 5.9
Conversion time
f(X IN) = 40 MHz
tCONV
Resolution 8 bit
4.9
Resolution 10 bit 4.72
f(X IN) = 25 MHz
Resolution 8 bit
3.92
Reference voltage
VCC
2
VREF
Analog input voltage
0
VREF
VIA
7751 Group User’s Manual
noted)
Unit
Bits
LSB
kΩ
µs
V
V
15–5
ELECTRICAL CHARACTERISTICS
15.5 Internal peripheral devices
15.5 Internal peripheral devices
Timing requirements (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Timer A input (Count input in event counter mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Limits
Min. Max.
80
40
40
Parameter
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Unit
ns
ns
ns
Timer A input (Gating input in timer mode)
Symbol
Parameter
Limits
Min. Max.
Data formula (Min.)
f(XIN) ≤ 40 MHz
16 ✕ 10
f(XIN)
Unit
9
400
f(XIN) ≤ 25 MHz
9
when φ divided by 2 selected as clock 16 ✕ 10
ns
640
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
8 ✕ 109
320
when φ selected as clock source for
f(XIN)
peripheral devices
8 ✕ 109
200
f(XIN) ≤ 40 MHz
f(XIN)
f(XIN) ≤ 25 MHz
8 ✕ 109
ns
tw(TAH)
TAiIN input high-level pulse width when φ divided by 2 selected as clock
320
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
4 ✕ 109
160
when φ selected as clock source for
f(XIN)
peripheral devices
8 ✕ 109
200
f(XIN) ≤ 40 MHz
f(XIN)
f(XIN) ≤ 25 MHz
9
tw(TAL)
TAiIN input low-level pulse width when φ divided by 2 selected as clock 8 ✕ 10
ns
320
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
4 ✕ 109
160
when φ selected as clock source for
f(XIN)
peripheral devices
Notes 1: TAiIN input cycle time must be 4 cycles or more of count source,
TAi IN input high-level pulse width must be 2 cycles or more of count source,
TAi IN input low-level pulse width must be 2 cycles or more of count source.
2: The limits in the upper row of the table are the values when f(X IN) is 40 MHz and the count source is f4.
The limits in the middle row of the table are the values when f(XIN) is 25 MHz and the count source is f4.
The limits in the lower row of the table are the values when f(XIN) is 25 MHz and the count source is f2.
tc(TA)
15–6
TAiIN input cycle time
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.5 Internal peripheral devices
Timer A input (External trigger input in one-shot pulse mode)
Symbol
f(XIN) ≤ 40 MHz
tc(TA)
TAiIN input cycle time
Limits
Min. Max.
Data formula (Min.)
Parameter
(Note)
f(XIN) ≤ 25 MHz
when φ divided by 2 selected as clock
source for peripheral devices
f(XIN) ≤ 25 MHz
when φ selected as clock source for
peripheral devices
8 ✕ 10
f(XIN)
Unit
9
200
8 ✕ 109
f(XIN)
320
4 ✕ 109
f(XIN)
160
ns
ns
80
TAiIN input high-level pulse width
ns
80
TAiIN input low-level pulse width
Note: The limits in the upper row of the table are the values when f(XIN) is 40 MHz and the count source is f4.
The limits in the middle row of the table are the values when f(XIN) is 25 MHz and the count source is f4.
The limits in the lower row of the table are the values when f(XIN) is 25 MHz and the count source is f2.
tw(TAH)
tw(TAL)
Timer A input (External trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
Parameter
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min. Max.
80
80
Unit
ns
ns
Timer A input (Up-down input in event counter mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP–T )
th(T –UP)
IN
IN
Parameter
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Limits
Min. Max.
2000
1000
1000
400
400
Unit
ns
ns
ns
ns
ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol
tsu(TAj
tsu(TAj
IN
–TAjOUT)
OUT
–TAjIN)
Parameter
TAjIN input setup time
TAjOUT input setup time
7751 Group User’s Manual
Limits
Min. Max.
200
200
Unit
ns
ns
15–7
ELECTRICAL CHARACTERISTICS
15.5 Internal peripheral devices
Internal peripheral devices
●Count input in event counter mode
●Gating input in timer mode
●External trigger input in one-shot pulse mode
●External trigger input in pulse width modulation mode
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
●Up-down input and count input in event counter mode
tc(UP)
tw(UPH)
TAiOUT input
(up-down input)
tw(UPL)
TAiOUT input
(up-down input)
TAiIN input
(When fall count is selected)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When rise count is selected)
●Two-phase pulse input in event counter mode
TAjIN input
tsu(TAjIN–TAjOUT)
tsu(TAjIN–TAjOUT)
tsu(TAjOUT–TAjIN)
TAjOUT input
tsu(TAjOUT–TAjIN)
Test conditions
•VCC = 5 V±10%
•Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
15–8
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.5 Internal peripheral devices
Timer B input (Count input in event counter mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Limits
Min. Max.
80
40
40
160
80
80
Parameter
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edges count)
TBiIN input high-level pulse width (both edges count)
TBiIN input low-level pulse width (both edges count)
Unit
ns
ns
ns
ns
ns
ns
Timer B input (pulse period measurement mode)
Symbol
Parameter
f(XIN) ≤ 40 MHz
tc(TB)
tw(TBH)
tw(TBL)
Limits
Min. Max.
Data formula (Min.)
16 ✕ 10
f(XIN)
f(XIN) ≤ 25 MHz
9
when φ divided by 2 selected as clock 16 ✕ 10
TBiIN input cycle time
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
8 ✕ 109
when φ selected as clock source for
f(XIN)
peripheral devices
8 ✕ 109
f(XIN) ≤ 40 MHz
f(XIN)
f(XIN) ≤ 25 MHz
8 ✕ 109
TBiIN input high-level pulse width when φ divided by 2 selected as clock
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
4 ✕ 109
when φ selected as clock source for
f(XIN)
peripheral devices
8 ✕ 109
f(XIN) ≤ 40 MHz
f(XIN)
f(XIN) ≤ 25 MHz
9
TBiIN input low-level pulse width when φ divided by 2 selected as clock 8 ✕ 10
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
when φ selected as clock source for
peripheral devices
Unit
9
4 ✕ 109
f(XIN)
400
640
ns
320
200
320
ns
160
200
320
ns
160
Notes 1: TBi IN input cycle time must be 4 cycles or more of count source,
TBi IN input high-level pulse width must be 2 cycles or more of count source,
TBi IN input low-level pulse width must be 2 cycles or more of count source.
2: The limits in the upper row of the table are the values when f(X IN) is 40 MHz and the count source is f4.
The limits in the middle row of the table are the values when f(XIN) is 25 MHz and the count source is f4.
The limits in the lower row of the table are the values when f(XIN) is 25 MHz and the count source is f2.
7751 Group User’s Manual
15–9
ELECTRICAL CHARACTERISTICS
15.5 Internal peripheral devices
Timer B input (Pulse width measurement mode)
Symbol
f(XIN) ≤ 40 MHz
tc(TB)
tw(TBH)
tw(TBL)
Limits
Min. Max.
Data formula (Min.)
Parameter
16 ✕ 10
f(XIN)
f(XIN) ≤ 25 MHz
9
when φ divided by 2 selected as clock 16 ✕ 10
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
8 ✕ 109
when φ selected as clock source for
f(XIN)
peripheral devices
8 ✕ 109
f(XIN) ≤ 40 MHz
f(XIN)
f(XIN) ≤ 25 MHz
8 ✕ 109
TBiIN input high-level pulse width when φ divided by 2 selected as clock
f(XIN)
source for peripheral devices
f(XIN) ≤ 25 MHz
4 ✕ 109
when φ selected as clock source for
f(XIN)
peripheral devices
8 ✕ 109
f(XIN) ≤ 40 MHz
f(XIN)
f(XIN) ≤ 25 MHz
9
TBiIN input low-level pulse width when φ divided by 2 selected as clock 8 ✕ 10
f(X
IN)
source for peripheral devices
f(XIN) ≤ 25 MHz
4 ✕ 109
when φ selected as clock source for
f(XIN)
peripheral devices
TBiIN input cycle time
Unit
9
400
640
ns
320
200
320
ns
160
200
320
ns
160
Notes 1: TBiIN input cycle time must be 4 cycles or more of count source,
TBi IN input high-level pulse width must be 2 cycles or more of count source,
TBi IN input low-level pulse width must be 2 cycles or more of count source.
2: The limits in the upper row of the table are the values when f(X IN) is 40 MHz and the count source is f4.
The limits in the middle row of the table are the values when f(XIN) is 25 MHz and the count source is f4.
The limits in the lower row of the table are the values when f(XIN) is 25 MHz and the count source is f2.
A-D trigger input
Symbol
tc(AD)
tw(ADL)
15–10
Parameter
_____
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
_____
7751 Group User’s Manual
Limits
Min. Max.
1000
125
Unit
ns
ns
ELECTRICAL CHARACTERISTICS
15.5 Internal peripheral devices
Serial I/O
Parameter
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C–Q)
th(C–Q)
tsu(D–C)
th(C–D)
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Limits
Min. Max.
200
100
100
80
0
20
90
Unit
ns
ns
ns
ns
ns
ns
ns
____
External interrupt INT i input
Symbol
tw(INH)
tw(INL)
Parameter
___
INT
i input high-level pulse width
___
INTi input low-level pulse width
7751 Group User’s Manual
Limits
Min. Max.
250
250
Unit
ns
ns
15–11
ELECTRICAL CHARACTERISTICS
15.5 Internal peripheral devices
Internal peripheral devices
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi input
tw(CKL)
th(C–Q)
TxDi output
td(C–Q)
tsu(D–C)
RxDi input
tw(INL)
INTi input
tw(INH)
Test conditions
•VCC = 5 V±10%
•Input timing voltage
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
15–12
7751 Group User’s Manual
th(C–D)
ELECTRICAL CHARACTERISTICS
15.6 Ready and Hold
15.6 Ready and Hold
Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(X IN ) = 40 MHz, unless otherwise noted)
Limits
Parameter
Symbol
Min. Max.
____
tsu(RDY–φ ) RDY
input setup time
40
_____
tsu(HOLD–φ ) ____
HOLD input setup time
40
th(φ –RDY)
RDY
input hold time
0
_____
th(φ –HOLD) HOLD input hold time
0
1
1
1
1
Unit
ns
ns
ns
ns
Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN ) = 40 MHz, unless otherwise noted)
Limits
Unit
Parameter
Symbol
Min.
Max.
_____
ns
td(φ –HLDA) HLDA output delay time
50
1
Note: For test conditions, refer to Figure 15.15.1.
7751 Group User’s Manual
15–13
ELECTRICAL CHARACTERISTICS
15.6 Ready and Hold
●Ready function
When 2- access in low-speed running
1
E output
RDY input
tsu(RDY–
1)
th(
1–RDY)
When 3- access and 4- access in low-speed running, and 4 - access in high-speed running
1
E output
RDY input
tsu(RDY–
When 2-
1)
access in high-speed running
1
E output
RDY input
tsu(RDY–
1)
th(
1–RDY)
Test conditions
•VCC = 5 V±10%
•Input timing voltage
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
15–14
7751 Group User’s Manual
th(
1–RDY)
ELECTRICAL CHARACTERISTICS
15.6 Ready and Hold
●Ready function
When 3- access in high-speed running
1
E output
RDY input
tsu(RDY–
1)
tsu(RDY–
1)
th(
1–RDY)
th(
1–RDY)
When 5- access in high-speed running
1
E output
RDY input
●Hold function
1
tsu(HOLD–
th(
1)
1–HOLD)
HOLD input
td(
1–HLDA)
td(
1–HLDA)
HLDA output
Test conditions
•VCC = 5 V±10%
•Input timing voltage
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
7751 Group User’s Manual
15–15
ELECTRICAL CHARACTERISTICS
15.7 Single-chip mode
15.7 Single-chip mode
Timing requirements (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Min. Max.
tc
External clock input cycle time
25
tw(H)
External clock input high-level pulse width
tc/2–8
tw(L)
External clock input low-level pulse width
tc/2–8
tr
External clock rise time
8
tf
External clock fall time
8
tsu(P0D–E) Port P0 input setup time
60
tsu(P1D–E) Port P1 input setup time
60
tsu(P2D–E) Port P2 input setup time
60
tsu(P3D–E) Port P3 input setup time
60
tsu(P4D–E) Port P4 input setup time
60
tsu(P5D–E) Port P5 input setup time
60
tsu(P6D–E) Port P6 input setup time
60
tsu(P7D–E) Port P7 input setup time
60
tsu(P8D–E) Port P8 input setup time
60
th(E–P0D)
Port P0 input hold time
0
th(E–P1D)
Port P1 input hold time
0
th(E–P2D)
Port P2 input hold time
0
th(E–P3D)
Port P3 input hold time
0
th(E–P4D)
Port P4 input hold time
0
th(E–P5D)
Port P5 input hold time
0
th(E–P6D)
Port P6 input hold time
0
th(E–P7D)
Port P7 input hold time
0
th(E–P8D)
Port P8 input hold time
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching characteristics (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min. Max.
ns
td(E–P0Q)
60
Port P0 data output delay time
ns
td(E–P1Q)
60
Port P1 data output delay time
ns
td(E–P2Q)
60
Port P2 data output delay time
ns
td(E–P3Q)
60
Port P3 data output delay time
ns
td(E–P4Q)
60
Port P4 data output delay time
ns
td(E–P5Q)
60
Port P5 data output delay time
ns
td(E–P6Q)
60
Port P6 data output delay time
ns
td(E–P7Q)
60
Port P7 data output delay time
ns
td(E–P8Q)
60
Port P8 data output delay time
Note: For test conditions, refer to Figure 15.15.1.
15–16
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.7 Single-chip mode
Single-chip mode
tf
tc
tr
tW(H)
tW(L)
XIN
E
td(E–P0Q)
Port P0 output
th(E–P0D)
tsu(P0D–E)
Port P0 input
td(E–P1Q)
Port P1 output
th(E–P1D)
tsu(P1D–E)
Port P1 input
td(E–P2Q)
Port P2 output
th(E–P2D)
tsu(P2D–E)
Port P2 input
td(E–P3Q)
Port P3 output
th(E–P3D)
tsu(P3D–E)
Port P3 input
td(E–P4Q)
Port P4 output
th(E–P4D)
tsu(P4D–E)
Port P4 input
td(E–P5Q)
Port P5 output
th(E–P5D)
tsu(P5D–E)
Port P5 input
td(E–P6Q)
Port P6 output
th(E–P6D)
tsu(P6D–E)
Port P6 input
td(E–P7Q)
Port P7 output
tsu(P7D–E)
th(E–P7D)
Port P7 input
td(E–P8Q)
Port P8 output
tsu(P8D–E)
th(E–P8D)
Port P8 input
Test conditions
•VCC = 5 V ±10%
•Input timing voltage
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage
: VOL = 0.8 V, VOH = 2.0 V
7751 Group User’s Manual
15–17
ELECTRICAL CHARACTERISTICS
15.8 Memory expansion mode and microprocessor mode : When 2-φ access in low-speed running
15.8 Memory expansion mode and microprocessor mode : When 2-φ access in low-speed running
Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
(Max.)
Min. Max.
tc
External clock input cycle time
tw(H)
Unit
40
ns
External clock input high-level pulse width
tc/2–8
ns
tw(L)
External clock input low-level pulse width
tc/2–8
ns
tr
External clock rise time
8
ns
tf
External clock fall time
8
ns
tsu(P1D–E)
Port P1 input setup time
30
ns
tsu(P2D–E)
Port P2 input setup time
30
ns
tsu(P4D–E)
Port P4 input setup time
60
ns
tsu(P5D–E)
Port P5 input setup time
60
ns
tsu(P6D–E)
Port P6 input setup time
60
ns
tsu(P7D–E)
Port P7 input setup time
60
ns
tsu(P8D–E)
Port P8 input setup time
60
ns
th(E–P1D)
Port P1 input hold time
0
ns
th(E–P2D)
Port P2 input hold time
0
ns
th(E–P4D)
Port P4 input hold time
0
ns
th(E–P5D)
Port P5 input hold time
0
ns
th(E–P6D)
Port P6 input hold time
0
ns
th(E–P7D)
Port P7 input hold time
0
ns
th(E–P8D)
Port P8 input hold time
0
ns
3 ✕ 10
–65
f(XIN)
9
tsu(P0A/P1A/P2A–P1D/P2D) Port Pi data setup time with address stabilized
15–18
7751 Group User’s Manual
55
ns
ELECTRICAL CHARACTERISTICS
15.8 Memory expansion mode and microprocessor mode : When 2-φ access in low-speed running
Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
td(E–P4Q)
Port P4 data output delay time
60
ns
td(E–P5Q)
Port P5 data output delay time
60
ns
td(E–P6Q)
Port P6 data output delay time
60
ns
td(E–P7Q)
Port P7 data output delay time
60
ns
td(E–P8Q)
Port P8 data output delay time
60
ns
tw(φH)
φ high-level pulse width
tw(φL)
φ low-level pulse width
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
20
ns
20
ns
td(E–φ )
φ 1 output delay time
tw(EL)
E low-level pulse width
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
35
ns
tpxz(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
ns
td(P1A–E)
Port P1 address output delay time
td(P1A–ALE)
Port P1 address output delay time
td(E–P2Q)
Port P2 data output delay time
35
ns
tpxz(E–P2Z)
Port P2 floating start delay time
5
ns
td(P2A–E)
Port P2 address output delay time
td(P2A–ALE)
Port P2 address output delay time
td(E–ALE)
ALE output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
1
0
_
2 ✕ 109
– 25
f(XIN)
1 ✕ 109
– 28
f(XIN)
1 ✕ 109
– 28
f(XIN)
1 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 28
f(XIN)
1 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 18
f(XIN)
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
____
__
18
ns
55
ns
12
ns
12
ns
5
ns
12
ns
5
ns
20
ns
4
ns
22
ns
20
ns
20
ns
Note: For test conditions, refer to Figure 15.15.1.
7751 Group User’s Manual
15–19
ELECTRICAL CHARACTERISTICS
15.8 Memory expansion mode and microprocessor mode : When 2-φ access in low-speed running
Switching characteristics (V CC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
9
1 ✕ 10
– 22 18
th(E–P0A)
Port P0 address hold time
ns
f(XIN)
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
th(E–P1Q)
Port P1 data hold time (BYTE = “L”)
tpzx(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
th(ALE–P2A)
Port P2 address hold time
th(E–P2Q)
Port P2 data hold time
tpzx(E–P2Z)
Port P2 floating release delay time
th(E–BHE)
BHE hold time
th(E–RW)
R/W hold time
____
__
Note: For test conditions, refer to Figure 15.15.1.
15–20
7751 Group User’s Manual
9
ns
18
ns
18
ns
18
ns
9
ns
– 22
18
ns
– 22
18
ns
– 22
18
ns
– 22
18
ns
1 ✕ 109
– 22
f(XIN)
1 ✕ 109
– 22
f(XIN)
1 ✕ 109
– 22
f(XIN)
1 ✕ 109
f(XIN)
1 ✕ 109
f(XIN)
1 ✕ 109
f(XIN)
1 ✕ 109
f(XIN)
ELECTRICAL CHARACTERISTICS
15.8 Memory expansion mode and microprocessor mode : When 2-φ access in low-speed running
Memory expansion mode and Microprocessor mode
: When 2- access in low-speed running
<Write>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E– 1)
tw(EL)
1)
E
th(E–P0A)
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
Address
th(E–P1A)
td(P1A–E)
Address
td(E–P1Q)
td(P1A–E)
td(P1A–ALE)
td(P2A–E)
Address/Data output
A16/D0–A23/D7
th(ALE–P1A)
td(E–P2Q )
Data
Address
td(P2A–ALE)
Data input
D0–D7
td(E–ALE)
tw (ALE)
th(E–P1Q)
Data
Address
th(E–P2Q )
th(ALE–P2A)
td(ALE–E)
ALE output
td(BH E–E)
th(E–BH E)
BHE output
td(R / W–E)
th(E–R / W )
R/W output
td(E–Pi Q )
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Input timing voltage
•Data input
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
15–21
ELECTRICAL CHARACTERISTICS
15.8 Memory expansion mode and microprocessor mode : When 2-φ access in low-speed running
Memory expansion mode and Microprocessor mode
: When 2- access in low-speed running
<Read>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E– 1)
tw(EL)
1)
E
th(E–P0A)
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
th(E–P1A)
Address
tpxz(E–P1Z)
td(P1A–E)
tpzx(E–P1Z)
Address
td(P1A–ALE)
th(ALE–P1A)
tsu(P1D–E)
th(E–P1D)
Data
td(P2A–E)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
Address
td(P1A–E)
tpzx(E–P2Z)
tpxz(E–P2Z)
Address
th(ALE–P2A)
tsu(P2D–E)
td(P2A–ALE)
tsu(P0A/P1A/P2A–P1D/P2D)
td(E–ALE)
tw(ALE)
th(E–P2D)
Data
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
tsu(PiD–E)
th(E–PiD)
Port Pi output
(i = 4–8)
Test conditions (
1,
E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
15–22
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage
•Data input
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
ELECTRICAL CHARACTERISTICS
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in low-speed running
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in low-speed running
Timing requirements (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
(Max.)
Min. Max.
tc
External clock input cycle time
tw(H)
Unit
40
ns
External clock input high-level pulse width
tc/2–8
ns
tw(L)
External clock input low-level pulse width
tc/2–8
ns
tr
External clock rise time
8
ns
tf
External clock fall time
8
ns
tsu(P1D–E)
Port P1 input setup time
30
ns
tsu(P2D–E)
Port P2 input setup time
30
ns
tsu(P4D–E)
Port P4 input setup time
60
ns
tsu(P5D–E)
Port P5 input setup time
60
ns
tsu(P6D–E)
Port P6 input setup time
60
ns
tsu(P7D–E)
Port P7 input setup time
60
ns
tsu(P8D–E)
Port P8 input setup time
60
ns
th(E–P1D)
Port P1 input hold time
0
ns
th(E–P2D)
Port P2 input hold time
0
ns
th(E–P4D)
Port P4 input hold time
0
ns
th(E–P5D)
Port P5 input hold time
0
ns
th(E–P6D)
Port P6 input hold time
0
ns
th(E–P7D)
Port P7 input hold time
0
ns
th(E–P8D)
Port P8 input hold time
0
ns
tsu(P0A/P1A/P2A–P1D/P2D) Port Pi data setup time with address stabilized
7751 Group User’s Manual
5 ✕ 109
–65
f(XIN)
135
ns
15–23
ELECTRICAL CHARACTERISTICS
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in low-speed running
Switching characteristics (V CC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
td(E–P4Q)
Port P4 data output delay time
60
ns
td(E–P5Q)
Port P5 data output delay time
60
ns
td(E–P6Q)
Port P6 data output delay time
60
ns
td(E–P7Q)
Port P7 data output delay time
60
ns
td(E–P8Q)
Port P8 data output delay time
60
ns
tw(φH)
φ high-level pulse width
tw(φL)
φ low-level pulse width
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
20
ns
20
ns
td(E–φ )
φ 1 output delay time
tw(EL)
E low-level pulse width
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
35
ns
tpxz(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
ns
td(P1A–E)
Port P1 address output delay time
td(P1A–ALE)
Port P1 address output delay time
td(E–P2Q)
Port P2 data output delay time
35
ns
tpxz(E–P2Z)
Port P2 floating start delay time
5
ns
td(P2A–E)
Port P2 address output delay time
td(P2A–ALE)
Port P2 address output delay time
td(E–ALE)
ALE output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
1
0
_
1 ✕ 109
– 28
f(XIN)
1 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 28
f(XIN)
1 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 18
f(XIN)
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
____
__
Note: For test conditions, refer to Figure 15.15.1.
15–24
4 ✕ 109
– 25
f(XIN)
1 ✕ 109
– 28
f(XIN)
7751 Group User’s Manual
18
ns
135
ns
12
ns
12
ns
5
ns
12
ns
5
ns
20
ns
4
ns
22
ns
20
ns
20
ns
ELECTRICAL CHARACTERISTICS
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in low-speed running
Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
9
1 ✕ 10
– 22 18
th(E–P0A)
Port P0 address hold time
ns
f(XIN)
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
th(E–P1Q)
Port P1 data hold time (BYTE = “L”)
tpzx(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
th(ALE–P2A)
Port P2 address hold time
th(E–P2Q)
Port P2 data hold time
tpzx(E–P2Z)
Port P2 floating release delay time
th(E–BHE)
BHE hold time
th(E–RW)
R/W hold time
____
__
9
ns
18
ns
18
ns
18
ns
9
ns
– 22
18
ns
– 22
18
ns
– 22
18
ns
– 22
18
ns
1 ✕ 109
– 22
f(XIN)
1 ✕ 109
– 22
f(XIN)
1 ✕ 109
– 22
f(XIN)
1 ✕ 109
f(XIN)
1 ✕ 109
f(XIN)
1 ✕ 109
f(XIN)
1 ✕ 109
f(XIN)
Note: For test conditions, refer to Figure 15.15.1.
7751 Group User’s Manual
15–25
ELECTRICAL CHARACTERISTICS
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in low-speed running
Memory expansion mode and Microprocessor mode
: When 3- access in low-speed running
<Write>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
td(P1A–E)
th(E–P1A)
Address
td(E–P1Q)
td(P1A–E)
td(P1A–ALE)
th(ALE–P1A)
td(P2A–E)
td(E–P2Q)
Address
td(E–ALE)
th(E–P1Q)
Data
Address
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E–P0A)
Address
td(P2A–ALE)
tw(ALE)
th(E–P2Q)
Data
th(ALE–P2A)
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
BHE output
td(R/W–E)
th(E–R/W)
R/W output
td(E–PiQ)
Port Pi output
(i = 4–8)
Test conditions (
1,
E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input
15–26
: VIL = 0.8 V, VIH = 2.5 V
•Input timing voltage
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in low-speed running
Memory expansion mode and Microprocessor mode
: When 3- access in low-speed running
<Read>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
td(P0A–E)
th(E–P0A)
Address
td(P1A–E)
th(E–P1A)
Address
td(P1A–E)
tpzx(E–P1Z)
tpxz(E–P1Z)
Address
td(P1A–ALE)
tsu(P1D–E)
th(ALE–P1A)
th(E–P1D)
Data
td(P2A–E)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
1)
tw(EL)
E
tpxz(E–P2Z)
tpzx(E–P2Z)
Address
td(P2A–ALE)
tsu(P0A/P1A/P2A–P1D/P2D)
tw(ALE)
td(E–ALE)
th(ALE–P2A)
tsu(P2D–E)
th(E–P2D)
Data
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
tsu(PiD–E)
th(E–PiD)
Port Pi output
(i = 4–8)
Test conditions (
1,
Test conditions (P4–P8)
E, P0–P3)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Input timing voltage
•Data input
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
15–27
ELECTRICAL CHARACTERISTICS
15.10 Memory expansion mode and microprocessor mode : When 4-φ access in low-speed running
15.10 Memory expansion mode and microprocessor mode : When 4-φ access in low-speed running
Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
(Max.)
Min. Max.
tc
External clock input cycle time
tw(H)
Unit
40
ns
External clock input high-level pulse width
tc/2–8
ns
tw(L)
External clock input low-level pulse width
tc/2–8
ns
tr
External clock rise time
8
ns
tf
External clock fall time
8
ns
tsu(P1D–E)
Port P1 input setup time
30
ns
tsu(P2D–E)
Port P2 input setup time
30
ns
tsu(P4D–E)
Port P4 input setup time
60
ns
tsu(P5D–E)
Port P5 input setup time
60
ns
tsu(P6D–E)
Port P6 input setup time
60
ns
tsu(P7D–E)
Port P7 input setup time
60
ns
tsu(P8D–E)
Port P8 input setup time
60
ns
th(E–P1D)
Port P1 input hold time
0
ns
th(E–P2D)
Port P2 input hold time
0
ns
th(E–P4D)
Port P4 input hold time
0
ns
th(E–P5D)
Port P5 input hold time
0
ns
th(E–P6D)
Port P6 input hold time
0
ns
th(E–P7D)
Port P7 input hold time
0
ns
th(E–P8D)
Port P8 input hold time
0
ns
tsu(P0A/P1A/P2A–P1D/P2D) Port Pi data setup time with address stabilized
15–28
7751 Group User’s Manual
7 ✕ 109
–65
f(XIN)
215
ns
ELECTRICAL CHARACTERISTICS
15.10 Memory expansion mode and microprocessor mode : When 4-φ access in low-speed running
Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
td(E–P4Q)
Port P4 data output delay time
60
ns
td(E–P5Q)
Port P5 data output delay time
60
ns
td(E–P6Q)
Port P6 data output delay time
60
ns
td(E–P7Q)
Port P7 data output delay time
60
ns
td(E–P8Q)
Port P8 data output delay time
60
ns
tw(φH)
φ high-level pulse width
tw(φL)
φ low-level pulse width
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
20
ns
20
ns
td(E–φ )
φ 1 output delay time
tw(EL)
E low-level pulse width
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
35
ns
tpxz(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
ns
td(P1A–E)
Port P1 address output delay time
td(P1A–ALE)
Port P1 address output delay time
td(E–P2Q)
Port P2 data output delay time
35
ns
tpxz(E–P2Z)
Port P2 floating start delay time
5
ns
td(P2A–E)
Port P2 address output delay time
td(P2A–ALE)
Port P2 address output delay time
td(E–ALE)
ALE output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
1
0
_
4 ✕ 109
– 25
f(XIN)
3 ✕ 109
– 28
f(XIN)
3 ✕ 109
– 28
f(XIN)
2 ✕ 109
– 28
f(XIN)
3 ✕ 109
– 28
f(XIN)
2 ✕ 109
– 28
f(XIN)
1 ✕ 109
– 20
f(XIN)
2 ✕ 109
– 18
f(XIN)
3 ✕ 109
– 20
f(XIN)
3 ✕ 109
– 20
f(XIN)
____
__
18
ns
135
ns
92
ns
92
ns
52
ns
92
ns
52
ns
20
ns
4
ns
62
ns
100
ns
100
ns
Note: For test conditions, refer to Figure 15.15.1.
7751 Group User’s Manual
15–29
ELECTRICAL CHARACTERISTICS
15.10 Memory expansion mode and microprocessor mode : When 4-φ access in low-speed running
Switching characteristics (V CC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 25 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
9
1 ✕ 10
– 22 18
th(E–P0A)
Port P0 address hold time
ns
f(XIN)
9
1 ✕ 10
– 15 25
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
th(E–P1Q)
– 22 18
Port P1 data hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
– 22 18
ns
tpzx(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
f(XIN)
1 ✕ 109
ns
– 22 18
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
f(XIN)
1 ✕ 109
ns
th(ALE–P2A)
– 15 25
Port P2 address hold time
f(XIN)
1 ✕ 109
– 22 18
ns
th(E–P2Q)
Port P2 data hold time
f(XIN)
1 ✕ 109
– 22 18
ns
tpzx(E–P2Z)
Port P2 floating release delay time
f(XIN)
____
1 ✕ 109
ns
th(E–BHE)
– 22 18
BHE hold time
f(XIN)
__
1 ✕ 109
th(E–RW)
– 22 18
ns
R/W hold time
f(XIN)
Note: For test conditions, refer to Figure 15.15.1.
15–30
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.10 Memory expansion mode and microprocessor mode : When 4-φ access in low-speed runninge
Memory expansion mode and Microprocessor mode
: When 4- access in low-speed running
<Write>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
th(E–P0A)
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
Address
td(P1A–E)
td(P1A–E)
th(E–P1A)
Address
td(E–P1Q )
Address
td(P1A–ALE)
td(P2A–E)
Address/Data output
A16/D0–A23/D7
th(ALE–P1A)
td(E–P2Q)
td(P2A–ALE)
td(E–ALE)
tw(ALE)
th(E–P2Q)
Data
Address
Data input
D0–D7
th(E–P1Q)
Data
th(ALE–P2A)
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
BHE output
td(R/W–E)
th(E–R/W)
R/W output
td(E–PiQ)
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Input timing voltage
•Data input
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
15–31
ELECTRICAL CHARACTERISTICS
15.10 Memory expansion mode and microprocessor mode : When 4-φ access in low-speed runninge
Memory expansion mode and Microprocessor mode
: When 4- access in low-speed running
<Read>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
E
1)
tw(EL)
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E–P0A)
Address
td(P1A–E)
td(P1A–E)
th(E–P1A)
Address
tpxz(E–P1Z)
tpzx(E–P1Z)
Address
th(ALE–P1A)
td(P1A–ALE)
td(P2A–E)
tsu(P1D–E)
th(E–P1D)
Data
tpxz(E–P2Z)
tpzx(E–P2Z)
Address
td(P2A–ALE)
th(ALE–P2A)
tsu(P0A/P1A/P2A–P1D/P2D)
td(E–ALE)
tw(ALE)
tsu(P2D–E)
th(E–P2D)
Data
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
tsu(PiD–E)
th(E–PiD)
Port Pi output
(i = 4–8)
15–32
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage
•Data input
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
ELECTRICAL CHARACTERISTICS
15.11 Memory expansion mode and microprocessor mode : When 3-φ access in high-speed running
15.11 Memory expansion mode and microprocessor mode : When 3-φ access in high-speed running
Timing requirements (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
(Max.)
Min. Max.
tc
External clock input cycle time
tw(H)
Unit
25
ns
External clock input high-level pulse width
tc/2–8
ns
tw(L)
External clock input low-level pulse width
tc/2–8
ns
tr
External clock rise time
8
ns
tf
External clock fall time
8
ns
tsu(P1D–E)
Port P1 input setup time
30
ns
tsu(P2D–E)
Port P2 input setup time
30
ns
tsu(P4D–E)
Port P4 input setup time
60
ns
tsu(P5D–E)
Port P5 input setup time
60
ns
tsu(P6D–E)
Port P6 input setup time
60
ns
tsu(P7D–E)
Port P7 input setup time
60
ns
tsu(P8D–E)
Port P8 input setup time
60
ns
th(E–P1D)
Port P1 input hold time
0
ns
th(E–P2D)
Port P2 input hold time
0
ns
th(E–P4D)
Port P4 input hold time
0
ns
th(E–P5D)
Port P5 input hold time
0
ns
th(E–P6D)
Port P6 input hold time
0
ns
th(E–P7D)
Port P7 input hold time
0
ns
th(E–P8D)
Port P8 input hold time
0
ns
5 ✕ 10
–75
f(XIN)
9
tsu(P0A/P1A/P2A–P1D/P2D) Port Pi data setup time with address stabilized
7751 Group User’s Manual
50
ns
15–33
ELECTRICAL CHARACTERISTICS
15.11 Memory expansion mode and microprocessor mode : When 3-φ access in high-speed running
Switching characteristics (V CC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
td(E–P4Q)
Port P4 data output delay time
60
ns
td(E–P5Q)
Port P5 data output delay time
60
ns
td(E–P6Q)
Port P6 data output delay time
60
ns
td(E–P7Q)
Port P7 data output delay time
60
ns
td(E–P8Q)
Port P8 data output delay time
60
ns
tw(φH)
φ high-level pulse width
tw(φL)
φ low-level pulse width
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
5
ns
5
ns
td(E–φ )
φ 1 output delay time
tw(EL)
E low-level pulse width
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
35
ns
tpxz(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
ns
td(P1A–E)
Port P1 address output delay time
td(P1A–ALE)
Port P1 address output delay time
td(E–P2Q)
Port P2 data output delay time
35
ns
tpxz(E–P2Z)
Port P2 floating start delay time
5
ns
td(P2A–E)
Port P2 address output delay time
td(P2A–ALE)
Port P2 address output delay time
td(E–ALE)
ALE output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
1
0
_
____
__
Note: For test conditions, refer to Figure 15.15.1.
15–34
7751 Group User’s Manual
3 ✕ 109
– 25
f(XIN)
2 ✕ 109
– 35
f(XIN)
2 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 20
f(XIN)
2 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 15
f(XIN)
1 ✕ 109
– 7.5
2 ✕ f(XIN)
1 ✕ 109
– 15
f(XIN)
2 ✕ 109
– 30
f(XIN)
2 ✕ 109
– 30
f(XIN)
18
ns
50
ns
15
ns
15
ns
5
ns
15
ns
5
ns
10
ns
5
ns
10
ns
20
ns
20
ns
ELECTRICAL CHARACTERISTICS
15.11 Memory expansion mode and microprocessor mode : When 3-φ access in high-speed running
Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
9
1 ✕ 10
– 10 15
th(E–P0A)
Port P0 address hold time
ns
f(XIN)
9
1 ✕ 10
– 15 10
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
th(E–P1Q)
– 10 15
Port P1 data hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
– 10 15
ns
tpzx(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
f(XIN)
1 ✕ 109
ns
– 10 15
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
f(XIN)
1 ✕ 109
ns
– 15 10
th(ALE–P2A)
Port P2 address hold time
f(XIN)
1 ✕ 109
– 10 15
ns
th(E–P2Q)
Port P2 data hold time
f(XIN)
1 ✕ 109
– 10 15
ns
tpzx(E–P2Z)
Port P2 floating release delay time
f(XIN)
____
1 ✕ 109
ns
– 10 15
th(E–BHE)
BHE hold time
f(XIN)
__
1 ✕ 109
th(E–RW)
– 10 15
ns
R/W hold time
f(XIN)
Note: For test conditions, refer to Figure 15.15.1.
7751 Group User’s Manual
15–35
ELECTRICAL CHARACTERISTICS
15.11 Memory expansion mode and microprocessor mode : When 3-φ access in high-speed running
Memory expansion mode and Microprocessor mode
: When 3- access in high-speed running
<Write>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
td(P1A–E)
td(P1A–E)
Address
td(P1A–ALE)
Data
th(ALE–P1A)
td(E–P2Q) th(E–P2Q)
td(P2A–E)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E–P0A)
Address
th(E–P1A)
Address
td(E–P1Q) th(E–P1Q)
Address
td(P2A–ALE)
Data
th(ALE–P2A)
td(E–ALE) tw(ALE)
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
BHE output
td(R/W–E)
th(E–R/W)
R/W output
td(E–PiQ)
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage
•Data input
15–36
: VIL = 0.8 V, VIH = 2.5 V
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.11 Memory expansion mode and microprocessor mode : When 3-φ access in high-speed running
Memory expansion mode and Microprocessor mode
: When 3- access in high-speed running
<Read>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E– 1)
tw(EL)
1)
E
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Address
td(P1A–E)
th(E–P1A)
Address
td(P1A–E)
tpzx(E–P1Z)
tpxz(E–P1Z)
Address
td(P1A–ALE)
Data input
D8–D15
(BYTE =“L”)
th(ALE–P1A)
tsu(P1D–E)
th(E–P1D)
Data
td(P2A–E)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E–P0A)
tpzx(E–P2Z)
tpxz(E–P2Z)
Address
td(P2A–ALE)
tsu(P0A/P1A/P2A–P1D/P2D)
td(E–ALE) tw(ALE)
ALE output
th(ALE–P2A)
tsu(P2D–E)
th(E–P2D)
Data
td(ALE–E)
th(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
tsu(PiD–E)
th(E–PiD)
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage
•Data input
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
15–37
ELECTRICAL CHARACTERISTICS
15.12 Memory expansion mode and microprocessor mode : When 4-φ access in high-speed running
15.12 Memory expansion mode and microprocessor mode : When 4-φ access in high-speed running
Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
(Max.)
Min. Max.
tc
External clock input cycle time
tw(H)
Unit
25
ns
External clock input high-level pulse width
tc/2–8
ns
tw(L)
External clock input low-level pulse width
tc/2–8
ns
tr
External clock rise time
8
ns
tf
External clock fall time
8
ns
tsu(P1D–E)
Port P1 input setup time
30
ns
tsu(P2D–E)
Port P2 input setup time
30
ns
tsu(P4D–E)
Port P4 input setup time
60
ns
tsu(P5D–E)
Port P5 input setup time
60
ns
tsu(P6D–E)
Port P6 input setup time
60
ns
tsu(P7D–E)
Port P7 input setup time
60
ns
tsu(P8D–E)
Port P8 input setup time
60
ns
th(E–P1D)
Port P1 input hold time
0
ns
th(E–P2D)
Port P2 input hold time
0
ns
th(E–P4D)
Port P4 input hold time
0
ns
th(E–P5D)
Port P5 input hold time
0
ns
th(E–P6D)
Port P6 input hold time
0
ns
th(E–P7D)
Port P7 input hold time
0
ns
th(E–P8D)
Port P8 input hold time
0
ns
tsu(P0A/P1A/P2A–P1D/P2D) Port Pi data setup time with address stabilized
15–38
7751 Group User’s Manual
7 ✕ 109
–75
f(XIN)
100
ns
ELECTRICAL CHARACTERISTICS
15.12 Memory expansion mode and microprocessor mode : When 4-φ access in high-speed running
Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
td(E–P4Q)
Port P4 data output delay time
60
ns
td(E–P5Q)
Port P5 data output delay time
60
ns
td(E–P6Q)
Port P6 data output delay time
60
ns
td(E–P7Q)
Port P7 data output delay time
60
ns
td(E–P8Q)
Port P8 data output delay time
60
ns
tw(φH)
φ high-level pulse width
tw(φL)
φ low-level pulse width
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
5
ns
5
ns
td(E–φ )
φ 1 output delay time
tw(EL)
E low-level pulse width
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
35
ns
tpxz(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
ns
td(P1A–E)
Port P1 address output delay time
td(P1A–ALE)
Port P1 address output delay time
td(E–P2Q)
Port P2 data output delay time
35
ns
tpxz(E–P2Z)
Port P2 floating start delay time
5
ns
td(P2A–E)
Port P2 address output delay time
td(P2A–ALE)
Port P2 address output delay time
td(E–ALE)
ALE output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
1
0
_
____
__
4 ✕ 109
– 25
f(XIN)
3 ✕ 109
– 35
f(XIN)
3 ✕ 109
– 35
f(XIN)
2 ✕ 109
– 20
f(XIN)
3 ✕ 109
– 35
f(XIN)
2 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 15
f(XIN)
1 ✕ 109
– 7.5
2 ✕ f(XIN)
2 ✕ 109
– 15
f(XIN)
3 ✕ 109
– 30
f(XIN)
3 ✕ 109
– 30
f(XIN)
18
ns
75
ns
40
ns
40
ns
30
ns
40
ns
30
ns
10
ns
5
ns
35
ns
45
ns
45
ns
Note: For test conditions, refer to Figure 15.15.1.
7751 Group User’s Manual
15–39
ELECTRICAL CHARACTERISTICS
15.12 Memory expansion mode and microprocessor mode : When 4-φ access in high-speed running
Switching characteristics (V CC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
9
1 ✕ 10
– 10 15
th(E–P0A)
Port P0 address hold time
ns
f(XIN)
1 ✕ 109
– 15 10
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
th(E–P1Q)
– 10 15
Port P1 data hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
– 10 15
ns
tpzx(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
f(XIN)
1 ✕ 109
ns
– 10 15
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
f(XIN)
1 ✕ 109
ns
– 15 10
th(ALE–P2A)
Port P2 address hold time
f(XIN)
1 ✕ 109
– 10 15
ns
th(E–P2Q)
Port P2 data hold time
f(XIN)
1 ✕ 109
– 10 15
ns
tpzx(E–P2Z)
Port P2 floating release delay time
f(XIN)
____
1 ✕ 109
ns
th(E–BHE)
– 10 15
BHE hold time
f(XIN)
__
1 ✕ 109
th(E–RW)
– 10 15
ns
R/W hold time
f(XIN)
Note: For test conditions, refer to Figure 15.15.1.
15–40
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.12 Memory expansion mode and microprocessor mode : When 4-φ access in high-speed running
Memory expansion mode and Microprocessor mode
: When 4- access in high-speed running
<Write>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
Address
td(P1A–E)
th(E–P1A)
Address
td(E–P1Q)
td(P1A–E)
Address
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E–P0A)
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
td(P1A–ALE)
th(ALE–P1A)
td(P2A–E)
td(E–P2Q)
Address
td(P2A–ALE)
td(E–ALE)
th(E–P1Q)
Data
th(E–P2Q)
Data
th(ALE–P2A)
tw(ALE)
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
BHE output
td(R/W–E)
th(E–R/W)
R/W output
td(E–PiQ)
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage
•Data input
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
15–41
ELECTRICAL CHARACTERISTICS
15.12 Memory expansion mode and microprocessor mode : When 4-φ access in high-speed running
Memory expansion mode and Microprocessor mode
: When 4- access in high-speed running
<Read>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
td(P0A–E)
th(E–P0A)
Address
td(P1A–E)
th(E–P1A)
Address
td(P1A–E)
Address
th(ALE–P1A)
td(P1A–ALE)
tsu(P1D–E)
th(E–P1D)
Data
td(P2A–E)
tpzx(E–P2Z)
tpxz(E–P2Z)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
tpzx(E–P1Z)
tpxz(E–P1Z)
Address
td(E–ALE)
tsu(P2D–E)
th(ALE–P2A)
td(P2A–ALE)
tsu(P0A/P1A/P2A–P1D/P2D)
tw(ALE)
th(E–P2D)
Data
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
tsu(PiD–E)
th(E–PiD)
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input
15–42
: VIL = 0.8 V, VIH = 2.5 V
•Input timing voltage
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.13 Memory expansion mode and microprocessor mode : When 5-φ access in high-speed running
15.13 Memory expansion mode and microprocessor mode : When 5-φ access in high-speed running
Timing requirements (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
(Max.)
Min. Max.
tc
External clock input cycle time
tw(H)
Unit
25
ns
External clock input high-level pulse width
tc/2–8
ns
tw(L)
External clock input low-level pulse width
tc/2–8
ns
tr
External clock rise time
8
ns
tf
External clock fall time
8
ns
tsu(P1D–E)
Port P1 input setup time
30
ns
tsu(P2D–E)
Port P2 input setup time
30
ns
tsu(P4D–E)
Port P4 input setup time
60
ns
tsu(P5D–E)
Port P5 input setup time
60
ns
tsu(P6D–E)
Port P6 input setup time
60
ns
tsu(P7D–E)
Port P7 input setup time
60
ns
tsu(P8D–E)
Port P8 input setup time
60
ns
th(E–P1D)
Port P1 input hold time
0
ns
th(E–P2D)
Port P2 input hold time
0
ns
th(E–P4D)
Port P4 input hold time
0
ns
th(E–P5D)
Port P5 input hold time
0
ns
th(E–P6D)
Port P6 input hold time
0
ns
th(E–P7D)
Port P7 input hold time
0
ns
th(E–P8D)
Port P8 input hold time
0
ns
tsu(P0A/P1A/P2A–P1D/P2D) Port Pi data setup time with address stabilized
7751 Group User’s Manual
9 ✕ 109
–75
f(XIN)
150
ns
15–43
ELECTRICAL CHARACTERISTICS
15.13 Memory expansion mode and microprocessor mode : When 5-φ access in high-speed running
Switching characteristics (V CC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, f(X IN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
td(E–P4Q)
Port P4 data output delay time
60
ns
td(E–P5Q)
Port P5 data output delay time
60
ns
td(E–P6Q)
Port P6 data output delay time
60
ns
td(E–P7Q)
Port P7 data output delay time
60
ns
td(E–P8Q)
Port P8 data output delay time
60
ns
tw(φH)
φ high-level pulse width
tw(φL)
φ low-level pulse width
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 20
f(XIN)
5
ns
5
ns
td(E–φ )
φ 1 output delay time
tw(EL)
E low-level pulse width
td(P0A–E)
Port P0 address output delay time
td(E–P1Q)
Port P1 data output delay time (BYTE = “L”)
35
ns
tpxz(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
5
ns
td(P1A–E)
Port P1 address output delay time
td(P1A–ALE)
Port P1 address output delay time
td(E–P2Q)
Port P2 data output delay time
35
ns
tpxz(E–P2Z)
Port P2 floating start delay time
5
ns
td(P2A–E)
Port P2 address output delay time
td(P2A–ALE)
Port P2 address output delay time
td(E–ALE)
ALE output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
1
0
_
____
__
Note: For test conditions, refer to Figure 15.15.1.
15–44
7751 Group User’s Manual
6 ✕ 109
– 25
f(XIN)
3 ✕ 109
– 35
f(XIN)
3 ✕ 109
– 35
f(XIN)
2 ✕ 109
– 20
f(XIN)
3 ✕ 109
– 35
f(XIN)
2 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 15
f(XIN)
1 ✕ 109
– 7.5
2 ✕ f(XIN)
2 ✕ 109
– 15
f(XIN)
3 ✕ 109
– 30
f(XIN)
3 ✕ 109
– 30
f(XIN)
18
ns
125
ns
40
ns
40
ns
30
ns
40
ns
30
ns
10
ns
5
ns
35
ns
45
ns
45
ns
ELECTRICAL CHARACTERISTICS
15.13 Memory expansion mode and microprocessor mode : When 5-φ access in high-speed running
Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
Unit
(Min.)
Min. Max.
9
1 ✕ 10
– 10 15
th(E–P0A)
Port P0 address hold time
ns
f(XIN)
1 ✕ 109
– 15 10
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
th(E–P1Q)
– 10 15
Port P1 data hold time (BYTE = “L”)
ns
f(XIN)
1 ✕ 109
– 10 15
ns
tpzx(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
f(XIN)
1 ✕ 109
ns
– 10 15
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
f(XIN)
1 ✕ 109
ns
– 15 10
th(ALE–P2A)
Port P2 address hold time
f(XIN)
1 ✕ 109
– 10 15
ns
th(E–P2Q)
Port P2 data hold time
f(XIN)
1 ✕ 109
– 10 15
ns
tpzx(E–P2Z)
Port P2 floating release delay time
f(XIN)
____
1 ✕ 109
ns
th(E–BHE)
– 10 15
BHE hold time
f(XIN)
__
1 ✕ 109
th(E–RW)
– 10 15
ns
R/W hold time
f(XIN)
Note: For test conditions, refer to Figure 15.15.1.
7751 Group User’s Manual
15–45
ELECTRICAL CHARACTERISTICS
15.13 Memory expansion mode and microprocessor mode : When 5-φ access in high-speed running
Memory expansion mode and Microprocessor mode
: When 5- access in high-speed running
<Write>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
th(E–P0A)
Address
td(P1A–E)
th(E–P1A)
Address
th(E–P1Q)
td(E–P1Q)
td(P1A–E)
Data
td(P1A–ALE)
th(ALE–P1A)
td(P2A–E)
Address/Data output
A16/D0–A23/D7
Data
td(E–P2Q)
th(E–P2Q)
Data
Address
td(P2A–ALE)
Data input
D0–D7
td(E–ALE)
th(ALE–P2A)
tw(ALE)
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
BHE output
td(R/W–E)
th(E–R/W)
R/W output
td(E–PiQ)
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage
•Data input
15–46
: VIL = 0.8 V, VIH = 2.5 V
: VIL = 1.0 V, VIH = 4.0 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
15.13 Memory expansion mode and microprocessor mode : When 5-φ access in high-speed running
Memory expansion mode and Microprocessor mode
: When 5- access in high-speed running
<Read>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
th(E–P0A)
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE =“H”)
Address/Data output
A8/D8–A15/D15
(BYTE =“L”)
Data input
D8–D15
(BYTE =“L”)
Address
td(P1A–E)
th(E–P1A)
Address
td(P1A–E)
Address
tsu(P1D–E)
th(ALE–P1A)
td(P1A–ALE)
th(E–P1D)
Data
td(P2A–E)
tpzx(E–P2Z)
tpxz(E–P2Z)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
tpzx(E–P1Z)
tpxz(E–P1Z)
Address
td(P2A–ALE)
tsu(P0A/P1A/P2A–P1D/P2D)
td(E–ALE)
tsu(P2D–E)
th(ALE–P2A)
tw(ALE)
th(E–P2D)
Data
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
tsu(PiD–E)
th(E–PiD )
Port Pi output
(i = 4–8)
Test conditions ( 1, E, P0–P3)
Test conditions (P4–P8)
•VCC = 5 V±10%
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage
•Data input
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
: VIL = 1.0 V, VIH = 4.0 V
15–47
ELECTRICAL CHARACTERISTICS
15.14 Memory expansion mode and microprocessor mode : When 2-φ access in high-speed running (Internal RAM access)
15.14 Memory expansion mode and microprocessor mode : When 2-φ access in high-speed
running (Internal RAM access)
Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz, unless otherwise noted)
Limits
Data formula
Symbol
Parameter
(Min.)
Min. Max.
1 ✕ 109
– 20
5
tw(φH)
φ high-level pulse width
f(XIN)
1 ✕ 109
– 20
5
tw(φL)
φ low-level pulse width
f(XIN)
td(E–φ )
1
0
φ 1 output delay time
_
E low-level pulse width
td(P0A–E)
Port P0 address output delay time
tpxz(E–P1Z)
Port P1 floating start delay time (BYTE = “L”)
td(P1A–E)
Port P1 address output delay time
td(P1A–ALE)
Port P1 address output delay time
tpxz(E–P2Z)
Port P2 floating start delay time
td(P2A–E)
Port P2 address output delay time
td(P2A–ALE)
Port P2 address output delay time
td(E–ALE)
ALE output delay time
td(ALE–E)
ALE output delay time
tw(ALE)
ALE pulse width
td(BHE–E)
BHE output delay time
td(R/W–E)
R/W output delay time
th(E–P0A)
Port P0 address hold time
th(ALE–P1A)
Port P1 address hold time (BYTE = “L”)
tpzx(E–P1Z)
Port P1 floating release delay time (BYTE = “L”)
th(E–P1A)
Port P1 address hold time (BYTE = “H”)
th(ALE–P2A)
Port P2 address hold time
tpzx(E–P2Z)
Port P2 floating release delay time
____
th(E–R/W)
15–48
ns
ns
ns
9
tw(EL)
th(E–BHE)
1 ✕ 10
– 20
f(XIN)
2 ✕ 109
– 35
f(XIN)
18
Unit
__
____
BHE hold time
__
R/W hold time
7751 Group User’s Manual
5
ns
15
ns
5
2 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 20
f(XIN)
15
ns
5
ns
5
2 ✕ 109
– 35
f(XIN)
1 ✕ 109
– 20
f(XIN)
1 ✕ 109
– 15
f(XIN)
1 ✕ 109
– 7.5
2 ✕ f(XIN)
1 ✕ 109
– 15
f(XIN)
2 ✕ 109
– 30
f(XIN)
2 ✕ 109
– 30
f(XIN)
1 ✕ 109
– 10
f(XIN)
1 ✕ 109
– 15
f(XIN)
1 ✕ 109
– 10
f(XIN)
1 ✕ 109
– 10
f(XIN)
9
1 ✕ 10
– 15
f(XIN)
1 ✕ 109
– 10
f(XIN)
9
1 ✕ 10
– 10
f(XIN)
1 ✕ 109
– 10
f(XIN)
ns
ns
15
ns
5
ns
10
ns
5
ns
10
ns
20
ns
20
ns
15
ns
10
ns
15
ns
15
ns
10
ns
15
ns
15
ns
15
ns
ELECTRICAL CHARACTERISTICS
15.14 Memory expansion mode and microprocessor mode : When 2-φ access in high-speed running (Internal RAM access)
Memory expansion mode and Microprocessor mode
: When 2- access in high-speed running (Internal RAM access)
<Write>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
tw(EL)
1)
E
Address output
A0–A7
Address output
A8–A15
(BYTE = “H”)
Address/Data output
A8/D8–A15/D15
(BYTE = “L”)
Data input
D8–D15
(BYTE = “L”)
1)
td(P0A–E)
th(E–P0A)
td(P1A–E)
th(E–P1A)
td(P1A–E)
Data ✽
td(P1A–ALE)
th(ALE–P1A)
td(P2A–E)
Address/Data output
A16/D0–A23/D7
Address
td(P2A–ALE)
Data input
D0–D7
td(E–ALE)
Data ✽
th(ALE–P2A)
tw(ALE)
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
✽ The undefined value is output.
Test conditions ( 1, E, P0–P3)
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
15–49
ELECTRICAL CHARACTERISTICS
15.14 Memory expansion mode and microprocessor mode : When 2-φ access in high-speed running (Internal RAM access)
Memory expansion mode and Microprocessor mode
: When 2- access in high-speed running (Internal RAM access)
<Read>
tw(L) tw(H) tr tf
tc
XIN
tw(
L)
tw(
1
td(E–
H)
td(E–
1)
1)
tw(EL)
E
td(P0A–E)
Address output
A0–A7
Address output
A8–A15
(BYTE = “H”)
td(P1A–E)
th(E–P1A)
Address
tpxz(E–P1Z)
td(P1A–E)
Address/Data output
A8/D8–A15/D15
(BYTE = “L”)
Data input
D8–D15
(BYTE = “L”)
tpzx(E–P1Z)
Address
th(ALE–P1A)
td(P1A–ALE)
tpxz(E–P2Z)
td(P2A–E)
Address/Data output
A16/D0–A23/D7
Data input
D0–D7
th(E–P0A)
Address
tpzx(E–P2Z)
Address
th(ALE–P2A)
td(P2A–ALE)
td(E–ALE) tw(ALE)
td(ALE–E)
ALE output
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE output
R/W output
✽ The contents of external data bus cannot
be read into the internal.
Test conditions ( 1, E, P0–P3)
•VCC = 5 V±10%
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Data input
15–50
: VIL = 0.8 V, VIH = 2.5 V
7751 Group User’s Manual
ELECTRICAL CHARACTERISTICS
_
15.15 Testing circuit for ports P0 to P8, φ1, and E
_
15.15 Testing circuit for ports P0 to P8, φ1, and E
P0
P1
P2
P3
P4
P5
P6
P7
P8
100pF
1
E
_
Fig. 15.15.1 Testing circuit for ports P0 to P8, φ 1, and E
7751 Group User’s Manual
15–51
ELECTRICAL CHARACTERISTICS
15.15 Testing circuit for ports P0 to P8, φ 1, and E
MEMORANDUM
15–52
7751 Group User’s Manual
CHAPTER 16
STANDARD
CHARACTERISTICS
16.1 Standard characteristics
ST ANDARD CHARACTERISTICS
16.1 Standard characteristics
16.1 Standard characteristics
Standard characteristics described below are just examples of the M37751M6C-XXXFP’s characteristics and
are not guaranteed. For rated values, refer to “Chapter 15. ELECTRICAL CHARACTERISTICS.”
16.1.1 Programmable I/O port (CMOS output) standard characteristics
(1) P-channel IOH–V OH characteristics
40.0
Ta = 25 °C
Ta = 85 °C
IOH [mA]
30.0
20.0
10.0
0
1.0
2.0
3.0
4.0
5.0
VOH [V]
(2) N-channel IOL–V OL characteristics
40.0
Ta = 25 °C
Ta = 85 °C
IOL [mA]
30.0
20.0
10.0
0
1.0
2.0
3.0
VOL [V]
16–2
7751 Group User’s Manual
4.0
5.0
ST ANDARD CHARACTERISTICS
16.1 Standard characteristics
16.1.2 Icc–f(XIN) standard characteristics
(1) Icc–f(XIN) standard characteristics on operating and at reset
Measuring conditions (VCC = 5.0 V, Ta = 25 °C, f(XIN) ; square waveform)
20
ICC [mA]
On operating in single-chip mode
10
At reset
0
10
20
30
40
f(XIN) [MHz]
(2) Icc–f(X IN) standard characteristics during wait mode
Measuring conditions (VCC = 5.0 V, Ta = 25 °C, f(XIN) ; square waveform)
6
5
In single-chip mode
ICC [mA]
4
3
2
1
0
10
20
30
40
f(XIN) [MHz]
7751 Group User’s Manual
16–3
ST ANDARD CHARACTERISTICS
16.1 Standard characteristics
16.1.3 A-D converter standard characteristics
The lower line of the graph indicates the absolute precision errors. These are expressed as the deviation
from the ideal value when the output code changes. For example, the change in output code from 15 to
16 should occurs at 77.5 mV, but the measured value is –1.2 mV. Accordingly, the measured point of
change is 77.5 – 1.2 = 76.3 mV.
The upper line of the graph indicates the input voltage width for which the output code is constant. For
example, the measured input voltage width for which the output code is 16 is 4.9 mV, so that the differential
non-linear error is 4.9 – 5 = –0.1 mV (–0.02 LSB).
16–4
7751 Group User’s Manual
STANDARD CHARACTERISTICS
16.1 Standard characteristics
[Measuring conditions]
•Vcc = 5.12 V, •V REF = 5.12 V, •f(X IN ) = 40 MHz, •Ta = 25 °C
7751 Group User’s Manual
16–5
ST ANDARD CHARACTERISTICS
16.1 Standard characteristics
MEMORANDUM
16–6
7751 Group User’s Manual
CHAPTER 17
APPLICATIONS
17.1 Memory expansion
APPLICATIONS
17.1 Memory expansion
17.1 Memory expansion
This section shows examples for memory and I/O expansion. Refer to “Chapter 12. CONNECTION WITH
EXTERNAL DEVICES” for details about the functions and operation of used pins when expanding a memory
or I/O. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS” for timing requirements of the microcomputer.
Application shown here are just examples. The user shall modify them according to the actual application
and test them.
17.1.1 Memory expansion model
Memory expansion to the external is possible in the memory expansion mode or the microprocessor mode.
The level of the external data bus width select signal makes it possible to select the four memory expansion
models shown in Table 17.1.1.
(1) Minimum model
This is an expansion model of which external data bus width is 8 bits and accessible area is
expanded up to 64 Kbytes. It is unnecessary to connect the address latch externally. This is an
expansion model which is suited to having priority the cost when connecting the memory of which
external data bus width is 8 bits.
(2) Medium model A
This is an expansion model of which external data bus width is 8 bits and accessible area is
expanded up to 16 Mbytes. In this expansion model, the high-order 8 bits of the external address bus
(A 23 to A 16) are multiplexed with the external data bus. Therefore, an n-bit (n ≤ 8) address latch is
required for latching address (n bits of A 23 to A 16).
(3) Medium model B
This is an expansion model of which external data bus width is 16 bits and accessible area is
expanded up to 64 Kbytes. This expansion model is used when having priority the rate performance.
In this expansion model, the middle-order 8 bits of the external address bus (A15 to A8) are multiplexed
with the external data bus. Therefore, an 8-bit address latch is required for latching address (A 15 to
A8).
(4) Maximum model
This is an expansion model of which external data bus width is 16 bits and accessible area is
expanded up to 16 Mbytes. In this expansion model, the high- and middle-order 16 bits of the
external address bus (A 23 to A 8) are multiplexed with the external data bus. Therefore, an 8-bit
address latch for latching A 15 to A 8 and an n-bit (n ≤ 8) address latch for latching n bits of A 23 to A 16
are required.
17–2
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
Table 17.1.1 Memory expansion model
Access area
External data
bus width
Maximum 64 Kbytes
Maximum 16 Mbytes
M37751
M37751
BYTE
16
BYTE
A0–A15
P0
8-bit width;
P2
8
Memory expansion model
Minimum model
M37751
Latch n
D Q
E
8
D0–D7
Memory expansion model
M37751
16
BYTE
P0
P1
P2
BYTE = “L”
A0–A15+n
ALE
D0–D7
P2
16-bit width;
P1
P1
BYTE = “H”
16+n
P0
ALE
Latch 8
BYTE
A0–A15
DQ
E
16
Medium model A
16+n
P0
A0–A15+n
Latch 8
P1
D Q
E
P2
D Q
E
ALE
Latch
n
D0–D15
16
D0–D15
BHE
BHE
Memory expansion model
Medium model B
Memory expansion model
Maximum model
Notes 1: Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” for details about the functions and operation
of used pins when expanding a memory. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS” for timing
requirements.
2: Because the address bus width is used as maximum 24 bits when expanding a memory, strengthen the M37751’s
Vss line. (Refer to “Appendix 8. Examples of noise immunity improvement.”)
7751 Group User’s Manual
17–3
APPLICATIONS
17.1 Memory expansion
17.1.2 How to calculate timing
When expanding a memory, use a memory of which standard specifications satisfy the address access
time and the data setup time for write. The following describes how to calculate each timing.
➀ External memory’s address access time; ta(AD)
t a(AD) = tsu(P0A/P1A/P2A-P1D/P2D) – (address decode time ✽1 + address latch delay time✽2)
Address decode time✽1: Time required for the chip select signal to be enabled after decoding address
Address latch delay time ✽2: Delay time required when latching address (Unnecessary in minimum model)
➁ External memory’s data setup time for write; tsu(D)
t su(D) = t w(EL) – t d(E–P2Q/P1Q)
t d(E–P2Q/P1Q): t d(E–P2Q) or td(E–P1Q)
Table 17.1.2 lists the data or the calculation formulas for each parameter. Figure 17.1.1 shows the bus
timing diagram. Figures 17.1.2 and 17.1.4 show the relationship between t su(P0A/P1A/P2A-P1D/P2D) and f(X IN);
Figures 17.1.3 and 17.1.5 show the relationship between tsu(D) and f(X IN).
Table 17.1.2 Data or calculation formulas for each parameter (unit: ns)
Bus cycle Low-speed running Low-speed running Low-speed running High-speed running
3φ access
4φ access
3 φ access
2φ access
Parameter
t su(P0A/P1A/P2A
—P1D/P2D)
t w(EL)
t d(E-P2Q)
t d(E-P1Q)
17–4
5 ✕ 10 9
3 ✕ 10 9
– 65
– 65
f(X IN)
f(X IN)
7 ✕ 10 9
– 65
f(X IN)
2 ✕ 10 9
– 25
f(X IN)
4 ✕ 10 9
– 25
f(X IN)
4 ✕ 10 9 – 25 3 ✕ 10 9 – 25
f(X IN)
f(X IN)
35
35
High-speed running
4φ access
High-speed running
5φ access
5 ✕ 10 9 – 75 7 ✕ 10 9 – 75 9 ✕ 10 9 – 75
f(XIN)
f(XIN)
f(X IN)
35
7751 Group User’s Manual
35
4 ✕ 10 9 – 25
f(X IN)
6 ✕ 10 9 – 25
f(X IN)
35
35
APPLICATIONS
17.1 Memory expansion
External data bus width = 8 bits (BYTE = “H”)
E
tw(EL)
tw(EL)
ALE
Port P0
(A0–A7)
Port P1
(A8–A15)
Port P2
(A16/D0–A23/D7)
Address low-order
Address low-order
Address middle-order
Address middle-order
External memory
output data
Address
high-order
Address
high-order
Data
ta(AD)
td(E-P2Q)
tsu(P0A/P1A/P2A–P1D/P2D)
tsu(D)
When reading data
R/W
When writing data
External data bus width = 16 bits (BYTE = “L”)
E
tw(EL)
tw(EL)
ALE
Port P0
(A0–A7)
Port P1
(A8/D8–A15/D15)
Address low-order
Address
middle-order
External memory
output data
Address low-order
Address
middle-order
Data (odd address)
td(E-P1Q)
Port P2
(A16/D0–A23/D7)
External memory
output data
Address
high-order
Address
high-order
Data (even address)
ta(AD)
td(E-P2Q)
tSU(P0A/P1A/P2A-P1D/P2D)
tsu(D)
R/W
When reading data
When writing data
: Specifications of the M37751
(The others are the external memory’s.)
Fig. 17.1.1 Bus timing diagrams
7751 Group User’s Manual
17–5
APPLICATIONS
17.1 Memory expansion
Port Pi data setup time with address stabilized
tsu(P0A/P1A/P2A–P1D/P2D)
[ns] 1000
935
4 access in low-speed running
3 access in low-speed running
2 access in low-speed running
900
810
800
712
700
649
635
571
560
600
518
490
500
473
435
435
389
400 363
351
310
300
268
200
100
319
401
372
346
323 303
285 268
253 239
235
247 229
226 215
212 198
207
185
185 173
165
162
152
143 135
149 135 122
111 101
92 85 77
71 65 60 55
292
268
0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
[MHz]
Operation clock frequency f(XIN)
Fig. 17.1.2 Relationship between t su(P0A/P1A/P2A-P1D/P2D) and f(XIN) (at low-speed running)
[ns] 600
3 access in low-speed running or 4 access in low-speed running
2 access in low-speed running
Data setup time for writing to
external memory tsu(D)
511
500
440
384
400
340
303
300
273
225
190
200
162
140
121
100
106
247
93
225 206
82
73
190 175
162 150
140 130
121 113 106
100
65 57 51
45 40 35 30
26 23 20
0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
[MHz]
Operation clock frequency f(XIN)
Fig. 17.1.3 Relationship between t su(D) and f(X IN) (at low-speed running)
17–6
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
Port Pi data setup time with address stabilized
tsu(P0A/P1A/P2A–P1D/P2D)
[ns] 350 334
316
285
271
250 243
205
200
152
258
246
229
216
150
5 access in high-speed running
4 access in high-speed running
3 access in high-speed running
300
300
142
133
125
194
117
100
184
175
110 103
235
166
225
158
97
91
29
30
50
215
206
197
189 182
175
168 161
155 150
150 143
137 130
125 119
114 109
104 100
86 81
76 72
67 63 60
56 53 50
0
22
23
24
25
26
27
28
31
32
33
34
35
36
37
38
39
40
[MHz]
Operation clock frequency f(XIN)
Fig. 17.1.4 Relationship between t su(P0A/P1A/P2A–P1D/P2D) and f(XIN) (at high-speed running)
[ns] 220 212
200
Data setup time for writing to external memory
tsu(D)
200
5 access in high-speed running
4 access in high-speed running
3 access in high-speed running
190
180
180
170
160
162
154
146
140
120
121
113
106
100
80 76
70
65
60
100
60
93
55
88
51
82
47
77
43
40
140
73
40
133
69
36
127
121 116
65
33
61
30
57
28
111
54
25
106 102
51
23
20
48
21
97
93
90
45
42
40
18
16
15
0
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
[MHz]
Operation clock frequency f(XIN)
Fig. 17.1.5 Relationship between t su(D) and f(XIN) (at high-speed running)
7751 Group User’s Manual
17–7
APPLICATIONS
17.1 Memory expansion
17.1.3 Points in memory expansion
(1) Reading data
Figure 17.1.6 shows the timing at which data is read from an external memory.
When reading data, the external data bus is placed in a floating state, and data is read
from the
_
external memory. This floating
state is maintained from tpxz(E–P1Z/P2Z) after falling of the E signal till
_
t pzx(E–P1Z/P2Z) after rising of the E signal. Table 17.1.3 lists the values of t pxz(E–P1Z/P2Z) and the formulas
to calculate t pzx(E–P1Z/P2Z).
Consider timing during data read to avoid collision between the data being read–in and the preceding
or following address output because the external data bus is multiplexed with the external address
bus. (Refer to “(3) Precautions on memory expansion.”)
tw(EL)
E
External memory
output enable signal
(Read signal)
External memory
chip select signal
OE
CE, S
tpxz(E-P1Z/P2Z)
Address output and data input
A8/D8–A15/D15 ✽1
A16/D0–A23/D7
ta(OE)
tpzx(E-P1Z/P2Z)
Address
Address
ta(CE), ta(S)
✽2
ten(OE)
tDF, tdis(OE) ✽3
ten(CE), ten(S)
External memory
data output
Data
tsu(P1D/P2D-E)
: Specifications of the M37751
(The others are the external
memory’s.)
✽1: This applies when the external data bus has a width of 16 bits (BYTE = “L”).
✽2: If one of the external memory’s specifications is smaller than tpxz(E-P1Z/P2Z) , there is a possibility of the tail of
address colliding with the head of data. → Refer to “(3) Precautions on memory expansion.”
✽3: If one of the external memory’s specifications is greater than tpzx(E-P1Z/P2Z) , there is a possibility of the tail of
data colliding with the head of address. → Refer to “(3) Precautions on memory expansion.”
Fig. 17.1.6 Timing at which data is read from external memory
17–8
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
Table 17.1.3 Values of t pxz(E–P1Z/P2Z) and formulas to calculate t pzx(E–P1Z/P2Z) (unit : ns)
Bus cycle Low-speed running Low-speed running Low-speed running High-speed running High-speed running
3φ access
4φ access
3φ access
2φ access
4φ access
Parameter
tpxz(E—P1Z)
5
tpxz(E—P2Z)
5
5
5
5
tpzx(E—P1Z)
tpzx(E—P2Z)
1 ✕ 10 9
– 22
f(X IN)
1 ✕ 10 9
– 22
f(XIN)
1 ✕ 10 9 – 10
1 ✕ 10 9
– 22
f(X IN)
f(X IN)
7751 Group User’s Manual
1 ✕ 10 9 – 10
f(X IN)
High-speed running
5φ access
5
1 ✕ 10 9 – 10
f(XIN)
17–9
APPLICATIONS
17.1 Memory expansion
(2) Writing data
Figure 17.1.7 shows the timing at which data is written to an external memory.
_
When writing data, the output data is validated after td(E-P1Q/P2Q) passes from falling
of the E signal. Its
_
validated data is output continuously until th(E-P1Q/P2Q) passes from rising of the E signal. Table 17.1.4
lists the data of td(E-P1Q/P2Q) and the calculation formulas of t h(E-P1Q/P2Q).
Data output at writing data must satisfy the data set up time, tsu(D), and the data hold time, th(D), for
write to an external memory.
tw(EL)
E
External memory
write signals
W, WE
External memory
chip select signals
CE, S
td(E-P1Q/P2Q)
th(E-P1Q/P2Q)
Address and data output
A8/D8–A15/D15
✽
Address
A16/D0–A23/D7
Data
tsu(D)
Address
th(D)
: Specifications of the M37751
(The others are the external memory’s.)
✽ This applies when the external data bus has a width of 16 bits (BYTE = “L”).
Fig. 17.1.7 Timing at which data is written to external memory
Table 17.1.4 Data of t d(E-P1Q/P2Q) and calculation formulas of t h(E-P1Q/P2Q) (unit: ns)
Bus cycle Low-speed running Low-speed running Low-speed running High-speed running High-speed running
3φ access
4φ access
3φ access
2φ access
4φ access
Parameter
t d(E—P1Q)
35
t d(E—P2Q)
35
35
35
35
t h(E—P1Q)
t hE—P2Q)
17–10
1 ✕ 10 9
– 22
f(X IN)
1 ✕ 10 9
– 22
f(X IN)
1 ✕ 10 9 – 10
1 ✕ 10 9
– 22
f(X IN)
f(X IN)
7751 Group User’s Manual
1 ✕ 10 9 – 10
f(X IN)
High-speed running
5φ access
35
1 ✕ 10 9 – 10
f(X IN)
APPLICATIONS
17.1 Memory expansion
(3) Precautions on memory expansion
As described in ➀ to ➂ below, if specifications of the external memory do not match those of the
M37751, some considerations must be incorporated into circuit design as in the following cases:
➀ When using an external memory that requires a long access time, t a(AD)
_
➁ When using an external memory that outputs data within t pxz(E-P1Z/P2Z) after falling of the E signal_
➂ When using an external memory that outputs data for more than t pzx(E-P1Z/P2Z) after rising of the E
signal
➀ When using an external memory that requires a long access time, t a(AD)
If the M37751’s tsu(P1D/P2D-E) cannot be satisfied because the external memory requires a long access
time, t a(AD), examine the method described below:
● Lower f(X IN).
● Select a long bus cycle by software. (Refer to section “12.2 Bus cycle.”)
● Use Ready function. (Refer to section “12.3 Ready function.”)
Figure 17.1.8 shows an example of using Ready function (at 2 φ access in low–speed running ).
Figure 17.1.9 shows an example of using Ready function (at 3 φ access in low–speed running ).
Figure 17.1.10 shows an example of using Ready function (at 3φ access in high–speed running ).
Figure 17.1.11 shows an example of using Ready function (at 4φ access in high–speed running ).
Ready function is available ___
for the internal areas, so that the circuit in Figures 17.1.8 to 17.1.11
use the chip select signal (CS 2) to specify the area where Ready function is available.
7751 Group User’s Manual
17–11
APPLICATIONS
17.1 Memory expansion
M37751
A8–A23
(D0–D15)
✽1
Data bus
✽2
Address
decode
circuit
Address latch
circuit
CS1
CS2
A0–A7
Address bus
✽1, ✽2
Use the elements of which propagation delay
time is within 12 ns.
RDY
✽3
AC32
AC74
E
D Q
T
1
1
AC04
Ready function is available
only for areas accessed
by CS2.
Circuit condition: f(XIN) ≤ 25 MHz, 2 access in low-speed running
A
td(E-
B
tc
1)
1
1
Ready request is accepted at the RDY pin input
level judgment timing A .
Ready state release request is accepted at the
RDY pin input level judgment timing B .
E
CS2
Q(AC74)
: E ( “L” level) stop by Ready function.
RDY
tsu(RDY-
1)
tsu(RDY-
1)
Sum of propagation delay time for AC32 , AC74,
and AC04(max. : 26 ns)
Fig. 17.1.8 Example of using Ready function (at 2 φ access in low–speed running)
17–12
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
M37751
✽1 to ✽3
A8–A23
(D0–D15)
Use the elements of which sum of
propagation delay time is within
Data bus
Address
decode
circuit
Address
latch circuit
9
2 ✕10
–tsu(RDY– 1)
f(XIN)
(f(XIN) = 25 MHz, 40 ns).
CS1
CS2
Address bus
A0–A7
RDY
AC04
AC32
✽3
E
1D
Ready function is available
only for areas accessed
by CS2.
CLR
1Q
2D
1T
2Q
2T
✽1
AC04
✽2
AC74
1
1
Circuit condition: f(XIN) ≤ 25 MHz, 3 access in low–speed running
A
B
tc
td(E-φ1)
1
1
E
1Q (AC74)
2Q (AC74)
CS2
RDY
tsu(RDY-
1)
tsu(RDY-
1)
: E ( “L” level) stop by Ready function.
Sum of propagation delay time for AC32 , AC74,
and AC04(max. : 26 ns)
Ready request is accepted at the RDY pin input level judgment timing A .
Ready state release request is accepted at the RDY pin input level judgment timing B .
Fig. 17.1.9 Example of using Ready function (at 3 φ access in low–speed running)
7751 Group User’s Manual
17–13
APPLICATIONS
17.1 Memory expansion
M37751
A8–A23
(D0–D15)
Data bus
Address
latch circuit
Address
decode
circuit
✽1 to ✽4
Use the elements of which sum of
propagation delay time is within 30.5 ns.
CS1
CS2
A0–A7
Address bus
RDY
E
1
1
1D 1Q
2D 2Q
1T
2T
AC04 ✽1
✽4
BC32
BC32✽3
Ready function is available
only for areas accessed
by CS2.
AC74✽2
Circuit condition: f(XIN) ≤ 28 MHz, 3 access in high–speed running
A
td(E-
B
tc
1)
1
1
Ready request is accepted at the RDY pin input
level judgment timing A .
Ready state release request is accepted at the
RDY pin input level judgment timing B .
E
CS2
✽ :The condition satisfying tsu(RDY- 1) ≥ 40 ns
is tc ≥ 35.25 ns.
Accordingly, when f(XIN) ≤ 28 MHz, this
circuit example satisfies tsu(RDY- 1) ≥ 40 ns.
1Q (AC74)
2Q (AC74)
: E ( “L” level) stop by Ready function.
RDY
tsu(RDY-
1)
✽
tsu(RDY-
✽
1)
Sum of propagation delay time for BC32 ✕ 2 , AC74,
and AC04(max. : 30.5 ns)
Fig. 17.1.10 Example of using Ready function (at 3 φ access in high–speed running)
17–14
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
M37751
✽1 to ✽4
A8–A23
(D0–D15)
Use the elements of which sum of
propagation delay time is within 30.5 ns.
Data bus
Address
latch circuit
Address
decode
circuit
CS1
CS2
A0–A7
Address bus
RDY
BC32✽3
E
AC04
1D 1Q
2D 2Q
1T
2T
BC32✽4
Ready function is available
only for areas accessed
by CS2.
✽1
AC74 ✽2
1
1
Circuit condition: f(XIN) ≤ 28 MHz, 4 access in high–speed running
A
td(E-
B
tc
1)
1
1
E
1Q (AC74)
Ready request is accepted at the RDY pin input
level judgment timing A .
2Q (AC74)
Ready state release request is accepted at the
RDY pin input level judgment timing B .
✽ The condition satisfying tsu(RDY- 1) ≥ 40 ns
is tc ≥ 35.25 ns.
Accordingly, when f(XIN) ≤ 28 MHz, this
circuit example satisfies tsu(RDY- 1) ≥ 40 ns.
CS2
RDY
tsu(RDY-
1)
✽
tsu(RDY-
✽
1)
: E ( “L” level) stop by Ready function.
Sum of propagation delay time for BC32 ✕ 2 , AC74,
and AC04(max. : 30.5 ns)
Fig. 17.1.11 Example of using Ready function (at 4 φ access in high–speed running)
7751 Group User’s Manual
17–15
APPLICATIONS
17.1 Memory expansion
_
➁ When using an external memory that outputs data within tpxz(E-P1Z/P2Z) after falling of the E
signal
_
Because the external memory outputs data within tpxz(E-P1Z/P2Z) after falling of the E signal, there will
be a possibility of the __
tail of address colliding with the head of data. In such a _case, generate the
memory read signal (OE) with delay only the leading edge of the fall of the E. (Refer to Figure
17.1.12.)
E
External memory
output enable signal
(Read signal)
Address output
d
OE
tpxz(E-P1Z/P2Z)
Address
Address
External memory
data output
Data
ta(OE)
ten(OE)
: Specifications of the M37751
(The others are the external memory’s.)
Note: Satisfy tpxz(E-P1Z/P2Z) ≤ ten(OE)+d.
If ten(OE) ≤ tpxz(E-P1Z/P2Z) (= 5 ns), secure a certain time (i.e., ‘d’ in this diagram)
from falling of E to the falling of OE.
Fig. 17.1.12 Example of causing to delay data output timing
17–16
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
_
➂ When using external memory that outputs data for more than t pzx(E-P1Z/P2Z) after rising of E
signal
_
Because the external memory outputs data for more than t pzx(E-P1Z/P2Z) after rising of the E signal,
there will be a possibility of the tail of data colliding with the head of address. In such a case,
examine the method described below:
● Cut the tail of data output from the external memory by using, for example, a bus buffer.
● Use the Mitsubishi’s memory chips that can be connected without a bus buffer.
Figures 17.1.13 to 17.1.20 show examples for how to use a bus buffer and the timing charts. Table
17.1.5 lists the memory chips that can be connected a without bus buffer. When using one of these
memory chips, the user can connect it to the user’s microcomputer without a bus buffer because
below are guaranteed. (However, the read signal must go
timing parameters t DF and tdis(OE) listed
_
high within 10 ns after rising of E signal.)
Table 17.1.5 Memory chips that can be connected without bus buffer
Memory
Type description
Conditions
tDF/tdis(OE)
EPROM
M5M27C256AK-85, -10, -12, -15
f(XIN) ≤ 20 MHz, at low–speed running
(Maximum)
M5M27C512AK-10, -12, -15
15 ns
M5M27C100K-12. -15
(when guaranteeing by
kit) (Note)
M5M27C101K-12, -15
M5M27C102K-12, -15
M5M27C201K, JK-10, -12, -15
M5M27C202K, JK-10, -12, -15
One-time PROM M5M27C256AP, FP, VP, RV-12, -15
M5M27C512AP, FP-15
M5M27C100P-15
M5M27C101P, FP, J, VP, RV-15
M5M27C102P, FP, J, VP, RV-15
M5M27C201P, FP, J, VP, RV-12, -15
M5M27C202P, FP, J, VP, RV-12, -15
Flash memory M5M28F101P, FP, J, VP, RV-10, -12, -15
M5M28F102FP, J, VP, RV-10, -12, -15
SRAM
M5M5256CP, FP, KP, VP, RV-55LL, -55XL,
-70LL, -70XL, -85LL, -85XL, -10LL, -10XL
M5M5278CP, FP, J-20, -20L
M5M5278CP, FP, J-25, -25L
M5M5278DP, J-12
M5M5278DP, FP, J-15, -15L
M5M5278DP, FP, J-20, -20L
8 ns
f(XIN) ≤ 40 MHz, at high–speed running
f(XIN) ≤ 25 MHz, at low–speed running
10 ns
6 ns
f(XIN) ≤ 25 MHz, at low–speed running
7 ns
f(XIN) ≤ 25 MHz, at low–speed running
f(XIN) ≤ 40 MHz, at high–speed running
8 ns
Note: When the user want specifications of the memory chips listed above, add a comment “tDF/t dis(OE) 15 ns
product, microcomputer and kit.”
7751 Group User’s Manual
17–17
APPLICATIONS
17.1 Memory expansion
M37751
CNVSS
A1–A7
Address bus
AC573
BYTE
D
Q
LE OE
AC573
D Q
ALE
LE OE
F245 ✽2
A8/D8–
A15/D15
A
B
Data bus (odd)
DIR OC
F245 ✽2
A16/D0–
A23/D7
A
B
Data bus (even)
DIR OC
E
✽3
BC32
AC04
✽1
RD
R/W
WO
BHE
WE
A0
XIN
XOUT
AC32 ✽4
Circuit condition: 3 access in low-speed running
25 MHz
✽1: Use the elements of which propagation delay time is within 20 ns.
✽2, ✽3 : Use the elements of which sum of output disable time in ✽2 and
propagation delay time in ✽3 is within 18 ns and the sum of output
enable time in ✽2 and propagation delay time in ✽3 is 5 ns or more.
✽4: Use the elements of which propagation delay time is within 12 ns.
Fig. 17.1.13 Example for using bus buffer (at low–speed running–1)
17–18
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
<When reading>
135 (min.)
E
18 (min.)
5 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
A
BC32 (tPHL)
BC32 (tPLH)
OC (F245), RD
F245
(tPZH/tPZL)
External memory
data output A (F245)
F245
(tPHZ/tPLZ)
D
<When writing>
135 (min.)
E
35 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
D
A
BC32 (tPLH)
BC32 (tPHL)
OC (F245), WO, WE
F245
(tPHL/tPLH)
External memory
data output B (F245)
F245
(tPHZ/tPLZ)
D
(Unit : ns)
Fig. 17.1.14 Timing chart for sample circuit using bus buffers (at low–speed running-1)
7751 Group User’s Manual
17–19
APPLICATIONS
17.1 Memory expansion
M37751
CNVSS
A1–A7
Address bus
AC573
BYTE
D
Q
LE OE
AC573
D Q
LE OE
ALE
ALS245A✽2
A8/D8–
A15/D15
A
B
Data bus (odd)
DIR OC
ALS245A✽2
A16/D0–
A23/D7
A
Data bus (even)
B
DIR OC
E
AC04
This circuit ensures that the rising of the
write signal occurs 1/2 1 clock earlier to
extend the write hold time.
1D1Q
2D
1T
2T 2Q
AC74
1
1
AC04 ✽1
RD
R/W
WO
BHE
WE
A0
XIN
XOUT
AC32
AC32
Circuit condition : 3 access in low-speed running
16 MHz
✽1: Use the elements of which propagation delay time is within 42.5 ns.
✽2: Use the elements of which output enable time is 5 ns or more and output disable time is
within 40.5 ns.
Fig. 17.1.15 Example for using bus buffer (at low-speed running-2 : connecting with memory requiring
long hold time for write)
17–20
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
<When reading>
225 (min.)
E, OC (ALS245A)
40.5 (min.)
5 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
A
AC32 (tPHL)
AC32 (tPLH)
RD
ALS245A
(tPZH/tPZL)
External memory
data output A (ALS245A)
ALS245A
(tPHZ/tPLZ)
D
<When writing>
1
1
225 (min.)
E, OC (ALS245A)
1Q (AC74)
AC04 (tPLH)+AC74 (tPLH)
2Q(AC74)
AC32 ✕ 2 (tPLH)
WO, WE
A8/D8–A15/D15
A16/D0–A23/D7
35 (max.)
A
D
ALS245A
(tPHL/tPLH)
D
External memory
data output B
(ALS245A)
ALS245A
(tPHZ/tPLZ)
Write hold time
(Unit : ns)
Fig. 17.1.16 Timing chart for sample circuit using bus buffers (at low-speed running-2)
7751 Group User’s Manual
17–21
APPLICATIONS
17.1 Memory expansion
M37751
CNVSS
A1–A7
Address bus
AC573
BYTE
D
Q
LE OE
AC573
D Q
ALE
LE OE
F245 ✽2
A8/D8–
A15/D15
A
B
Data bus (odd)
DIR OC
F245 ✽2
A16/D0–
A23/D7
A
B
Data bus (even)
DIR OC
E
✽3
BC32
AC04
✽1
RD
R/W
WO
BHE
WE
A0
XIN
XOUT
AC32 ✽4
Circuit condition: 5 access in high-speed running
40 MHz
✽1: Use the elements of which propagation delay time is within 45 ns.
✽2, ✽3 : Use the elements of which sum of output disable time in ✽2 and
propagation delay time in ✽3 is within 15 ns, and the sum of output
enable time in ✽2 and propagation delay time in ✽3 is 5 ns or more.
✽4: Use the elements of which propagation delay time is within 40 ns.
Fig. 17.1.17 Example for using bus buffer (at high-speed running-1)
17–22
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
<When reading>
125 (min.)
E
15 (min.)
5 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
A
BC32 (tPHL)
BC32 (tPLH)
OC (F245), RD
F245
(tPZH/tPZL)
External memory
data output A (F245)
F245
(tPHZ/tPLZ)
D
<When writing>
125 (min.)
E
35 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
D
A
BC32 (tPLH)
OC (F245), WO, WE
F245
(tPHL/tPLH)
External memory
data output B (F245)
F245
(tPHZ/tPLZ)
D
(Unit : ns)
Fig. 17.1.18 Timing chart for sample circuit using bus buffers (at high-speed running-1)
7751 Group User’s Manual
17–23
APPLICATIONS
17.1 Memory expansion
M37751
CNVSS
A1–A7
Address bus
AC573
BYTE
D
Q
LE OE
AC573
D Q
LE OE
ALE
F245✽2
A8/D8–
A15/D15
A
B
Data bus (odd)
DIR OC
F245 ✽2
A16/D0–
A23/D7
A
Data bus (even)
B
DIR OC
BC32
E
AC04
✽3
This circuit ensures that the rising of the
write signal occurs 1.5 1 clock earlier to
extend the write hold time.
1D1Q
2D
1T
2T 2Q
AC74
1
1
AC04 ✽1
RD
R/W
WO
BHE
WE
A0
XIN
XOUT
AC32 ✽4
AC32
✽3
Circuit condition : 5 access in high-speed running
40 MHz
✽1: Use the elements of which propagation delay time is within 45 ns.
✽2, ✽3 : Use the elements of which sum of output disable time in ✽2 and
propagation delay time in ✽3 is within 15 ns, and the sum of output
enable time in ✽2 and propagation delay time in ✽3 is 5 ns or more.
✽4: Use the elements of which propagation delay time is within 40 ns.
Fig. 17.1.19 Example for using bus buffer (at high-speed running-2 : connecting with memory requiring
long hold time for write)
17–24
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
<When reading>
125 (min.)
E
15 (min.)
5 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
A
AC32 (tPHL)
AC32 (tPLH)
BC32 (tPHL)
BC32 (tPLH)
F245
(tPZH/tPZL)
F245
(tPHZ/tPLZ)
RD
OC (F245)
External memory
data output A (F245)
D
<When writing>
1
1
125 (min.)
E
1Q (AC74)
AC04 (tPLH)+AC74 (tPLH)
2Q (AC74)
BC32 (tPHL)
BC32 (tPLH)
OC (F245)
AC32 ✕ 2(tPLH)
WO, WE
35 (max.)
A8/D8–A15/D15
A16/D0–A23/D7
A
External memory
data output B (F245)
D
F245
(tPHL/tPLH)
F245
(tPHZ/tPLZ)
D
Write hold time
(Unit : ns)
Fig. 17.1.20 Timing chart for sample circuit using bus buffers (at high-speed running-2)
7751 Group User’s Manual
17–25
APPLICATIONS
17.1 Memory expansion
17.1.4 Example of memory expansion
(1) Example of SRAM expansion (minimum model)
Figure 17.1.21 shows a memory expansion example (minimum model) using a 32-Kbyte SRAM in the
memory expansion mode at the low-speed running. Figure 17.1.22 shows the timing chart for this
example.
Figure 17.1.23 shows a memory expansion example (minimum model) using a 32-Kbyte SRAM in the
memory expansion mode at the high-speed running. Figure 17.1.24 shows the timing chart for this
example.
M37751
BYTE
AC32 ✽1 M5M5256CP-70LL
A14
S
CNVSS
A0–A13
A0–A13
A14
D0–D7
D0–D7
OE
BHE
✽1, ✽2: Use the elements of which propagation
delay time is within 18 ns.
Memory map
WE
000016
008016
Open
E
AC32 ✽2
R/W
SFR area
Internal RAM area
088016 External RAM
area
(M5M5256CP)
400016
Internal ROM area
XIN
XOUT
25 MHz
FFFF16
Circuit condition : 3 access in low-speed running
Fig. 17.1.21 Example of SRAM expansion (minimum model at low-speed running)
17–26
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
<When reading>
135 (min.)
E, OE
12 (min.)
A0–A14
A
18 (min.)
5 (max.)
D0–D7
(A)
(A)
tsu(P0A/P1A/P2A-P1D/P2D) = 135
S
AC32 (tPHL)
AC32 (tPLH)
ta(S)
ta(AD)
External RAM
data output
15 (max.)
(Kit guaranteed)
D
tsu(P2D-E) ≥ 30
ta(OE)
<When writing>
135 (min.)
E, OE
A0–A14
A
A
35 (max.)
D0–D7
(A)
AC32 (tPHL)
18 (min.)
D
tsu(D) ≥ 30
(A)
AC32 (tPLH)
WE
AC32 (tPHL)
AC32 (tPLH)
S
(Unit : ns)
Fig. 17.1.22 Timing chart for SRAM expansion example (minimum model at low-speed running)
7751 Group User’s Manual
17–27
APPLICATIONS
17.1 Memory expansion
M37751
BYTE
AC32 ✽1 M5M5256CP-70LL
A14
S
CNVSS
A0–A13
A0–A13
A14
D0–D7
D0–D7
OE
BHE
✽1, ✽2: Use the elements of which propagation
delay time is within 15 ns.
Memory map
WE
000016
008016
Open
E
AC32 ✽2
R/W
SFR area
Internal RAM area
088016 External RAM
area
(M5M5256CP)
400016
Internal ROM area
XIN
XOUT
40 MHz
FFFF16
Circuit condition : 5 access in high-speed running
Fig. 17.1.23 Example of SRAM expansion (minimum model at high-speed running)
17–28
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
<When reading>
125 (min.)
E, OE
40 (min.)
15 (min.)
5 (max.)
A0–A14
(A)
(A)
tsu(P0A/P1A/P2A-P1D/P2D) = 150
S
AC32 (tPHL)
AC32 (tPLH)
ta(S)
ta(AD)
15 (max.)
(Kit guaranteed)
External RAM
data output
D
tsu(P2D-E) ≥ 30
ta(OE)
<When writing>
125 (min.)
E, OE
A0–A14
A
35 (max.)
D0–D7
(A)
15 (min.)
D
AC32 (tPHL)
tsu(D) ≥ 30
(A)
AC32 (tPLH)
W
AC32 (tPHL)
AC32 (tPLH)
S
(Unit : ns)
Fig. 17.1.24 Timing chart for SRAM expansion example (minimum model at high-speed running)
7751 Group User’s Manual
17–29
APPLICATIONS
17.1 Memory expansion
(2) Example of ROM expansion (maximum model)
Figure 17.1.25 shows a memory expansion example (maximum model) using a 1-Mbits ROM in the
microprocessor mode. Figure 17.1.26 shows the timing chart for this example.
Figure 17.1.27 shows a memory expansion example (maximum model) using a 1-Mbits ROM in the
microprocessor mode. Figure 17.1.28 shows the timing chart for this example.
M5M27C102K-12
M37751
CNVSS
BYTE
Address bus
A1–A7
A8/D8–
A15/D15
A1–A16
AC573 ✻1
D Q
✽1: Use the elements of which propagation
delay time is within 15 ns.
✽2: Use the elements of which propagation
delay time is within 23 ns.
A0–A15
A8–A15
LE
Memory map
AC573
A16/D0
ALE
D1–D7
D
000016
008016
A16
Q
LE
Data bus
D0–D15
D0–D15
OE
E
Internal RAM
area
088016
CE
External ROM
area
AC04 ✻2
R/W
XIN
SFR area
(M5M27C102K)
XOUT
1FFFF16
25 MHz
Circuit condition : 3 access in low-speed running
Fig. 17.1.25 Example of ROM expansion (maximum model at low-speed running)
17–30
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
<When reading>
135 (min.)
E, OE
12 (min.)
A8/D8–A15/D15
A16/D0
5 (max.)
18 (min.)
A
A
20 (min.)
R/W
18 (max.)
tsu(P0A/P1A/P2A-P1D/P2D) = 135
ta(AD)+AC573 (tPHL/tPLH)
AC04 (tPHL)
AC04 (tPLH)
CE
ta(OE)
External ROM
data output
15 (max.)
( Kit guaranteed )
D
ta(CE)
tsu(P1D/P2D-E) ≥ 30
(Unit : ns)
Fig. 17.1.26 Timing chart for ROM expansion example (maximum model at low-speed running)
7751 Group User’s Manual
17–31
APPLICATIONS
17.1 Memory expansion
M5M27C102K-12
M37751
CNVSS
Address bus
A1–A7
BYTE
A8/D8–
A15/D15
A1–A16
A0–A15
AC573 ✻1
D Q
✽1: Use the elements of which propagation
delay time is within 30 ns.
✽2: Use the elements of which propagation
delay time is within 35 ns.
A8–A15
LE
Memory map
AC573
A16/D0
ALE
D1–D7
D
000016
008016
A16
Q
LE
Data bus
D0–D15
E
CE
External ROM
area
AC04 ✻2
R/W
XIN
Internal RAM
area
088016
D0–D15
OE
SFR area
(M5M27C102K)
XOUT
1FFFF16
40 MHz
Circuit condition : 5 access in high-speed running
Fig. 17.1.27 Example of ROM expansion (maximum model at high-speed running)
<When reading>
125 (min.)
E, OE
40 (min.)
A8/D8–A15/D15
A16/D0
5 (max.)
15 (min.)
A
A
45 (min.)
R/W
15 (max.)
tsu(P0A/P1A/P2A-P1D/P2D) = 150
ta(AD)+AC573 (tPHL/tPLH)
AC04 (tPHL)
AC04 (tPLH)
CE
15 (max.)
( Kit guaranteed )
ta(OE)
External ROM
data output
D
ta(CE)
tsu(P1D/P2D-E) ≥ 30
(Unit : ns)
Fig. 17.1.28 Timing chart for ROM expansion example (maximum model at high-speed running)
17–32
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
(3) Example of ROM and SRAM expansion (maximum model)
Figure 17.1.29 shows a memory expansion example (maximum model) using two 32-Kbytes ROM
and two 32-Kbytes SRAM in the microprocessor mode at the low-speed running. Figure 17.1.30
shows the timing chart for this example.
Figure 17.1.31 shows a memory expansion example (maximum model) using two 32-Kbytes ROM
and two 32-Kbytes SRAM in the microprocessor mode at the high-speed running. Figure 17.1.32
shows the timing chart for this example.
M37751
M5M5256CP-70LL
M5M27C256AK-15
CNVSS
A1–A7
BYTE
A8/D8–
A15/D15
Address bus
A8–A15
AC573 ✻2
LE
A0–A14
ALE
A1–A15
AC573
A16/D0
D Q
CE
CE
D Q
✻1
AC04
S
A0–A14
A0–A14
A1–A15
S
A0–A14
A1–A15
A1–A15
✻2
A16
D8–D15
D0–D7
D0–D7
LE
D8–D15
D0–D7
OE
D0–D7
DQ1–DQ8
OE
OE
W
DQ1–DQ8
OE
W
Data bus (odd)
Data bus (even)
D1–D7
AC04
AC32 ✽3
RD
R/W
E
WE
A0
WO
BHE
XIN
XOUT
Memory map
AC32
000016
008016
21 MHz
Circuit condition : 3 access in low-speed running
088016
SFR area
Internal
RAM area
External
ROM area
(M5M27C256AK ✕2)
✽1: Use the elements of which propagation delay time is within 80 ns.
✽2: Use the elements of which propagation delay time is within 23 ns.
✽3: Use the elements of which propagation delay time is within 10.6 ns.
1000016
External
RAM area
(M5M5256CP ✕ 2)
1FFFF16
Fig. 17.1.29 Example of ROM and SRAM expansion (maximum model at low-speed running)
7751 Group User’s Manual
17–33
APPLICATIONS
17.1 Memory expansion
<When reading>
165.4 (min.)
E
19.6 (min.)
A1–A7
A
A
5 (max.)
A8/D8–A15/D15
A16/D0
A
A
tsu(P0A/P1A/P2A–P1D/P2D) = 173
AC573 (tPHL)
CE, S
25.6 (min.)
AC04 (tPHL)
S
CE
ta(S)
AC32 (tPLH)
OE
AC32 (tPHL)
ta(OE)
15 (max.)
(Kit guaranteed)
External memory
data output
D
tsu(P1D/P2D-E) ≥ 30
ta(AD), ta(CE)
<When writing>
165.4 (min.)
E
19.6 (min.)
A1–A7
A8/D8–A15/D15
A16/D0, D1–D7
A
A
A
D
tsu(D) ≥ 30
35 (max.)
A
25.6 (min.)
AC573 (tPHL)+AC04 (tPHL)
S
AC32 (tPHL)
AC32 (tPLH)
WE, WO
(Unit: ns)
Fig. 17.1.30 Timing chart for ROM and SRAM expansion example (maximum model at low-speed
running)
17–34
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
M37751
M5M5256CP-70LL
M5M27C256AK-12
CNVSS
A1–A7
BYTE
A8/D8–
A15/D15
Address bus
AC573 ✽2
A8–A15
CE
CE
D Q
LE
A0–A14
ALE
A1–A15
✽1
AC04
S
A0–A14
A0–A14
A1–A15
S
A0–A14
A1–A15
A1–A15
✽2
AC573
A16/D0
D Q
A16
D8–D15
D0–D7
D0–D7
LE
OE
D8–D15
D0–D7
OE
D0–D7
DQ1–DQ8
OE
W
DQ1–DQ8
OE
W
Data bus (odd)
Data bus (even)
D1–D7
AC04
BC32 ✽3
RD
R/W
E
WE
A0
WO
BHE
XIN
✽4
AC32
XOUT
Memory map
000016
008016
31 MHz
Circuit condition : 4 access in high-speed running
088016
SFR area
Internal
RAM area
External
ROM area
(M5M27C256AK ✕2)
✽1: Use the elements of which propagation delay time is within 50 ns.
✽2: Use the elements of which propagation delay time is within 30 ns.
✽3: Use the elements of which propagation delay time is within 7.2 ns.
✽4: Use the elements of which propagation delay time is within 22.2 ns.
1000016
External
RAM area
(M5M5256CP✕ 2)
1FFFF16
Fig. 17.1.31 Example of ROM and SRAM expansion (maximum model at high-speed running)
7751 Group User’s Manual
17–35
APPLICATIONS
17.1 Memory expansion
<When reading>
104 (min.)
E
61.7 (min.)
A1–A7
A
A
5 (max.)
A8/D8–A15/D15
A16/D0
A
A
tsu(P0A/P1A/P2A-P1D/P2D) = 150
AC573 (tPHL)
CE, S
CE
22.2 (min.)
AC04 (tPHL)
S
BC32 (tPHL)
BC32 (tPLH)
OE
ta(S)
15 (max.)
(Kit guaranteed)
ta(OE)
External memory
data output
D
tsu(P1D/P2D-E) ≥ 30
ta(AD), ta(CE)
<When writing>
104 (min.)
E
61.7 (min.)
A
A1–A7
A8/D8–A15/D15
A16/D0, D1–D7
A
D
A
tsu(D) ≥ 30
35 (max.)
A
22.2 (min.)
AC573 (tPHL)+AC04 (tPHL)
S
AC32 (tPHL)
AC32 (tPLH)
WE, WO
(Unit: ns)
Fig. 17.1.32 Timing chart for ROM and SRAM expansion example (maximum model at high-speed
running)
17–36
7751 Group User’s Manual
APPLICATIONS
17.1 Memory expansion
17.1.5 Example of I/O expansion
(1) Example of port expansion circuit using M66010FP
Figure 17.1.33 shows an example of a port expansion circuit using the M66010FP. Although Figure
17.1.33 is an expansion example in the high-speed running, when using 1.923 MHz or less frequency
for Serial I/O transfer clock, the same expansion is possible regardless of the bus cycle.
About Serial I/O control in this expansion example is described below.
In this example, 8-bit data transmission/reception is performed 3 times by using UART0 and 24-bit
port expansion is realized. Setting of UART0 is described below:
● Clock synchronous serial I/O mode: Transmission/Reception enable state
● Internal clock is selected. Transfer clock frequency is 1.66 MHz.
● LSB first
The control process is described below:
➀ Output “L” level from port P4 5. (Expansion I/O ports of M66010FP become floating state by this
signal. )
➁ Output “H” level from port P4 5.
➂ Output “L” level from port P4 4.
➃ Transmit/Receive 24-bit data by using UART0.
➄ Output “H” level from port P4 4.
Figure 17.1.34 shows serial transfer timing between M37751 and M66010FP.
7751 Group User’s Manual
17–37
APPLICATIONS
17.1 Memory expansion
M37751
M66010FP
TxD0
DI
CNVSS
RxD0
DO
BYTE
CLK0
CLK
P44
CS
P45
S
RTS0
A0–A7
Open
VCC
A8/D8–
A15/D15
GND
A16/D0–
A23/D7
ALE
E
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
Expanded I/O port
1
R/W
BHE
Circuit condition: •UART0 used in clock synchronous serial I/O mode
•Internal clock selected
XIN
XOUT
•Frequency of transfer clock =
40 MHz
Fig. 17.1.33 Example of port expansion circuit using M66010FP
17–38
7751 Group User’s Manual
f4
2 (2 + 1)
= 1.66 MHz
CS
P44
7751 Group User’s Manual
D2
Expanded I/O port
Expanded I/O port D24
to
D1
DO
RXD0
Expanded I/O port
DI
TXD0
CLK0 CLK
S
P45
DI1
DO3
DO4
DO5
DO6
DI2
DI3
DI4
DI5
DI6
DI7
DO7
DI8
DO8
✽ Expanded I/O ports are N- channel open- drain output type.
DI24
DI2
DI1
DO2
Serial outputting data of shift register 1
DO1
Inputting serial data to shift register 2
Inputting data of expanded I/O ports to shift register 1
Terminating floating of expanded I/O ports
DI20
DO20
DI22
DO22
DI23
DO23
DI24
DO24
DO24
DO2
DO1
: M37751’s pin name
(The others are M66010FP’s pin name and operation.
DI21
DO21
Outputting data of shift register 2 to
expanded I/O ports
APPLICATIONS
17.1 Memory expansion
Fig. 17.1.34 Serial transfer timing between M37751 and M66010FP
17–39
APPLICATIONS
17.1 Memory expansion
MEMORANDUM
17–40
7751 Group User’s Manual
CHAPTER 18
PROM VERSION
18.1 EPROM mode
18.2 Usage precaution
PROM VERSION
In the PROM version, programming/reading to and from the built-in PROM can be performed by using a
general-purpose PROM programmer and a programming adapter.
The PROM version has the following two types :
●One time PROM version
Programming to the PROM can be performed once.
This version is suitable for a small quantity of and various productions.
●EPROM version
Programming to the PROM can be performed repeatedly because a program can be erased by exposing
the erase window on the top of the package to an ultraviolet light source.
This version can be used only for program development, evaluation only.
The PROM version have the same functions as the mask ROM version except that the former have a builtin PROM. Table 18.1.1 lists the product expansion of the PROM version.
Table 18.1.1 Product expansion of PROM version
Type name
PROM size
M37751E6C-XXXFP
One time PROM 49152 bytes
(M37751E6CFP)
EPROM 49152 bytes
M37751E6CFS
18–2
7751 Group User’s Manual
RAM size
2048 bytes
PROM VERSION
18.1 EPROM mode
18.1 EPROM mode
The PROM version can select the normal operating mode which performs the same operation as that of the
mask ROM version, or the EPROM
mode which enables to program/read to/from the built-in PROM.
______
When “L” level is input to the RESET pin, the PROM version enters the EPROM mode.
18.1.1 Pin description
Table 18.1.2 lists the pin description in the EPROM mode.
Table 18.1.2 Pin description in EPROM mode
Functions
Pin
Name
Input/Output
Apply
5
V
±
10%
to
V CC pin, and 0 V to VSS pin.
VCC, V SS
Power source input
––
Apply V PP level when programming or verifying.
VPP input
CNVSS
Input
BYTE
______
RESET
Reset input
Input
Connect to V SS pin.
Input
Connect a ceramic resonator or a quartz-crystal
oscillator between X IN and X OUT pins. When an
external generated clock is input, the clock must
be input to XIN pin, and XOUT pin must be left open.
XIN
Clock input
XOUT
Clock output
Output
Enable output
Output
AVCC, AV SS Analog power source input
––
_
E
Open.
Connect AV CC pin to V CC pin and AV SS pin to VSS pin.
VREF
Reference voltage input
Input
Connect to V SS pin.
P00–P0 7
P10–P1 7
Address input (A0–A7)
Input
Address input (A8–A15)
P20–P2 7
Data input/output (D0–D7)
Input
I/O
Input pins for A 0–A7 of addresses.
Input pins for A 8–A15 of addresses.
P30–P3 3
Input port P3
Input
Connect to VSS pin.
P40–P4 7
Input port P4
Input
Connect to VSS pin.
_____
P50
Control input
Input
P5 0 functions as ___
PGM input pin.
P5 1 functions as OE input pin.
P51
P52
P53–P5 6
I/O pins for data D 0–D 7.
___
P5 2 functions as CE input pin.
Connect to V CC pin.
Input port P5
Connect to V SS pin.
P57
P60–P6 7
Input port P6
Input
P70–P7 7
Input port P7
Input
P80–P8 7
Input port P8
Input
Connect to V SS pin.
7751 Group User’s Manual
18–3
PROM VERSION
18.1 EPROM mode
18.1.2 Programming/reading
EPROM mode can perform programming/reading to and from the built-in PROM with the same manner as
M5M27C101K. However, there is no device identification code. Accordingly, programming conditions must
be set carefully. Perform the programming to addresses 1400016 to 1FFFF 16.
Table 18.1.3 lists the pin correspondence with M5M27C101K. Figure 18.1.1 shows the pin connections in
EPROM mode. Table 18.1.4 lists the built-in PROM states in EPROM mode.
Table 18.1.3 Pin correspondence with M5M27C101K
Vcc
M37751E6C-XXXFP
(M37751E6CFP)
M37751E6CFS
Vcc
VPP input
CNVss, BYTE
VPP
Vss
Vss
Address input
P0, P1
Vss
A0–A15
Data I/O
P2
P52
D0–D 7
P51
OE
P50
PGM
__
CE input
M5M27C101K
Vcc
CE
__
OE input
____
PGM input
18–4
7751 Group User’s Manual
PROM VERSION
18.1 EPROM mode
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7/ADTRG
VSS
AVSS
VREF
AVCC
VCC
P80/CTS0/RTS0
P81/CLK0
P82/RxD0
P83/TxD0
VCC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
OE
PGM
1
64
2
63
3
62
4
61
5
60
M37751E6C-XXXFP
CE
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
P42/ 1
P41/RDY
6
7
8
9
10
11
12
13
14
15
16
17
18
19
59
58
57
56
55
54
53
52
51
50
49
48
47
46
20
45
21
44
22
43
23
42
24
41
P84/CTS1/RTS1
P85/CLK1
P86/RxD1
P87/TxD1
P00/A0
P01/A1
P02/A2
P03/A3
P04/A4
P05/A5
P06/A6
P07/A7
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A16/D0
P21/A17/D1
P22/A18/D2
P23/A19/D3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D7
D6
D5
D4
✽
VPP
P40/HOLD
BYTE
CNVSS
RESET
XIN
XOUT
E
VSS
P33/HLDA
P32/ALE
P31/BHE
P30/R/W
P27/A23/D7
P26/A22/D6
P25/A21/D5
P24/A20/D4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS
✽ : Connect an oscillating circuit.
: EPROM pins
Outline : 80P6N-A
Fig. 18.1.1 Pin connections in EPROM mode
7751 Group User’s Manual
18–5
PROM VERSION
18.1 EPROM mode
Table 18.1.4 Built-in PROM state in EPROM mode
Pin name
CE
OE
PGM
VPP
Vcc
Data I/O
Read-out
VIL
VIL
✕
5 V
5 V
Output
Output
disable
VIL
VIH
VIH
✕
✕
✕
5 V
5 V
5 V
5 V
Floating
Floating
Program
VIL
VIH
VIL
12.5 V
6 V
Input
Program verify
VIL
VIL
VIH
12.5 V
6 V
Output
Program disable
VIH
VIH
VIH
12.5 V
6 V
Floating
Mode
✕ : It may be V IL or V IH.
(1) Read ___
___
When CE and OE pins are set to “L” level and an address is input to address input pins, the data
of the ___
specified___
address, input address, is output externally from data I/O pins.
When CE and OE pins are set to “H” level, data I/O pins enter the floating state.
(2) Program
(Write)
___
___
When CE pin is set to “L” level and OE pin is set to “H” level and V PP level is applied to V PP pin,
programming to the built-in PROM becomes possible.
Input an address to address input
pins and supply data to be programmed to data I/O pins in 8-bit
____
parallel. In this condition, when PGM pin is set to “L” level, the data is programmed at the specified
address, input address, into the built-in PROM.
(3) Erase (Possible only in EPROM version)
The contents of the built-in PROM is erased by exposing the glass window on top of the package
to an ultraviolet light which has a wave length of 2537 Angstrom. The light must be 15 J/cm2 or more.
18–6
7751 Group User’s Manual
PROM VERSION
18.1 EPROM mode
18.1.3 Programming algorithm of built-in PROM
➀
➁
➂
➃
Set Vcc = 6 V, V PP = 12.5 V, and address to 1400016.
After applying a programming pulse of 0.2 ms, check whether data can be read or not.
If the data cannot be read, apply a programming pulse of 0.2 ms again.
Repeat the procedure, which consists of applying a programming pulse of 0.2 ms and read check, until
the data can be read. Additionally, record the number of applied pulses ( χ) before the data has been
read.
➄ Apply χ pulse (0.2 ✕ χ ms) (described in ➃) as additional programming pulses.
➅ When this procedure ( ➀ to ➄) is completed, increment the address and repeat the above procedure until
the last address is reached.
➆ After programming to the last address, read data when Vcc = VPP = 5 V (or Vcc = VPP = 5.5 V).
Figure 18.1.2 shows the programming algorithm flowchart.
7751 Group User’s Manual
18–7
PROM VERSION
18.1 EPROM mode
START
ADDR = FIRST LOCATION
VCC = 6.0 V
VPP = 12.5 V
χ=0
PROGRAM ONE PULSE OF 0.2 ms
χ = χ+1
χ = 25 ?
YES
NO
FAIL
VERIFY
BYTE
VERIFY
BYTE
PASS
FAIL
DEVICE
FAILED
PASS
PROGRAM PULSE
OF 0.2χ ms DURATION
INCREMENT ADDR
NO LAST ADDR ?
YES
VCC = VPP = *5.0 V
VERIFY
ALL BYTE
FAIL
DEVICE
FAILED
PASS
DEVICE PASSED
Fig. 18.1.2 Programming algorithm flow chart
18–8
7751 Group User’s Manual
*4.5 V≤ VCC = VPP ≤ 5.5 V
PROM VERSION
18.1 EPROM mode
18.1.4 Electrical characteristics of programming algorithm
AC electrical characteristics (Ta = 25±5 °C, Vcc = 6±0.25 V, VPP = 12.5±0.3 V, unless otherwise noted)
Symbol
Limits
Parameter
Min.
tAS
Address setup time
2
tOES
OE setup time
2
tDS
Data setup time
2
tAH
tDH
Address hold time
0
2
tDFP
Output floating delay time after OE
0
tVCS
Vcc setup time
2
tVPS
V PP setup time
2
tPW
Data hold time
___
____
0.19
PGM pulse width
____
tOPW
tCES
___
tOE
Data delay time after OE
0.19
2
Additional PGM pulse width
CE setup time
___
Typ.
Max.
130
0.2
0.21
5.25
150
Unit
µs
µs
µs
µs
µs
ns
µs
µs
ms
ms
µs
ns
Programming timing diagram
Program
Verify
VIH
Address
VIL
tAS
VIH/VOH
Data
tAH
Data set
Data output valid
VIL/VOL
tDS
tDH
tDFP
VPP
VPP
VCC
VCC+1
VCC
VCC
tVPS
tVCS
VIH
CE
VIL
tCES
VIH
PGM
tOES
tOE
VIL
tPW
OE
VIH
tOPW
VIL
Switching characteristics measuring conditions
●Input voltage : VIL = 0.45 V, VIH = 2.4 V
●Input signal rise/fall time (10 % – 90 %) : ≤ 20 ns
●Reference voltage in timing measurement : Input/output “L” = 0.8 V, “H” = 2 V
7751 Group User’s Manual
18–9
PROM VERSION
18.2 Usage precaution
18.2 Usage precaution
18.2.1 Precautions on all PROM versions
●When programming to the built-in PROM, high voltage is required. Accordingly, be careful not to apply
excessive voltage to the microcomputer. Furthermore, be especially careful during power-on.
●Noise gets in easily because the built-in PROM is wired directly from CNVSS (VPP) pin. To prevent noise,
the wiring of CNVSS (V PP) pin is performed below. Figure 18.2.1 shows the wiring of CNVSS (V PP) pin.
<In single-chip or memory expansion mode>
Connect CNV SS (V PP) pin to the microcomputer’s V SS pin in the shortest possible distance.
If the wiring cannot be shortened, insert a resistor of about 5 kohms as close to CNVSS (V PP) pin as
possible. By way of this resistor, connect CNVSS (V PP) pin to V SS pin.
<In microprocessor mode>
Connect CNV SS (VPP) pin to the microcomputer’s V CC pin in the shortest possible distance.
In single-chip and
memory expansion modes
In microprocessor mode
M37751
M37751
Shortest possible
distance
Approx. 5 kohms
VCC
CNVSS(VPP)
CNVSS(VPP)
VSS
Shortest possible
distance
✽ The above processing is unnecessary for the BYTE (VPP) pin.
Figure 18.2.1 Wiring of CNVSS (VPP) pin
18–10
7751 Group User’s Manual
PROM VERSION
18.2 Usage precaution
18.2.2 Precautions on one time PROM version
One time PROM version shipped in a blank (M37751E6CFP), of which built-in PROM is programmed by
users, is also provided.
For the microcomputer, a programming test and screening are not performed in the assembly process and
the following processes. To improve their reliability after programming, we recommend to program and test
as the flow shown in Figure 18.2.2 before use.
Programming with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function check in target device
Note: Never expose to 150 °C exceeding 100 hours.
Fig. 18.2.2 Programming and test flow for One Time PROM version
18.2.3 Precautions on EPROM version
●Cover the transparent glass window with a shield or others during the read mode because exposing to
sun light or fluorescent lamp can cause erasing the programmed data.
Be careful that the shield does not touch the EPROM lead pins.
A shield to cover the transparent window is available from Mitsubishi Electric Corporation.
●Clean the transparent glass before erasing. There is a possibility that fingers’ fat and paste disturb the
passage of ultraviolet rays and affect badly the erasure capability.
●The EPROM version is a tool only for program development, evaluation only, and do not use it for the
mass product run.
7751 Group User’s Manual
18–11
PROM VERSION
18.2 Usage precaution
MEMORANDUM
18–12
7751 Group User’s Manual
CHAPTER 19
FLASH MEMORY
VERSION
19.1 Parallel input/output mode
19.2 Serial input/output mode
FLASH MEMORY VERSION
In the flash memory version M37751F6CFP, to perform program, read, and erase operations for the builtin flash memory is possible. The M37751F6CFP has the same function as the mask ROM version except
for the built–in flash memory (Note).
The M37751F6CFP can select the microcomputer mode, which is performed the same operation as the
mask ROM version, or the
flash memory mode, which enables to access to the built–in flash memory. When
______
inputting “L” level to the RESET pin, the M37751F6CFP enters the flash memory mode. In the flash memory
mode, there are two modes: the parallel input/output mode and the serial input/output mode.
Note: Ports P4 5 and P4 6 peripheral circuits are different from those of mask ROM version.
● Microcomputer mode
● Flash memory mode
Parallel input/output mode
Read–only mode
Read/write mode
Serial input/output mode
Fig. 19.1.1 Operation mode for flash memory version
P45, P46
Direction register
Data bus
Port latch
Fig. 19.1.2 Ports P45 and P4 6 peripheral circuit (flash memory version)
19–2
7751 Group User’s Manual
FLASH MEMORY VERSION
19.1 Parallel input/output mode
19.1 Parallel input/output mode
The built-in flash memory can be accessed by using a general purpose ROM programmer in the parallel
I/O mode. In this mode, the read–only mode or the read/write mode (software command control mode) can
be selected as the built–in flash memory mode with the voltage applied to the VPP (CNVSS) pin.
7751 Group User’s Manual
19–3
FLASH MEMORY VERSION
19.1 Parallel input/output mode
19.1.1 Pin description
Table 19.1.1 lists the pin description in the parallel I/O mode.
Table 19.1.1 Pin description in parallel I/O mode
Pin
Vcc, Vss
CNVss
Name
Input/Output
Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin.
Power supply
V PP input
Functions
Input
[Read-only mode]
Supply Vcc to Vcc +1.0 V.
[Read/write mode]
Supply 12 V ±5 %.
Connect to Vss pin.
RESET
External data bus width Input
select input
Input
Reset input
XIN
Clock input
Input
XOUT
Clock output
Output
E
Enable output
Output
AVcc
Analog supply input
Connect to Vcc pin.
Connect to Vss pin.
Connect to Vss pin.
P00–P0 7
P10–P1 7
Reference voltage input Input
Address input A 0 to A 7 Input
Address input A 8 to A15 Input
P20–P2 7
Data input/output D0 to D7
P30–P3 3
Input port P3
P40, P4 1
Input port P4
BYTE
______
_
AVss
VREF
Connect a ceramic resonator or quartz-crystal oscillator
between X IN and X OUT pins. When using an external
clock, the clock source must be input to X IN pin and
X OUT pin must be left open.
Left open.
These are address A0–A7 input pins.
These are address A8–A15 input pins.
Input/Output These are data D0–D 7 input/output pins.
Input
Connect to Vss pin.
Input
Connect to Vss pin.
Left open.
P42
P4 3 to P4 7
P50
Connect to Vss pin.
Connect___
to Vss pin.
Control signal input
Input
This is ___
WE signal input pin.
This is ___
OE signal input pin.
This is CE signal input pin.
P51
P52
Input port P5
Address input A 16
Connect to Vcc pin.
P54
P5 5 to P5 7
Input port P5
Connect to Vss pin.
P6 0 to P6 7
Input port P6
Input
P7 0 to P7 7
Input port P7
P8 0 to P8 7
Input port P8
Input
Input
P53
19–4
This is address A16 input pin.
Connect to Vss pin.
7751 Group User’s Manual
FLASH MEMORY VERSION
19.1 Parallel input/output mode
19.1.2 Access to built–in flash memory
In the parallel I/O mode, the built–in flash memory can be accessed with the same operation as CMOS
flash memory M5M28F101. However, because the built–in flash memory has a capacity of 48 Kbytes, use
addresses 04000 16 to 0FFFF 16 for programming and write “FF 16” to addresses 00000 16 to 03FFF 16 and
1000016 to 1FFFF 16. The M37751F6CFP does not contain a facility to read out a device identification code
by applying a high voltage to A 9 (P11) pin. Do not erratically set program conditions etc..
Table 19.1.2 lists the pin correspondence of the M37751F6CFP and the M5M28F101.
Figure 19.1.3 shows the pin connection in the parallel I/O mode.
Table 19.1.2 Pin correspondence of M37751F6CFP
and M5M28F101 (parallel I/O mode)
Vcc
VPP input
Vss
M37751F6CFP
M5M28F101
Vcc
Vcc
CNVss
VPP
Vss
Vss
Address input
P0, P1, P5 4
A 0 to A 16
Data I/O
___
P2
CE signal input
___
P52
OE signal input
___
P51
WE signal input P50
7751 Group User’s Manual
D 0 to D 7
___
CE
OE
___
___
WE
19–5
FLASH MEMORY VERSION
P84/CTS1/RTS1
P85/CLK1
P86/RxD1
P87/TxD1
P00/A0
P01/A1
P02/A2
P03/A3
P04/A4
P05/A5
P06/A6
P07/A7
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A16/D0
P21/A17/D1
P22/A18/D2
P23/A19/D3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
19.1 Parallel input/output mode
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65
40
66
39
67
38
68
37
69
36
70
35
71
34
72
M37751F6CFP
73
33
32
74
31
75
30
76
29
77
28
78
27
79
26
80
25
2
3
4
5
6
7
8
9
D4
D5
D6
D7
VSS
VPP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
WE
CE
OE
A16
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
P42/ 1
P41/RDY
1
P24/A20/D4
P25/A21/D5
P26/A22/D6
P27/A23/D7
P30/R/W
P31/BHE
P32/ALE
P33/HLDA
VSS
E
XOUT
XIN
RESET
CNVSS
BYTE
P40/HOLD
✽
VCC
P83/TxD0
P82/RxD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
Outline : 80P6N-A
✽ : Connect to oscillation circuit.
Fig. 19.1.3 Pin connection in parallel I/O mode
19–6
7751 Group User’s Manual
FLASH MEMORY VERSION
19.1 Parallel input/output mode
19.1.3 Read–only mode
When connecting shown in Figure 19.1.3 and V PPL level is applied to the VPP pin, the built–in flash memory
operates at the read–only mode. In the read–only mode, the built–in flash memory becomes read, output
disable, or standby state depending on the control signals. In this mode, the contents of the built–in flash
memory can be read. Table 19.1.3 lists the states of the built–in flash memory.
Table 19.1.3 States of control signals and built–in flash memory in read–only mode
___
___
___
CE
OE
WE
VPP
Data I/O
Read
VIL
VIL
VIH
VPPL
Output
Output disable
Standby
VIL
VIH
Floating
✕
VIH
✕
VPPL
VIH
VPPL
Floating
Pin
State
Note: ✕ can be V IL or V IH.
(1) Read
When inputting the address of a memory location to be read and the control signals at the timing
shown in Figure 19.1.4, data of the specified address (input address) is output to an external.
A0–A16
Read address
tRC
CE
OE
tWRR
ta(CE)
WE
ta(OE)
D0–D7
tDF
tOH
Floating
Data
Floating
tOLZ
tCLZ
Read data output
ta(AD)
Fig. 19.1.4 Read timing
7751 Group User’s Manual
19–7
FLASH MEMORY VERSION
19.1 Parallel input/output mode
(2) Output disable
The microcomputer enters the read disable state.
(3) Standby
The microcomputer enters the power–saving state and the supply current decreases.
19–8
7751 Group User’s Manual
FLASH MEMORY VERSION
19.1 Parallel input/output mode
19.1.4 Read/write (software command control) mode
When connecting shown in Figure 19.1.3 and VPPH level is applied to the VPP pin, the built–in flash memory
operates at the read/write mode. In the read/write mode, the built–in flash memory becomes read, output
disable, standby or program state depending on the control signals. In this mode, program, read, and erase
operations can be performed to the built–in flash memory. Table 19.1.4 lists the states of the built–in flash
memory.
Table 19.1.4 States of control signals and built–in flash memory in read/write mode
State
Read
Pin
___
___
___
CE
OE
WE
VPP
Data I/O
VIL
VIL
VIH
VIH
VIH
VPPH
Output
VPPH
VPPH
Floating
Floating
VPPH
Input
Output disable
VIL
Standby
VIH
✕
✕
Program
VIL
VIH
VIL
Notes 1: ✕ can be V IL or V IH .
2: Refer to “(5) Software command” for read and write states.
(1) Read
When executing the read command or program verify command etc., the read mode is used. (Refer
to “(5) Software command.”)
(2) Output disable
The microcomputer enters the read disable state.
(3) Standby
The microcomputer enters the power–saving state and the supply current decreases.
(4) Program
When inputting the command code or program data etc., the program mode is used. (Refer to “(5)
Software command.”)
7751 Group User’s Manual
19–9
FLASH MEMORY VERSION
19.1 Parallel input/output mode
(5) Software command
In the read/write mode, the built–in flash memory is accessed by input (execution) of the software
command.
Table 19.1.5 lists the software command. The software command is executed by data input/output
in the first and second cycles. The command code is input to select the operation of the built–in flash
memory in the first cycle. The data etc. are input/output in the second cycle.
The following explains each software command.
Table 19.1.5 Software command and input/output information
First cycle
Second cycle
Software command
Address input Data (command code) input Address input
Data I/O
✕
Read address
Read
0016
Read data output
✕
Program address
Program
4015
Program data input
Program verify
Erase
Erase verify
✕
C016
✕
Verify data output
✕
2016
✕
20 16 (command code) input
Verify address
✕
A0 16
FF 16
✕
Verify data output
✕
FF16 (command code) input
✕
Device identification
ADI
9016
DDI output
Note: ✕ can be V IL or V IH.
ADI (Device identification address) : Manufacture’s code 0000016 ; device code 0000116
DDI (Device identification data) : Manufacture’s code 1C 16; device code D0 16
Reset
19–10
7751 Group User’s Manual
FLASH MEMORY VERSION
19.1 Parallel input/output mode
● Read command
Figure 19.1.5 shows the read command execution timing.
___
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code “0016” in the first cycle.
The data of the specified address (input address) is output to an external by inputting the address
and control signals in the second cycle.
The read command code which is latched into the command latch is retained until any other
command code is latched into the command latch. Accordingly, when the second cycle input over
again after the read command code is input in the first cycle, the read command is executed over
again.
The read command code is latched into the command latch after power–on.
A0–A16
Read address
tRC
tWC
CE
tRRW
OE
tCH
tCS
tWRR
tWP
WE
ta(CE)
ta(OE)
tDS
D0–D7
Floating
tDF
Floating
0016
tOH
Data
tOLZ
tDH
tCLZ
Read data output
ta(AD)
tVSC
VPP
Floating
VPPH
VPPL
First cycle
Second cycle
Fig. 19.1.5 Read command execution timing
Note: When executing any command other than the read command, input the command code
(input from the first cycle) each time the execution.
7751 Group User’s Manual
19–11
FLASH MEMORY VERSION
19.1 Parallel input/output mode
● Program command
Figure 19.1.6 shows the program command and the program verify command execution
timing.
___
The command code is latched into the internal command latch at the rising edge of the WE signal
the first cycle.
by inputting the control signals and the command code “4016” in___
The address is latched into___
the internal at the falling edge of the WE signal and the data is latched
at the rising edge of the WE signal by inputting the address, data, and control signals in the
second cycle.
___
The program is started at the rising edge of the WE signal in the second cycle and the input data
is programmed to the specified address (input address) within 10 µ s as measured by its internal
timer. Programming is performed by the byte unit.
Note: Be sure to execute a program verify command after executing the program command. If this
verification fails, execute repeatedly the program command and the program verify command
until the verification passes. (Refer to “19.1.6 Program/erase algorithm flow chart.”)
● Program verify command
This command is executed to verify the program data after executing the program command.
___
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code “C016” in the first cycle.
The data of the address where the program command is executed is output to an external by
inputting the control signals in the second cycle.
Since the address is internally latched when the program command is executed, there is no need
to input it when the program verify command is executed.
19–12
7751 Group User’s Manual
7751 Group User’s Manual
VPP
VPPL
VPPH
D0–D7
WE
OE
CE
A0–A16
Floating
tDH
4016
tDS
tWP
First cycle
tVSC
tCS
tRRW
tWC
tCH
tDH
Data
tDS
tWP
tAH
Program
Second cycle
Program data input
tCS
Floating
tWPH
tAS
Program address
tCH
Floating
tDP
Program
tCS
First cycle
tDH
C016
tDS
tWP
tWC
tCH
Program verify
Floating
tWRR
tOH
Data
Second cycle
ta(AD)
tOLZ
tCLZ
ta(OE)
ta(CE)
tRC
Floating
Verify data output
tDF
FLASH MEMORY VERSION
19.1 Parallel input/output mode
Fig. 19.1.6 Program command and program verify command execution timing
19–13
FLASH MEMORY VERSION
19.1 Parallel input/output mode
● Erase command
Figure 19.1.7 shows the erase command and the erase verify command execution timing.
___
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code “2016” in the first cycle.
___
The command code is latched into the internal command latch again at the rising edge of the WE
signal by inputting the control signals and the command ___
code “2016” again in the second cycle.
The erase operation is started at the rising edge of the WE signal in the second cycle, and the
built–in flash memory contents are collectively erased within 9.5 ms as measured by the internal
timer.
Write “0016” to all the built–in flash memory area before executing the erase command.
Note: Be sure to execute a erase verify command after executing the erase command. If this
verification fails, execute repeatedly the erase command and the erase verify command until
the verification passes. (Refer to “19.1.6 Program/erase algorithm flow chart.”)
When executing again the erase command after executing the erase verify command and
the verification fails, there is no need to write “0016 ” to the built–in flash memory.
● Erase verify command
This command is executed to verify whether or not all contents of the built–in flash memory have
been erased after executing the erase command.
___
The address is latched internally at the falling edge of the WE signal by inputting the address, the
cycle. The command code is latched into
control signals, and the command code “A016” in the first
___
the internal command latch at the rising edge of the WE signal.
The data of the specified address (input address) is output to an external by inputting the control
signals in the second cycle.
19–14
7751 Group User’s Manual
7751 Group User’s Manual
VPP
VPPL
VPPH
D0–D7
WE
OE
CE
A0–A16
Floating
tCH
tCS
Erase
Second cycle
tDH
tDH
tDS
tWP
2016
Floating
tWPH
tWC
20 16
tDS
tWP
First cycle
tVSC
tCS
tRRW
tWC
tCH
Floating
tDE
Erase
tCS
tAS
First cycle
tDH
A016
tDS
tWP
tAH
Verify address
tCH
Erase verify
Floating
tWRR
tOH
Data
Second cycle
ta(AD)
tOLZ
tCLZ
ta(OE)
ta(CE)
tRC
Floating
Verify data output
tDF
FLASH MEMORY VERSION
19.1 Parallel input/output mode
Fig. 19.1.7 Erase command and erase verify command execution timing
19–15
FLASH MEMORY VERSION
19.1 Parallel input/output mode
● Reset command
This command is used to stop executing of program or erase safely after inputting the program or
erase command code that is, after the command code is latched into the internal command latch
in the first cycle.
Figure 19.1.8 shows the reset command execution timing.
When inputting the control signals and the command code “FF16” in the first cycle after the program
or erase command code is latched into the command
latch, the command code is latched into the
___
internal command latch at the rising edge of the WE signal.
When inputting the control signals and command code “FF 16” again in the second cycle, the
command latch is cleared to “00 16” and becomes the state where the read command code is
latched. Then, program or erase is not executed. (The contents of the built–in flash memory is not
changed.)
A0–A16
tWC
tWC
CE
OE
tCH
tCS
tWPH
tWPH
tWP
tWP
WE
tDS
D0–D7
VPP
Floating
or
4016
2016
Floating
tDS
Floating
FF16
FF16
tDH
tDH
VPPH
VPPL
First cycle
First cycle
Program or erase
Fig. 19.1.8 Reset command execution timing
19–16
tCH
tCS
7751 Group User’s Manual
Second cycle
Reset
Floating
FLASH MEMORY VERSION
19.1 Parallel input/output mode
● Device identification command
Figure 19.1.9 shows the device identification command execution timing.
___
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code “9016” in the first cycle.
The manufacture’s code “1C 16” (i.e., MITSUBISHI) is output externally when inputting an address
“00000 16” and the control signals in the second cycle. The device code “D0 16” (i.e., 1M–bit flash
memory) is output externally when inputting an address “0000116” and the control signals.
A0–A16
ADI
tWC
tRC
CE
tRRW
OE
tCH
tCS
tWRR
tWP
ta(CE)
WE
ta(OE)
tDS
Floating
tDF
tOH
D0–D7
9016
Data
tOLZ
tDH
tCLZ
DDI output
ta(AD)
tVSC
VPP
Floating
Floating
VPPH
VPPL
First cycle
Second cycle
ADI (Device identification address) : Manufacturer’s code 0000016; device code 0000116
DDI (Device identification data) : Manufacturer’s code 1C16; device code D016
Fig. 19.1.9 Device identification command execution timing
7751 Group User’s Manual
19–17
FLASH MEMORY VERSION
19.1 Parallel input/output mode
19.1.5 Electrical characteristics
DC electrical characteristics (Ta = 25 °C, VCC = 5 V±10%, unless otherwise noted)
Symbol
Test conditions
Parameter
ISB1
ISB2
ICC1
Vcc supply current (at standby)
Vcc supply current (at read)
Min.
Vcc = 5.5 V, CE = V IH
Vcc = 5.5 V,
CE = Vcc±0.2 V
Vcc = 5.5 V, CE = V IL,
t RC = 150 ns, Iout = 0 mA
V PP = V PP H
V PP = V PP H
0 ≤ V PP ≤ Vcc+1.0 V
V PP = V PP H
V PP = V PP H
V PP = V PP H
Limits
Typ.
Max.
1
Unit
mA
100
µA
30
mA
mA
30
mA
30
µA
10
µA
IPP1
VPP supply current (at read)
100
µA
100
mA
Vpp supply current (at program)
IPP2
30
mA
IPP3
Vpp supply current (at erase)
30
V
pp
supply
voltage
(read-only
mode)
VPPL
Vcc
Vcc+1.0 V
V
12.6
Vpp supply voltage (read/write mode)
VPPH
12.0
11.4
Note: V IH/V IL, V OH/VOL, and I IH/I IL for the control input, address input, and data input/output pins conform to
standards for microcomputer modes (memory expansion and microprocessor modes).
ICC2
ICC3
Vcc supply current (at program)
Vcc supply current (at erase)
AC electrical characteristics (Ta = 25 °C, VCC = 5 V±10%, unless otherwise noted)
Read–only mode
Symbol
t RC
t a(AD)
t a(CE)
t a(OE)
t CLZ
t OLZ
t DF
t OH
t WRR
19–18
Parameter
Read cycle time
Address access time
___
CE
access time
___
OE access time
___
Output enable time (after ___
CE)
Output enable time (after OE)
___
Output floating time (after OE)
___ ___
Output efficiency time (after CE, OE, address)
Write recovery time (before read)
7751 Group User’s Manual
Limits
Min.
Max.
150
150
150
55
0
0
35
0
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
FLASH MEMORY VERSION
19.1 Parallel input/output mode
Read/write mode
Symbol
Parameter
t WC
Write cycle time
t AS
Address setup time
t AH
Address hold time
t DS
Data setup time
t DH
Data hold time
t WRR
Write recovery time (before read)
t RRW
Read recovery time (before write)
___
t CS
CE setup time
___
t CH
CE hold time
t WP
Write pulse time
t WPH
Write pulse waiting time
t DP
Program time
t DE
Erase time
t VSC
V PP setup time
Note: The read timing is same as the read only mode.
7751 Group User’s Manual
Limits
Min.
Max.
150
0
60
50
10
6
0
20
0
60
20
10
9.5
1
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
ms
µs
19–19
FLASH MEMORY VERSION
19.1 Parallel input/output mode
19.1.6 Program/erase algorithm flow chart
Program
Erase
START
START
VCC = 5V
VPP = VPPH
VCC = 5V
VPP = VPPH
ADDR = FIRST LOCATION
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADDR = FIRST LOCATION
X=0
DURATION = 10 µs
X=X+1
WRITE PROGRAM-VERIFY
COMMAND
C016
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
DURATION = 9.5 ms
DURATION = 6 µs
X=X+1
YES
X = 25 ?
WRITE ERASE-VERIFY
COMMAND
NO
FAIL
VERIFY
BYTE ?
PASS
PASS
INCREMENT
ADDR
NO
VERIFY
BYTE ?
DURATION = 6 µs
FAIL
X = 1000 ?
LAST
ADDR ?
YES
NO
YES
FAIL
WRITE READ
COMMAND
A016
VERIFY
BYTE ?
0016
PASS
PASS
VPP = VPPL
DEVICE
PASSED
INCREMENT
ADDR
DEVICE
FAILED
NO
VERIFY
BYTE ?
FAIL
LAST
ADDR ?
YES
WRITE READ
COMMAND
0016
VPP = VPPL
DEVICE
PASSED
19–20
7751 Group User’s Manual
DEVICE
FAILED
FLASH MEMORY VERSION
19.2 Serial input/output mode
19.2 Serial input/output mode
In the serial I/O mode, the contents of the built–in flash memory can be reprogrammed with the state
mounting the microcomputer on the board.
19.2.1 Pin description
Table 19.2.1 lists the pin description in the serial I/O mode.
7751 Group User’s Manual
19–21
FLASH MEMORY VERSION
19.2 Serial input/output mode
Table 19.2.1 Pin description in serial I/O mode
Name
Input/Output
Pin
Power
supply
Vcc, Vss
V PP input
Input
CNVss
Functions
Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin.
Supply 12 V ±5 %.
External data bus width Input
select input
Connect to Vss pin or Vcc pin.
RESET
Reset input
Input
Connect to Vss pin.
XIN
Clock input
Input
XOUT
Clock output
Output
Connect a ceramic resonator or quartz-crystal oscillator
between X IN and X OUT pins. When using an external
clock, the clock source must be input to X IN pin and
X OUT pin must be left open.
E
Enable output
Output
AVcc
Analog supply input
BYTE
______
_
Connect to Vcc pin.
AVss
VREF
P0 0–P07
“H” level is output.
Reference voltage input Input
Input
Input port P0
P1 0–P17
P2 0–P27
Input port P1
Input
Input port P2
Input
P3 0–P33
Input port P3
Input
P4 0
Input port P4
Input
Connect to Vss pin.
Input level between Vss and Vcc or open.
Input “H” or “L” level, or open.
Input “H” or “L” level, or open.
P4 1
P4 2
Clock φ 1 is output.
P4 3
P4 4
Input “H” or “L” level, or open.
BUSY output
Output
This pin is BUSY signal output.
P4 5
SDA I/O
SCLK input
I/O
Input
This pin is serial data I/O.
P4 6
P4 7
Input port P4
P5 0
Input port P5
Control signal input
Input
Input “H” or___
“L” level, or open.
P5 1
P5 2 to P5 7
This pin is OE signal input.
Input “H” or “L” level, or open.
Input port P5
P6 0 to P6 7
Input port P6
P7 0 to P7 7
Input port P7
Input
Input
P8 0 to P8 7
Input port P8
Input
19–22
This pin is serial clock input.
Input “H” or “L” level, or open.
Input “H” or “L” level, or open.
7751 Group User’s Manual
FLASH MEMORY VERSION
19.2 Serial input/output mode
19.2.2 Access to built–in flash memory
Figure 19.2.1 shows the pin connection in the serial I/O mode.
___
When inputting “H” level to the SDA (P45), SCLK (P4 6), and OE signal input (P51) pins, and after that,
applying the VPPH level to the V PP (CNVSS), the built–in flash memory operates in the serial I/O mode. The
software command, address, and data required for operation of the built–in flash memory are input/output
by the clock synchronous serial transfer in this mode. The software command, address, and program data
are taken from SDA pin to the inside synchronously with the rising edge of the serial clock inputting to
SCLK pin. The read data, verify data, and error code are externally output from SDA pin synchronously
with the falling edge of the serial clock. The transfer is performed at 8–bit length and LSB first.
In the serial I/O mode, the built–in flash memory is accessed by inputting (execution) of the software
command. Table 19.2.2 lists the software command. To execute the software command requires twice or
four times of the transfer. In the first transfer, the command code is input for selecting the built–in flash
memory’s operation. In the second to fourth transfer, address and data etc. are input/output.
Each software command is described below.
As the capacity of the built-in flash memory is 48 Kbytes, specify addresses 4000 16 to FFFF 16 . If the
addresses except addresses 4000 16 to FFFF 16 are specified, the error occurs.
Table 19.2.2 Software command and input/output information
First transfer
Second transfer
Third transfer
Software command
(command code input)
Low-order 8 bits of High-order 8 bits of
00 16
Read
read address input read address input
Low-order 8 bits of
program address input
Verify data output
Program
40 16
Program verify
C016
Auto erase
30 16
30 16 (command
code) input
Error check
80 16
Error code output
7751 Group User’s Manual
High-order 8 bits of
program address input
Forth transfer
Read data output
Program data input
19–23
FLASH MEMORY VERSION
P84/CTS1/RTS1
P85/CLK1
P86/RxD1
P87/TxD1
P00/A0
P01/A1
P02/A2
P03/A3
P04/A4
P05/A5
P06/A6
P07/A7
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A16/D0
P21/A17/D1
P22/A18/D2
P23/A19/D3
19.2 Serial input/output mode
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65
40
66
39
67
38
68
37
69
36
70
35
71
34
72
33
M37751F6CFP
73
32
74
31
75
30
76
29
77
28
78
27
79
26
80
25
2
3
4
5
6
7
8
VSS
VPP
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDA
BUSY
SCLK
OE
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN
P56/TA3OUT
P55/TA2IN
P54/TA2OUT
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
(Note) P42/ 1
P41/RDY
1
P24/A20/D4
P25/A21/D5
P26/A22/D6
P27/A23/D7
P30/R/W
P31/BHE
P32/ALE
P33/HLDA
VSS
E
XOUT
XIN
RESET
CNVSS
BYTE
P40/HOLD
✽
VCC
P83/TxD0
P82/RxD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
Outline : 80P6N-A
✽ : Connect to the oscillation circuit.
Note : This pin outputs clock 1.
Fig. 19.2.1 Pin connection in serial I/O mode
19–24
7751 Group User’s Manual
FLASH MEMORY VERSION
19.2 Serial input/output mode
● Read command
Figure 19.2.2 shows the read command execution timing.
The command code “00 16” is input at the first transfer.
The low–order 8 bits and the___
high–order 8 bits are input at the second and third transfer.
When setting “L” level to the OE signal, the data of the specified address (input address) is read
out and latched up to the internal
data latch.
___
When returning “H” level to the OE signal and inputting the serial clock, the data which is latched
up to the data latch is output externally.
tCH
tCH
SCLK
A7
A0
SDA
A8
A1
D0
D7
5
00 0 0 00 0 0
Command code input(0016) Read address input
(Low-order)
Read address input
(High-order)
tCR
tWR
tRC
Read data output
(Note)
OE
Read
BUSY
“L”
Note: When outputting the read data, the SDA pin is switched for output at the first falling edge of the serial clock.
The SDA pin is placed in the floating state during the th(C-E) period after the last rising edge of the serial clock
(at the 8th bit).
Fig. 19.2.2 Read command execution timing
7751 Group User’s Manual
19–25
FLASH MEMORY VERSION
19.2 Serial input/output mode
● Program command
Figure 19.2.3 shows the program command execution timing.
The command code “40 16” is input at the first transfer.
The low–order 8 bits and the high–order 8 bits of the address are input at the second and third
transfer.
The data is input at the forth transfer.
Programming is started at the last rising edge of the forth transfer serial clock and the BUSY signal
becomes “H” level. The input data is programmed to the specified address (input address) within
10 µs as measured by the built–in timer and the BUSY signal becomes “L” level. Programming is
performed by the byte unit.
Note: Be sure to execute a program verify command after executing the program command. If this
verification fails, execute repeatedly the program and program verify commands until the
verification passes. (Refer to “19.2.4 Program algorithm flow chart.”)
tCH
tCH
tCH
SCLK
tPC
A0
SDA
A7
A8
A15
D0
D7
0 0 00 0 01 0
Command code input (4016)
Program address input
(Low-order)
Program address input
(High-order)
Program data input
“H”
OE
tWP
BUSY
Program
Fig. 19.2.3 Program command execution timing
19–26
7751 Group User’s Manual
FLASH MEMORY VERSION
19.2 Serial input/output mode
● Program verify command
Figure 19.2.4 shows the program verify command execution timing.
This command is executed to verify data of address where the program command has been
executed after executing the program command.
The command code
“C0 16” is input at the first transfer.
___
When setting the OE signal to “L” level, data of address where the program command has been
executed is read out
and latched to the internal data latch.
___
When returning the OE signal to “H” level and inputting the serial clock, the data which is latched
to the data latch is output externally.
Since the address is internally latched when the program command is executed, there is no need
to input it when the program verify command is executed.
SCLK
D0
D7
0 00 0 0 0 11
SDA
Command code input (C016)
tCRPV
tWR
tRC
Verify data output
(Note)
OE
Verify read
BUSY
“L”
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of
the serial clock. The SDA pin is switched in the floating state during the th(C-E) period after the
last rising edge of the serial clock (at the 8th bit).
Fig. 19.2.4 Program verify command execution timing
7751 Group User’s Manual
19–27
FLASH MEMORY VERSION
19.2 Serial input/output mode
● Auto erase command
Figure 19.2.5 shows the auto erase command execution timing.
The command code “30 16” is input at the first transfer.
The command code “30 16” is input again at the second transfer.
Erasing is started at the last rising edge of the second transfer serial clock and the BUSY signal
becomes “H” level. The BUSY signal becomes “L” by erasing all the contents of the built–in flash
memory.
Note: When executing the auto erase command once, “erase → erase verify” is performed repeatedly
internally and automatically after programming “00 16” to all memory area until erasing all the
contents of the built–in flash memory.
Accordingly, erasing is completed by executing the auto erase command once.
tCH
SCLK
SDA
tEC
0 0 0 0 11 00
00 0 0 11 00
Command code input (3016) Command code input (3016)
“H”
OE
BUSY
Auto erase
Fig. 19.2.5 Auto erase command execution timing
19–28
7751 Group User’s Manual
FLASH MEMORY VERSION
19.2 Serial input/output mode
● Error check command
Figure 19.2.6 shows the error check command execution timing.
The command code “80 16” is input at the first transfer.
When inputting the serial clock, the error information is output externally.
When an error occurs, the serial communication circuit sets the corresponding error flag to “1” and
stops operating, and the serial clock and data are not accepted (even including an error check
command). Accordingly, apply the VPPL level to the VPP pin to clear the serial I/O mode and then
apply the V PP H level again to select the serial I/O mode and initialize the serial communication
circuit. The error information is output when first executing the error check command after initializing.
Figure 19.2.7 shows the error information.
The error flag becomes “0” by executing the error check command. Be sure to execute the error
check command because the error flag is undefined after power–on.
tCH
SCLK
E0E1
0 0 00 0 0 0 1
SDA
Command code input (8016)
? ?? ?? ?
Error information
output (Note)
“H”
OE
BUSY
“L”
Note: When outputting the error information, the SDA pin is switched for output at the
first falling edge of the serial clock. The SDA pin is switched in the floating state
during the th(C-E) period after the last rising edge of the serial clock (at the 8th
bit).
Fig. 19.2.6 Error check command execution timing
7751 Group User’s Manual
19–29
FLASH MEMORY VERSION
19.2 Serial input/output mode
Command error flag (E0)
When inputting the code other than the five command codes
shown in Table 19.2.2, this flag becomes “1.”
Address error flag (E1)
When inputting the addresses other than addresses 400016
to FFFF16, this flag becomes “1.”
The contents are undefined at reading.
✽ The error flags are undefined after power-on.
✽ When executing the error check command, the error flags become “0.”
Fig. 19.2.7 Error information
19–30
7751 Group User’s Manual
FLASH MEMORY VERSION
19.2 Serial input/output mode
19.2.3 Electrical characteristics
DC electrical characteristics (Ta = 25 °C, V CC = 5 V±10%, V PP = 12 V±5%, unless otherwise noted)
Limits
Symbol
Test conditions
Parameter
Unit
Min.
Max.
Typ.
Vcc = 5.5 V, t WR = 320 ns,
Vcc supply current (at read)
I CC1
30
mA
I out = 0 mA
Vcc supply current (at program)
30
I CC2
mA
Vcc
supply
current
(at
erase)
I CC3
30
mA
V PP supply current (at read)
I PP1
100
µA
V PP supply current (at program)
I PP2
30
mA
V PP supply current (at erase)
I PP3
30
mA
VPP supply voltage (at serial I/O mode)
12.0
12.6
11.4
VPPH
V
Note: V IH/VIL, V OH/VOL, and I IH/I IL for the control signal input, BUSY output, SDA I/O, and SCLK input pins
conform to standards for microcomputer modes.
AC electrical characteristics (Ta = 25 °C, VCC = 5 V±10%, V PP = 12 V±5%, f(X IN) = 40 MHz, unless otherwise noted)
Symbol
t CH
t CR
t WR
t RC
t CRPV
t WP
t PC
t EC
t C(CK)
t W(CKH)
t W(CKL)
t r(CK)
t f(CK)
t d(C-Q)
t h(C-Q)
t h(C-E)
t su(D-C)
t h(C-D)
Parameter
Serial transmission interval time
Read waiting time after transmission
Read pulse width
Transfer waiting time after read
Waiting time before program verify
Programming time
Transfer waiting time after programming
Transfer waiting time after erase
SCLK input cycle time
SCLK “H” pulse width
SCLK “L” pulse width
SCLK rise time
SCLK fall time
SDA output delay time
SDA output hold time
SDA output hold time (only the 8th bit)
SDA input setup time
SDA input hold time
Limits
Min.
Max.
400 (Note 1)
400 (Note 1)
320 (Note 2)
400 (Note 1)
6
10
400 (Note 1)
400 (Note 1)
250
100
100
20
20
0
0
90
120 (Note 3) 200 (Note 4)
30
90
Unit
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When f(XIN) = 25 MHz or less, calculate the minimum value as the following formula 1.
1 ✕ 10
Formula 1 :
✕ 10 9
f(X IN)
2: When f(XIN) = 25 MHz or less, calculate the minimum value as the following formula 2.
1 ✕ 8
Formula 2 :
✕ 10 9
f(X IN)
3: When f(XIN) = 25 MHz or less, calculate the minimum value as the following formula 3.
1 ✕ 3
✕ 10 9
f(X IN)
4: When f(XIN) = 25 MHz or less, calculate the maximum value as the following formula 4.
1 ✕ 5
✕ 10 9
Formula 4 :
f(X IN)
Formula 3 :
7751 Group User’s Manual
19–31
FLASH MEMORY VERSION
19.2 Serial input/output mode
Timing
tC(CK)
tf(CK)
tW(CKL)
tr(CK)
tW(CKH)
SCLK
td(C-Q)
th(C-E)
th(C-Q)
SDA output
tsu(D-C) th(C-D)
SDA input
Test conditions
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
•Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC
19–32
7751 Group User’s Manual
FLASH MEMORY VERSION
19.2 Serial input/output mode
19.2.4 Program algorithm flow chart
START
VCC = 5 V
SDA = SCLK = OE = “H”
VPP = VPPH
ADDR = FIRST LOCATION
X=0
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
DURATION = 10 µs
X=X+1
WRITE PROGRAM-VERIFY
COMMAND
C016
DURATION = 6 µs
YES
X = 25 ?
NO
FAIL
VERIFY
BYTE ?
PASS
PASS
INCREMENT
ADDR
NO
VERIFY
BYTE ?
FAIL
LAST
ADDR ?
YES
WRITE READ
COMMAND
0016
VPP = VPPL
DEVICE
PASSED
7751 Group User’s Manual
DEVICE
FAILED
19–33
FLASH MEMORY VERSION
19.2 Serial input/output mode
MEMORANDUM
19–34
7751 Group User’s Manual
APPENDIX
Appendix
Appendix
Appendix
Appendix
Appendix
1.
2.
3.
4.
5.
Appendix 6.
Appendix 7.
Appendix 8.
Appendix 9.
Memory assignment
Memory assignment in SFR area
Control registers
Package outlines
Example for processing
unused pins
Hexadecimal instruction
code table
Machine instructions
Examples of noise
immunity improvement
Q & A
APPENDIX
Appendix 1. Memory assignment
Appendix 1. Memory assignment
1. During single-chip mode
00000016
SFR area
00008016
Internal RAM
2048 bytes
00087F16
Not used
00400016
Internal ROM
48 Kbytes
00FFFF16
M37751M6C-XXXFP
Type
name
M37751E6C-XXXFP
M37751E6CFS
M37751F6CFP
Fig. 1. Memory assignment during single-chip mode
20–2
7751 Group User’s Manual
APPENDIX
Appendix 1. Memory assignment
2. During memory expansion mode
SFR area
00000016
SFR area
00000216
00008016
External area
Internal RAM
area
2048 bytes
00000916
00087F16
External area
Bank 016
00400016
Internal ROM
area
48 Kbytes
00FFFF16
01000016
Bank 116
01FFFF16
External area
FF000016
Bank FF16
FFFFFF16
M37751M6C-XXXFP
Type
name
M37751E6C-XXXFP
M37751E6CFS
M37751F6CFP
Fig. 2. Memory assignment during memory expansion mode
7751 Group User’s Manual
20–3
APPENDIX
Appendix 1. Memory assignment
3. During microprocessor mode
SFR area
00000016
SFR area
00000216
00008016
External area
00000916
Internal RAM
area
2048 bytes
00087F16
Bank 016
Note: Interrupt vector table is assigned
to addresses FFD616 to FFFF16.
Set a ROM to this area.
External area
00FFFF16
01000016
Bank 116
01FFFF16
FF000016
Bank FF16
FFFFFF16
M37751M6C-XXXFP
Type
name
M37751E6C-XXXFP
M37751E6CFS
M37751F6CFP
Fig. 3. Memory assignment during microprocessor mode
20–4
7751 Group User’s Manual
APPENDIX
Appendix 2. Memory assignment in SFR area
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid data.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
State immediately after a reset
0 : “0” immediately after a reset.
1 : “1” immediately after a reset.
? : Undefined immediately after
a reset.
Address Register name
016
116
216
Port P0 register
316
Port P1 register
416 Port P0 direction register
516 Port P1 direction register
Port P2 register
616
Port P3 register
716
816 Port P2 direction register
916 Port P3 direction register
Port P4 register
A16
Port P5 register
B16
C16 Port P4 direction register
D16 Port P5 direction register
Port P6 register
E16
Port P7 register
F16
1016 Port P6 direction register
1116 Port P7 direction register
Port P8 register
1216
1316
1416 Port P8 direction register
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
1E16 A-D control register 0
1F16 A-D control register 1
0
: Always “0” at reading
?
: Always undefined at reading
0
: “0” immediately after a reset. Fix this bit to “0.”
State immediately after a reset
Access characteristics
b0
b7
b0
b7
RW
RW
RW
RW
RW
RW
0
0
0
RW
0
0
0
0
?
0
?
0
?
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
7751 Group User’s Manual
?
?
?
?
0016
0016
?
0
0016
0 0
?
?
0016
0016
?
?
0016
0016
?
?
0016
?
?
?
?
?
?
?
?
?
0 0
0 0
?
0
0
0
?
0
?
1
?
1
20–5
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid data.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
State immediately after a reset
0 : “0” immediately after a reset.
1 : “1” immediately after a reset.
? : Undefined immediately after
a reset.
Address
Register name
0 : Always “0” at reading
?
: Always undefined at reading
0
: “0” immediately after a reset. Fix this bit to “0.”
2016
2116
2216
2316
2416
2516
2616
2716
2816
2916
2A16
2B16
2C16
2D16
2E16
2F16
3016
3116
3216
3316
3416
3516
3616
3716
3816
3916
3A16
3B16
3C16
3D16
3E16
3F16
b0
20–6
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
UART0 transmit/receive mode register
UART0 baud rate register
UART0 transmit buffer register
RO
RW
UART0 transmit/receive control register 1
RO
0
0
0
UART1 transmit/receive mode register
UART1 baud rate register
0
0
0
UART1 transmit/receive control register 0 RW
UART1 transmit/receive control register 1
RO
RO
0
?
0
0
?
0
0
?
0
0
?
0
0
?
0
0
?
0
0
?
0 0
0016
?
?
?
? 1
0 0
?
0 0
0016
?
?
?
? 1
0 0
?
0 0
0
?
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
0
?
0
0
0
WO
RW
RW RO RW
0
0
?
0
?
0
RO
0
0
0
WO
RW
RW RO RW
0
0
?
0
?
0
RO
0
0
0
RW
WO
WO
UART1 transmit buffer register
0
0
?
RO
UART0 receive buffer register
UART1 receive buffer register
b0
b7
?
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
WO
WO
A-D register 0
UART0 transmit/receive control register 0
State immediately after a reset
Access characteristics
b7
RO
7751 Group User’s Manual
0
0
0
1
0
0
0
0
?
0
0
0
1
0
0
0
0
?
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid data.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
State immediately after a reset
0 : “0” immediately after a reset.
1 : “1” immediately after a reset.
? : Undefined immediately after
a reset.
Address
0
: Always “0” at reading
?
: Always undefined at reading
0 : “0” immediately after a reset. Fix this bit to “0.”
Register name
4016
4116
4216
4316
4416
4516
4616
4716
4816
4916
4A16
4B16
4C16
4D16
4E16
4F16
5016
5116
5216
5316
5416
5516
5616
5716
5816
5916
5A16
5B16
5C16
5D16
5E16
5F16
b0
WO
One-shot start register
WO
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
RW
?
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
0
0
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
RW
RW
RW
RW
RW
Timer A0 register
Timer B0 mode register
Timer B1 mode register
b0
b7
RW
Count start register
Up-down register
State immediately after a reset
Access characteristics
b7
RW
RW
RW
✽
✽
✽
RW
RW
RW
RW
WO RW ✽ RW
RW
0016
?
0 0
?
0 0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0016
0016
0016
0016
0016
? 0
? 0
? 0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
✽
0
0
0
0
0
0
✽ The access characteristics at addresses 4616 to 4F16 varies according to Timer A’s operating mode.
(Refer to “Chapter 5. TIMER A.”)
✽ The access characteristics at addresses 5016 to 5516 varies according to Timer B’s operating mode.
(Refer to “Chapter 6. TIMER B.”)
✽ The access characteristics of bit 5 at addresses 5B16 to 5D16 varies according to Timer B’s operating
mode. (Refer to “Chapter 6. TIMER B.”)
✽ The access characteristics of bit 1 at address 5E16 and its state immediately after a reset vary according
to the voltage level supplied to the CNVSS pin. (Refer to section “2.5 Processor modes.”)
7751 Group User’s Manual
20–7
APPENDIX
Appendix 2. Memory assignment in SFR area
Access characteristics
RW : It is possible to read the bit state at reading. The written value becomes valid data.
RO : It is possible to read the bit state at reading. The written value becomes invalid.
WO : The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
State immediately after a reset
0 : “0” immediately after a reset.
1 : “1” immediately after a reset.
? : Undefined immediately after
a reset.
Address
6016
6116
6216
6316
6416
6516
6616
6716
6816
6916
6A16
6B16
6C16
6D16
6E16
6F16
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
7D16
7E16
7F16
Register name
Watchdog timer register
0
: Always “0” at reading
?
: Always undefined at reading
0
: “0” immediately after a reset. Fix this bit to “0.”
b7
Access characteristics
b0
State immediately after a reset
b0
b7
(Note 1)
? (Note 2)
?
?
?
?
?
RW
Watchdog timer frequency select register
0
?
?
?
?
?
?
?
?
?
?
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
?
?
?
?
?
?
?
?
?
?
?
?
?
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
RW
RW
RW
?
?
?
0
0
0
0
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes 1: By writing dummy data to address 6016, a value “FFF16” is set to the watchdog timer. The
dummy data is not retained anywhere.
2: The value “FFF16” is set tot the watchdog timer. (Refer to “Chapter 9. WATCHDOG TIMER.”)
20–8
7751 Group User’s Manual
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
APPENDIX
Appendix 3. Control registers
Appendix 3. Control registers
The register structure of each control register assignment in the SFR area are shown on the following pages.
The view of the register structure is described below.
✽1
b7
b6
b5
b4
b3
b2
b1
b0
XXX register (Address XX16)
✕ 0
Bit
✽2
Bit name
Functions
✽3
At reset
RW
0
RW
Undefined
WO
0
RO
0
... select bit
0 : ...
1 : ...
1
... select bit
0 : ...
1 : ...
The value is “0” at reading.
2
... flag
0 : ...
1 : ...
3
Fix this bit to “0.”
0
RW
4
This bit is ignored in ... mode.
0
RW
Undefined
–
7 to 5 Nothing is assigned.
✽4
✽1
Blank
0
1
✕
: Set to “0” or “1” to according to the usage.
: Set to “0” at writing.
: Set to “1” at writing.
: Ignored depending on the specific mode or state. It may be either “0” or “1.”
: Nothing is assigned.
✽2
0
1
Undefined
: “0” immediately after a reset.
: “1” immediately after a reset.
: Undefined immediately after a reset.
✽3
RW
RO
WO
—
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written
value may be “0” or “1.”
: The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” is at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See ✽4 above.)
: It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” is at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See ✽4 above.)
The written value becomes invalid. Accordingly, the written value may be “0” or “1.”
7751 Group User’s Manual
20–9
APPENDIX
Appendix 3. Control registers
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi register (i = 0 to 8)
(Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216)
Bit
Bit name
Functions
At reset
RW
Data is input/output to/from a pin by
reading/writing from/to the corresponding bit.
Undefined
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
Port Pi0
1
Port Pi1
2
Port Pi2
3
Port Pi3
4
Port Pi4
Undefined
RW
5
Port Pi5
Undefined
RW
6
Port Pi6
Undefined
RW
7
Port Pi7
Undefined
RW
At reset
RW
0
RW
0
RW
0
RW
0 : “L” level
1 : “H” level
Note: Bits 7 to 4 of the port P3 register cannot be written and are fixed to “0” at reading.
Port Pi direction register
b7
b6
b5
b4
b3
b2
b1
b0
Port Pi direction register (i = 0 to 8)
(Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416)
Bit
Bit name
0
Port Pi0 direction bit
1
Port Pi1 direction bit
Functions
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
2
Port Pi2 direction bit
3
Port Pi3 direction bit
0
RW
4
Port Pi4 direction bit
0
RW
5
Port Pi5 direction bit
0
RW
6
Port Pi6 direction bit
0
RW
7
Port Pi7 direction bit
0
RW
Note: Bits 7 to 4 of the port P3 direction register cannot be written and are fixed to “0” at reading.
20–10
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
A-D control register 0
b7
b6
b5
b4
b3
b2
b1
b0
A-D control register 0 (Address 1E16)
Bit
0
Functions
Bit name
Analog input select bits
(Valid in one-shot and repeat
modes) (Note 1)
0 0 0 : AN0 selected
0 0 1 : AN1 selected
0 1 0 : AN2 selected
0 1 1 : AN3 selected
1 0 0 : AN4 selected
1 0 1 : AN5 selected
1 1 0 : AN6 selected
1 1 1 : AN7 selected (Note 2)
1
2
3
A-D operation mode select bit 0
4
At reset
RW
Undefined
RW
Undefined
RW
Undefined
RW
0
RW
0
RW
b2 b1 b0
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 /
Repeat sweep mode 1 (Note 3)
5
Trigger select bit
0 : Internal trigger
1 : External trigger
0
RW
6
A-D conversion start bit
0 : Stop A-D conversion
1 : Start A-D conversion
0
RW
7
A-D conversion frequency
( AD) select bit 0
0
RW
When A-D conversion frequency
( AD) select bit 1 (bit 4 at address
1F16) = “0,”
0 : f2 divided by 4, or f4 divided by 4
1 : f2 divided by 2, or f4 divided by 2
When A-D conversion frequency
( AD) select bit 1 (bit 4 at address
1F16) = “1,”
0 : f2 or f4
1 : Not selected
Notes 1: These bits are ignored in the single sweep, repeat sweep mode 0, and repeat sweep
mode 1. (They may be either “0” or “1.”)
2: When selecting an external trigger, the AN7 pin cannot be used as an analog input
pin.
3: Use the A-D operation mode select bit 1 (bit 2 at address 1F16) to select either the
repeat sweep mode 0 or repeat sweep mode 1.
4: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while
the A-D converter halts.
7751 Group User’s Manual
20–11
APPENDIX
Appendix 3. Control registers
A-D control register 1
b7
b6
b5
b4
b3
b2
b1
b0
A-D control register 1 (Address 1F16)
Bit
0
Functions
Bit name
A-D sweep pin select bits
(Valid in single sweep, repeat sweep
mode 0 and repeat sweep mode 1)
(Note 1)
1
●Single sweep mode/Repeat sweep
mode 0
At reset
RW
1
RW
1
RW
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins) (Note 2)
●Repeat sweep mode 1 (Note 3)
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
2
A-D operation mode select bit 1
(Use in repeat sweep mode 0
and repeat sweep mode 1)
(Note 4)
0 : Repeat sweep mode 0
1 : Repeat sweep mode 1
0
RW
3
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0
RW
4
A-D conversion frequency
( AD) select bit 1
Refer to A-D conversion frequency
( AD) select bit 0 (bit 7 at address
1E16)
0
RW
Undefined
–
7 to 5 Nothing is assigned.
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or
“1.”)
2: When selecting an external trigger, the AN7 pin cannot be used as an analog input
pin.
3: Analog input pins which are frequently A-D converted are selected in the repeat
sweep mode 1.
4: Fix this bit to “0” in the one-shot, repeat, and single sweep modes.
5: Writing to each bit of the A-D control register 1 must be performed while the A-D
converter halts.
20–12
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
A-D register i
●8-bit mode
(b15)
(b8)
b7
b0
b7
b0
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
Bit
Functions
7 to 0 Reads an A-D conversion result.
15 to 8 The value is “0” at reading.
●10-bit mode
(b15)
(b10)
(b8)
b7
b2
b0
b7
b0
At reset
RW
Undefined
RO
0
RO
At reset
RW
Undefined
RO
0
RO
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
Bit
Functions
9 to 0 Reads an A-D conversion result.
15 to 10 The value is “0” at reading.
7751 Group User’s Manual
20–13
APPENDIX
Appendix 3. Control registers
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
0
Functions
At reset
RW
0 0 0 : Serial I/O disabled
(P8 functions as a programmable
I/O port.)
0 0 1 : Clock synchronous serial I/O
mode
0 1 0 : Not selected
0 1 1 : Not selected
1 0 0 : UART mode
(Transfer data length = 7 bits)
1 0 1 : UART mode
(Transfer data length = 8 bits)
1 1 0 : UART mode
(Transfer data length = 9 bits)
1 1 1 : Not selected
0
RW
0
RW
0
RW
Bit name
Bit
Serial I/O mode select bits
1
2
b2 b1 b0
3
Internal/External clock select bit
0 : Internal clock
1 : External clock
0
RW
4
Stop bit length select bit
(Valid in UART mode) (Note)
0 : One stop bit
1 : Two stop bits
0
RW
5
Odd/Even parity select bit
(Valid in UART mode when
parity enable bit is “1”) (Note)
0 : Odd parity
1 : Even parity
0
RW
6
Parity enable bit
(Valid in UART mode) (Note)
0 : Parity disabled
1 : Parity enabled
0
RW
7
Sleep select bit
(Valid in UART mode) (Note)
0 : Sleep mode cleared (ignored)
1 : Sleep mode selected
0
RW
Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be either “0”
or “1.”) Additionally, fix bit 7 to “0.”
UARTi baud rate register (BRGi)
b7
b0
UART0 baud rate register (Address 3116)
UART1 baud rate register (Address 3916)
20–14
Bit
Functions
At reset
RW
7 to 0
Can be set to “0016” to “FF16.”
Assuming that the set value = n, BRGi
divides the count source frequency by n + 1.
Undefined
WO
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
UARTi transmit buffer register
(b15)
(b8)
b7
b0
b7
b0
UART0 transmit buffer register (Addresses 3316, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
Functions
Bit
At reset
RW
8 to 0 Transmit data is set.
Undefined
WO
15 to 9 Nothing is assigned.
Undefined
–
At reset
RW
0
RW
0
RW
UARTi transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
Bit
0
Functions
Bit name
BRG count source select bits
1
b1 b0
0 0 : f2 / f4
0 1 : f16 / f32
1 0 : f64 / f128
1 1 : f512 / f1024
2
CTS/RTS select bit
0 : CTS function selected.
1 : RTS function selected.
0
RW
3
Transmit register empty flag
0 : Data present in transmit register.
(During transmitting)
1 : No data present in transmit register.
(Transmitting completed)
1
RO
Undefined
–
0
RW
6 to 4
7
Nothing is assigned.
Transfer format select bit
(Used in clock synchronous
serial I/O mode) (Note)
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
Note: Fix bit 7 to “0” in the UART mode or when Serial I/O is ignored.
7751 Group User’s Manual
20–15
APPENDIX
Appendix 3. Control registers
UARTi transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Functions
Bit name
Bit
At reset
RW
0
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0
RW
1
Transmit buffer empty flag
0 : Data present in transmit buffer
register.
1 : No data present in transmit
buffer register.
1
RO
2
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0
RW
3
Receive complete flag
0 : No data present in receive
buffer register.
1 : Data present in receive buffer
register.
0
RO
4
Overrun error flag
(Note 1) 0 : No overrun error
1 : Overrun error detected
0
RO
5
Framing error flag (Notes 1, 2) 0 : No framing error
1 : Framing error detected
(Valid in UART mode)
0
RO
6
(Notes 1, 2) 0 : No parity error
Parity error flag
(Valid in UART mode)
1 : Parity error detected
0
RO
7
(Notes 1, 2) 0 : No error
Error sum flag
1 : Error detected
(Valid in UART mode)
0
RO
Notes 1: Bit 4 is cleared to “0” when clearing the receive enable bit to “0.”
Bits 5 and 6 are cleared to “0” when one of the following is performed:
•clearing the receive enable bit to “0.”
•reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out.
Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.”
2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode.
UARTi receive buffer register
(b15)
(b8)
b7
b0
b7
b0
UART0 receive buffer register (Addresses 3716, 3616)
UART1 receive buffer register (Addresses 3F16, 3E16)
Bit
Functions
8 to 0 Receive data is read out from here.
15 to 9 Nothing is assigned.
The value is “0” at reading.
20–16
7751 Group User’s Manual
At reset
RW
Undefined
RO
0
–
APPENDIX
Appendix 3. Control registers
Count start register
b7
b6
b5
b4
b3
b2
b1
b0
Count start register (Address 4016)
Bit
Bit name
Functions
0 : Stop counting
1 : Start counting
At reset
RW
0
RW
0
Timer A0 count start bit
1
Timer A1 count start bit
0
RW
2
Timer A2 count start bit
0
RW
3
Timer A3 count start bit
0
RW
4
Timer A4 count start bit
0
RW
5
Timer B0 count start bit
0
RW
6
Timer B1 count start bit
0
RW
7
Timer B2 count start bit
0
RW
Functions
At reset
RW
0
WO
0
WO
0
WO
One-shot start register
b7
b6
b5
b4
b3
b2
b1
b0
One-shot start register (Address 4216)
Bit
Bit name
0
Timer A0 one-shot start bit
1
Timer A1 one-shot start bit
1 : Start outputting one-shot pulse
(valid when selecting internal
trigger.)
2
Timer A2 one-shot start bit
The value is “0” at reading.
3
Timer A3 one-shot start bit
0
WO
4
Timer A4 one-shot start bit
0
WO
Undefined
–
7 to 5 Nothing is assigned.
7751 Group User’s Manual
20–17
APPENDIX
Appendix 3. Control registers
Up-down register
b7
b6
b5
b4
b3
b2
b1
b0
Up-down register (Address 4416)
Bit
Functions
Bit name
0
Timer A0 up-down bit
1
Timer A1 up-down bit
0 : Down-count
1 : Up-count
This function is valid when the
contents of the up-down register is
selected as the up-down switching
factor.
RW
0
RW
0
RW
0
RW
0
RW
2
Timer A2 up-down bit
3
Timer A3 up-down bit
4
Timer A4 up-down bit
0
RW
5
Timer A2 two-phase pulse signal 0 : Two-phase pulse signal
processing function disabled
processing select bit
(Note)
1 : Two-phase pulse signal
processing function enabled
Timer A3 two-phase pulse signal
0
WO
0
WO
0
WO
6
processing select bit
7
(Note)
When not using the two-phase pulse
signal processing function, set the bit
Timer A4 two-phase pulse signal
to “0.”
processing select bit (Note)
The value is “0” at reading.
Note: Use the LDM or STA instruction when writing to bits 5 to 7.
20–18
At reset
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Timer Ai register
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Bit
Functions
15 to 0 These bits have different functions according
to the operating mode.
At reset
RW
Undefined
RW
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
Bit name
Functions
At reset
RW
0
RW
0
RW
0
RW
3
0
RW
4
0
RW
5
0
RW
6
0
RW
7
0
RW
0
1
2
Operating mode select bits
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot pulse mode
1 1 : Pulse width modulation (PWM) mode
These bits have different functions according to the operating mode.
7751 Group User’s Manual
20–19
APPENDIX
Appendix 3. Control registers
Timer Mode
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
b7 b6 b5
0
b4 b3
RW
Undefined
RW
At reset
RW
0
RW
0
RW
b2 b1 b0
0 0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
0 0 : Timer mode
1
2
Pulse output function select bit
0 : No pulse output
(TAiOUT pin functions as a programmable
I/O port.)
1 : Pulse output
(TAiOUT pin functions as a pulse output
pin.)
0
RW
3
Gate function select bits
b4 b3
0
RW
0
RW
4
0 0 : No gate function
0 1 : (TAiIN pin functions as a programmable I/O port.)
1 0 : Counter counts only while TAiIN
pin’s input signal is “L” level.
1 1 : Counter counts only while TAiIN
pin’s input signal is “H” level.
5
Fix this bit to “0” in the timer mode.
0
RW
6
Count source select bits
0
RW
0
RW
7
20–20
At reset
b7 b6
0 0 : f2 / f4
0 1 : f16 / f32
1 0 : f64 / f128
1 1 : f512 / f1024
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Event counter mode
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1
when down-counting, or by FFFF16 – n + 1
when up-counting.
When reading, the register indicates the
counter value.
b7
b6
b5
✕ ✕ 0
b4
b3
b2
b1
At reset
RW
Undefined
RW
At reset
RW
0
RW
0
RW
b0
0 1
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
0 1 : Event counter mode
1
2
Pulse output function select bit
0 : No pulse output (TAiOUT pin functions
as a programmable I/O port.)
1 : Pulse output (TAiOUT pin functions
as a pulse output pin.)
0
RW
3
Count polarity select bit
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0
RW
4
Up-down switching factor select
bit
0 : Contents of up-down register
1 : Input signal to TAiOUT pin
0
RW
5
Fix this bit to “0” in event counter mode.
0
RW
6
These bits are ignored in event counter mode.
0
RW
0
RW
7
✕ : It may be either “0” or “1.”
7751 Group User’s Manual
20–21
APPENDIX
Appendix 3. Control registers
One-shot pulse mode
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Functions
Bit
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the “H” level
width of the one-shot pulse output from the
TAiOUT pin is expressed as follows : n
fi.
At reset
RW
Undefined
WO
fi: Frequency of count source (f2 / f4, f16/ f32, f64/ f128, or f512/ f1024)
b7
b6
b5
0
b4
b3
b2
b1
b0
1 1 0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
0
1
2
3
Bit name
Operating mode select bits
6
7
20–22
1 0 : One-shot pulse mode
@
Fix this bit to “1” in one-shot pulse mode.
Trigger select bits
4
5
Functions
b1 b0
b4 b3
0 0 : Writing “1” to one-shot start register
0 1 : (TAiIN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAiIN pin’s input signal
1 1 : Rising edge of TAiIN pin’s input signal
Fix this bit to “0” in one-shot pulse mode.
Count source select bits
b7 b6
0 0 : f2 / f4
0 1 : f16 / f32
1 0 : f64 / f128
1 1 : f512 / f1024
7751 Group User’s Manual
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
APPENDIX
Appendix 3. Control registers
Pulse width modulation (PWM) mode
<When operating as a 16-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
b0
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Functions
Bit
15 to 0 These bits can be set to “000016” to “FFFE16.”
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
n
TAiOUT pin is expressed as follows:
fi
At reset
RW
Undefined
WO
fi: Frequency of count source (f2 / f4, f16 / f32, f64 / f128, or f512 / f1024)
<When operating as an 8-bit pulse width modulator>
(b15)
b7
(b8)
b0 b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
Functions
Bit
At reset
RW
7 to 0 These bits can be set to “0016” to “FF16.”
Assuming that the set value = m, PWM
pulse’s period output from the TAiOUT pin is
8
expressed as follows: (m + 1)(2 – 1)
fi
Undefined
WO
15 to 8 These bits can be set to “0016” to “FE16.”
Assuming that the set value = n, the “H” level
width of the PWM pulse output from the
TAiOUT pin is expressed as follows:
n(m + 1)
Undefined
WO
fi
fi: Frequency of count source (f2 / f4, f16 / f32, f64 / f128, or f512 / f1024)
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bi t
0
Functions
Bit name
Operating mode select bits
b1 b0
1 1 : PWM mode
1
2
3
Fix this bit to “1” in PWM mode.
Trigger select bits
4
b4 b3
0 0 : Writing “1” to count start register
0 1 : (TAiIN pin functions as a programmable I/O port.)
1 0 : Falling edge of TAiIN pin’s input signal
1 1 : Rising edge of TAiIN pin’s input signal
5
16/8-bit PWM mode select bit
0 : As a 16-bit pulse width modulator
1 : As an 8-bit pulse width modulator
6
Count source select bits
b7 b6
7
0 0 : f2 / f4
0 1 : f16 / f32
1 0 : f64 / f128
1 1 : f512 / f1024
7751 Group User’s Manual
At reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
20–23
APPENDIX
Appendix 3. Control registers
Timer Bi register
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Bit
Functions
At reset
RW
15 to 0 These bits have different functions according Undefined
to the operating mode.
RW
Timer Bi mode register
b7 b6 b5
b4 b3 b2
b1 b0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Operating mode select bits
1
2
Functions
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/Pulse width
measurement mode
1 1 : Not selected
These bits have different functions according to the operating mode.
3
At reset
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
–
5
These bits have different functions according to the operating mode.
Undefined
RO
(Note)
6
0
RW
7
0
RW
Note: Bit 5 is ignored in the timer and event counter modes; its value is undefined at reading.
20–24
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Timer mode
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
At reset
RW
15 to 0 These bits can be set to “000016” to “FFFF16.” Undefined
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
RW
Bit
b7
b6
b5
✕
b4
b3
b2
b1
Functions
b0
✕ ✕ 0 0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
0 0 : Timer mode
1
2
These bits are ignored in timer mode.
3
At reset
RW
0
RW
0
RW
0
RW
0
RW
4
Nothing is assigned.
Undefined
–
5
This bit is ignored in timer mode.
Undefined
–
6
Count source select bits
0
RW
0
RW
7
b7 b6
0 0 : f2 /f4
0 1 : f16 /f32
1 0 : f64 /f128
1 1 : f512 /f1024
✕ : It may be either “0” or “1.”
7751 Group User’s Manual
20–25
APPENDIX
Appendix 3. Control registers
Event counter mode
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Bit
Functions
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
b7
b6
b5
✕ ✕ ✕
b4
b3
b2
b1
RW
Undefined
RW
At reset
RW
0
RW
0
RW
0
RW
0
RW
b0
0 1
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Operating mode select bits
Functions
b1 b0
0 1 : Event counter mode
1
2
Count polarity select bit
b3 b2
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Counts at both falling and rising edges
of external signal
1 1 : Not selected
3
4
Nothing is assigned.
Undefined
—
5
This bit is ignored in event counter mode.
Undefined
—
6
These bits are ignored in event counter mode.
0
RW
0
RW
7
✕ : It may be either “0” or “1.”
20–26
At reset
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Pulse period/pulse width measurement mode
(b15)
b7
(b8)
b0 b7
b0
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Bit
Functions
15 to 0 The measurement result of pulse period or
pulse width is read out.
b7
b6
b5
b4
b3
b2
b1
At reset
RW
Undefined
RO
At reset
RW
0
RW
0
RW
0
RW
0
RW
Undefined
–
Undefined
RO
0
RW
0
RW
b0
1 0
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Bit
0
Bit name
Operating mode select bits
1
2
Measurement mode select bits
3
Functions
b1 b0
1 0 : Pulse period/Pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement
(Interval between falling edges
of measurement pulse)
0 1 : Pulse period measurement
(Interval between rising edges
of measurement pulse)
1 0 : Pulse width measurement
(Interval from a falling edge to a rising
edge, and from a rising edge to a
falling edge of measurement pulse)
1 1 : Not selected
4
Nothing is assigned.
5
Timer Bi overflow flag
(Note)
0 : No overflow
1 : Overflowed
6
Count source select bits
b7 b6
7
0 0 : f2 / f4
0 1 : f16 / f32
1 0 : f64 / f128
1 1 : f512 / f1024
Note: The timer Bi overflow flag is cleared to “0” by writing to the timer Bi mode register with the
count start bit = “1”. The timer Bi overflow flag cannot be set to “1” by software.
7751 Group User’s Manual
20–27
APPENDIX
Appendix 3. Control registers
Processor mode register 0
b7
b6
0
b5
b4
b3
b2
0
b1
b0
Processor mode register 0 (Address 5E16)
Bit
0
Bit name
Processor mode bits
1
2
Fix this bit to “0.”
3
Software reset bit
4
Interrupt priority detection time
select bits
5
6
Fix this bit to “0.”
7
Clock 1 output select bit
(Note 2)
Functions
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not selected
At reset
RW
0
RW
0
RW
(Note 1)
0
RW
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0
WO
b5 b4
0
RW
0
RW
0
RW
0
RW
0 0 : 7 cycles of
0 1 : 4 cycles of
1 0 : 2 cycles of
1 1 : Not selected
0 : Clock 1 output disabled
(P42 functions as a programmable
I/O port.)
1 : Clock 1 output enabled
(P42 functions as a clock 1 output pin.)
Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1.” (Fixed to “1.”)
2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”)
20–28
7751 Group User’s Manual
APPENDIX
Appendix 3. Control registers
Processor mode register 1
b7
b6
0 0
b5
b4
b3
b2
b1
b0
0 0
Processor mode register 1 (Address 5F16)
Bit
1, 0
Functions
Bit name
Fix these bits to “0.”
At reset
RW
0
RW
0
RW
2
Clock source for peripheral
devices select bit
(Note)
0:
1:
3
CPU running speed select bit
(Note)
0 : High-speed running
1 : Low-speed running
0
RW
4
Bus cycle select bits
In high-speed running
0
RW
0
RW
0
RW
divided by 2
b5 b4
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
In low-speed running
5
b5 b4
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
7, 6
Fix these bits to “0.”
Note: Fix this bit to “0” when f(XIN) > 25 MHz.
7751 Group User’s Manual
20–29
APPENDIX
Appendix 3. Control registers
Watchdog timer register
b7
b0
Watchdog timer register (Address 6016)
Bit
7 to 0
Functions
Initializes the watchdog timer.
When a dummy data is written to this register, the watchdog
timer’s value is initialized to “FFF16.” (Dummy data: 0016 to FF16)
At reset
RW
Undefined
–
At reset
RW
0
RW
Watchdog timer frequency select register
b7
b6
b5
b4
b3
b2
b1
b0
Watchdog timer frequency select register (Address 6116)
Bit
0
Bit name
Watchdog timer frequency select 0 : Wf512 / Wf1024
1 : Wf32 / Wf64
bit
7 to 1 Nothing is assigned.
20–30
Functions
7751 Group User’s Manual
Undefined
–
APPENDIX
Appendix 3. Control registers
Interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 7016 to 7C16)
Bit
Bit name
0
Interrupt priority level select bits
1
2
3
Interrupt request bit
7 to 4
Nothing is assigned.
Functions
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0 : No interrupt request
1 : Interrupt request
At reset
RW
0
RW
0
RW
0
RW
0
(Note)
RW
Undefined
–
Note: The A-D conversion interrupt request bit becomes undefined after reset.
b7
b6
b5
b4
b3
b2
b1
b0
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit
Bit name
0
Interrupt priority level select bits
1
2
Functions
At reset
RW
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
High level
0
RW
0
RW
0
RW
b2 b1 b0
3
Interrupt request bit (Note)
0 : No interrupt request
1 : Interrupt request
0
RW
4
Polarity select bit
0 : Set the interrupt request bit at
“H” level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
“L” level for level sense and at
rising edge for edge sense.
0
RW
5
Level sense/Edge sense select bit
0 : Edge sense
1 : Level sense
0
RW
Undefined
–
7, 6
Nothing is assigned.
Note: The INT0 to INT2 interrupt request bits are invalid when selecting the level sense.
7751 Group User’s Manual
20–31
APPENDIX
Appendix 4. Package outlines
Appendix 4. Package outlines
80P6N-A
20–32
7751 Group User’s Manual
APPENDIX
Appendix 4. Package outlines
80D0
7751 Group User’s Manual
20–33
APPENDIX
Appendix 5. Example for processing unused pins
Appendix 5. Example for processing unused pins
Table 1 Example for processing unused pins in single-chip mode
Pin name
Example of processing
Ports P0 to P8
_
Set for input mode and connect these pins to Vcc or
Vss via a resistor; or set for output mode and leave
these pins open. (Note 1)
E
Leave it open.
X OUT (Note 2)
AVcc
Connect this pin to Vcc.
AVss, VREF, BYTE
Connect these pins to Vss.
Notes 1: When setting these ports to the output mode and leave them open, they remain set to the input
mode until they are switched to the output mode by software after reset. While ports remain set
to the input mode, consequently, voltage levels of pins are unstable, and a power source current
can increase.
The contents of the direction register can be changed by noise or a program runaway generated
by noise. To improve its reliability, we recommend to periodically set the contents of the direction
register by software.
When processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer).
2: This applies when a clock externally generated is input to the XIN pin.
20–34
7751 Group User’s Manual
APPENDIX
Appendix 5. Example for processing unused pins
Table 2 Example for processing unused pins in memory expansion mode or microprocessor mode
Pin name
Example of processing
Ports P4 2 to P4 7, P5 to P8
____
BHE (Note 2)
ALE (Note 3)
Set for input mode and connect these pins to Vcc or
Vss via a resistor; or set for output mode and leave
these pins open. (Note 1)
Leave them open. (Note 4)
_____
HLDA, φ 1
X
OUT (Note 5)
_____
____
Leave it open.
HOLD, RDY
Connect these pins to Vcc via a resistor (pull-up).
AVcc
Connect this pin to Vcc.
Connect these pins to Vss.
AVss, VREF
Notes 1: When setting these ports to the output mode and leave them open, they remain set to the input
mode until they are switched to the output mode by software after reset. While ports remain set
to the input mode, consequently, voltage levels of pins are unstable, and a power source current
can increase.
The contents of the direction register can be changed by noise or a program runaway generated
by noise. To improve its reliability, we recommend to periodically set the contents of the direction
register by software.
When processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer).
2: This applies when “H” level is input to the BYTE pin.
3: This applies when “H” level is input to the BYTE pin and the access space is 64 Kbytes.
4: When supplying Vss level to the CNVss pin, these pins remain set to the input mode until they
are switched to the output mode by software after reset (until the pin function is switched in the
case of the φ 1 pin in the memory expansion mode). While pins remain set to the input mode,
consequently, voltage levels of pins are unstable, and a power source current can increase.
5: This applies when a clock externally generated is input to the XIN pin.
7751 Group User’s Manual
20–35
APPENDIX
Appendix 5. Example for processing unused pins
● When setting ports for input mode
P0–P8
E
XOUT
P42–P47, P5–P8
BHE
ALE
Left open
M37751
M37751
VCC
AVCC
AVSS
VREF
HLDA
Left open
1
XOUT
Left open
VCC
H O LD
RDY
BYTE
AVCC
AVSS
VREF
VSS
VSS
In memory expansion mode
In microprocessor mode
In single-chip mode
● When setting ports for output mode
P0–P8
Left open
E
XOUT
Left open
P42–P47, P5–P8
M37751
M37751
VCC
AVCC
AVSS
VREF
BYTE
BHE
ALE
HLDA
Left open
Left open
1
XOUT
Left open
VCC
HOLD
RDY
AVCC
AVSS
VREF
VSS
VSS
In memory expansion mode
and microprocessor mode
In single-chip mode
Fig. 4. Example for processing unused pins
20–36
7751 Group User’s Manual
APPENDIX
Appendix 6. Hexadecimal instruction code table
Appendix 6. Hexadecimal instruction code tab le
7751 Group User’s Manual
20–37
APPENDIX
Appendix 6. Hexadecimal instruction code table
20–38
7751 Group User’s Manual
APPENDIX
Appendix 6. Hexadecimal instruction code table
7751 Group User’s Manual
20–39
APPENDIX
Appendix 7. Machine instructions
Appendix 7. Machine instructions
20–40
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–41
APPENDIX
Appendix 7. Machine instructions
20–42
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–43
APPENDIX
Appendix 7. Machine instructions
20–44
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–45
APPENDIX
Appendix 7. Machine instructions
20–46
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–47
APPENDIX
Appendix 7. Machine instructions
20–48
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–49
APPENDIX
Appendix 7. Machine instructions
20–50
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–51
APPENDIX
Appendix 7. Machine instructions
20–52
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–53
APPENDIX
Appendix 7. Machine instructions
20–54
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–55
APPENDIX
Appendix 7. Machine instructions
20–56
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–57
APPENDIX
Appendix 7. Machine instructions
20–58
7751 Group User’s Manual
APPENDIX
Appendix 7. Machine instructions
7751 Group User’s Manual
20–59
APPENDIX
Appendix 7. Machine instructions
20–60
7751 Group User’s Manual
APPENDIX
Appendix 8. Examples of noise immunity improvement
Appendix 8. Examples of noise immunity improvement
Generally effective examples of noise immunity improvements are described below. Although the effect of
these countermeasure depends on each system, refer to the following when an noise-related problem
occurs.
1. Short wiring length
The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer.
______
(1) Wiring for RESET pin
______
Make the length of wiring connected to RESET
pin as short as possible.
______
In particular, connect a capacitor between RESET pin and Vss pin with the shortest possible wiring
(within 20 mm).
______
Reason: If noise is input to RESET pin,
the microcomputer restarts operation before the internal state of the
microcomputer is completely
initialized. This may cause a
program runaway.
Noise
Reset
circuit
M37751
RESET
Vss
Vss
Not
acceptable
Reset
circuit
Vss
M37751
RESET
Vss
Acceptable
______
Fig. 5. Wiring for RESET pin
7751 Group User’s Manual
20–61
APPENDIX
Appendix 8. Examples of noise immunity improvement
(2) Wiring for clock input/output pins
● Make the length of wiring connected to the clock input/output pins as short as possible.
● Make the length of wiring between the grounding lead of the capacitor, which is connected to
the oscillator and Vss pin of the microcomputer, as short as possible (within 20 mm).
● Separate the Vss pattern for oscillation from all other Vss patterns. (Refer to Figure 14.)
Reason: The microcomputer’s operation
synchronizes with a clock generated
by the oscillation circuit.
If noise enters clock I/O pins, clock
waveforms may be deformed. This
may cause a malfunction or a
program runaway.
Also, if the noise causes a potential
difference between the Vss level
of the microcomputer and the Vss
level of an oscillator, the correct
clock will not be input in the
microcomputer.
Noise
M37751
M37751
XIN
XOUT
Vss
XIN
XOUT
Vss
Not acceptable
Acceptable
Fig. 6. Wiring for clock input/output pins
(3) Wiring for CNVss pin
Connect CNVss pin to Vss pin with the shortest possible wiring.
Reason:
The processor mode of the
microcomputer is influenced by a
potential at CNVss pin when
CNVss and Vss pins are
connected.
If the noise causes a potential
difference between CNVss and
Vss pins, the processor mode may
become unstable. This may cause
a microcomputer malfunction or
a program runaway.
M37751
Noise
CNVss
CNVss
Vss
Vss
Not Acceptable
Fig. 7. Wiring for CNVss pin
20–62
M37751
7751 Group User’s Manual
Acceptable
APPENDIX
Appendix 8. Examples of noise immunity improvement
(4) Wiring for CNVss (V PP) pin of built-in PROM version
< In single-chip or memory expansion modes>
● Connect CNVss (V PP) to Vss pin of the microcomputer with the shortest possible wiring.
● If the above countermeasure can not be taken, insert an approximate 5 kΩ resistor between
CNVss (VPP) and Vss pins and be sure to make the distance between the resistor and CNVss (VPP)
pin as short as possible.
< In microprocessor mode>
● Connect CNVss (V PP) pin to Vcc pin with the shortest possible wiring.
Reason: CNVss (V PP) pin is connected to the internal ROM in the low-impedance state. (Noise is
easily fed to the pin in this condition.)
If noise enters the CNVss (VPP) pin, incorrect instruction codes or data is fetched from the
built-in PROM. This may cause a program runaway.
Single-chip and
memory expansion modes
Microprocessor mode
M37751
M37751
Shortest possible
distance
Approx. 5 kohms
VCC
CNVSS(VPP)
CNVSS(VPP)
VSS
Shortest possible
distance
CNVss pin is connected to
Vss pin with the shortest
possible wiring.
CNVss pin is connected to
Vss pin with the shortest
possible wiring.
✽ The above countermeasure is not necessary for BYTE (VPP) pin.
Fig. 8. Wiring for CNVss (V PP) pin of built-in PROM version
7751 Group User’s Manual
20–63
APPENDIX
Appendix 8. Examples of noise immunity improvement
2. Connection of bypass capacitor between Vss and Vcc lines
Connect an approximate 0.1 µ F bypass capacitor as follows:
● Connect a bypass capacitor between the Vss and Vcc pins, at equal lengths.
● The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as
possible.
● Use thicker wiring for the Vss and Vcc lines than the other signal lines.
Bypass capacitor
AA
AA
AA
AA
AA AA
Wiring pattern
Wiring pattern
Vcc
Vss
M37751
Fig. 9. Bypass capacitor between Vss and Vcc lines
20–64
7751 Group User’s Manual
APPENDIX
Appendix 8. Examples of noise immunity improvement
3. Wiring for analog input pins, analog power source pins, etc.
(1) Processing analog input pins
● Connect a resistor to the analog signal line, which is connected to an analog input pin, and make
the connection as close to the microcomputer as possible.
● Connect a capacitor between the analog input pin and AVss pin, as close to the AVss pin as
possible.
Reason: A signal which is input to the analog input pin is usually an output signal from a sensor.
The sensor which measures changes in status tends to be installed far from the microcomputer
printed circuit board. The result is long wiring that becomes an antenna which picks up
noise and feeds it into the microcomputer analog input pin.
If a capacitor between an analog input pin and AVss pin is grounded far away from AVss
pin, noise on the GND line may enter the microcomputer through the capacitor.
Noise
(Note 2)
M37751
RI
ANi
Thermistor
CI
AVss
Reference value
RI : Approximately 100 to 1000
CI : Approximately 100 to 1000 pF
Notes 1 : Design an external circuit for ANi pin so that charge/discharge is available within 1
cycle of AD.
2 : This resistor and thermistor are used to divide resistance.
Fig. 10. Example of noise immunity improvement using thermistor
7751 Group User’s Manual
20–65
APPENDIX
Appendix 8. Examples of noise immunity improvement
(2) Processing analog power source pins, etc.
● Use independent power sources for Vcc, AVcc and V REF pins.
● Insert capacitors between the AVcc and AVss pins, and between the V REF and AVss pins.
Reasons: Prevents the A-D converter from noise on the Vcc line.
M37751
Reference value
C1
0.47 µF
C2
0.47 µF
AVcc
VREF
C1
C2
Note : Connect capacitors using the
thickest, shortest wiring possible.
AVss
ANi
(sensor, etc.)
Fig. 11. Processing analog power source pins, etc.
20–66
7751 Group User’s Manual
APPENDIX
Appendix 8. Examples of noise immunity improvement
4. Oscillator protection
The oscillator which generates the basic clock for the microcomputer operations must be protected from
the affect of other signals.
(1) Distance oscillator from signal lines with large current flows
Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle
currents larger than the microcomputer current value tolerance.
Reason: A microcomputer is used in systems
which contain signal lines for
controlling motors, LEDs, thermal
heads, etc. Noise occurs due to
mutual inductance when a large
current flows through the signal
lines.
M37751
Mutual inductance
M
Large
current
XIN
XOUT
Vss
Fig. 12. Connection of signal wires where a large
current flows
(2) Distance oscillator from signal lines with frequent potential level changes
● Install an oscillator and a connecting pattern of an oscillator away from signal lines in which
potential levels change frequently.
● Do not cross the signal lines over the clock-related or noise-sensitive signal lines.
Reason: S i g n a l s l i n e s w i t h f r e q u e n t l y
changing potential levels may affect
other signal lines at a rising or falling
edge. In particular, if the lines cross
over a clock-related signal line, clock
waveforms may be deformed, which
causes a microcomputer malfunction
or a program runaway.
M37751
Do not cross.
✽
XIN
XOUT
Vss
✽ I/O pin for signal with frequently
changing potential levels.
Fig. 13. Wiring of rapidly level changing signal wire
7751 Group User’s Manual
20–67
APPENDIX
Appendix 8. Examples of noise immunity improvement
(3) Oscillator protection using Vss pattern
Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the
oscillator mount position.
Connect the Vss pattern to Vss pin of the microcomputer with the shortest possible wiring, separating
it from other Vss patterns.
An example on the bottom of an
oscillator.
AAAAAA
AA
AAA
A
A
AAAAA
M37751
Mounted pattern
example of an
oscillator unit.
XIN
XOUT
Vss
Separate Vss lines for oscillation and supply.
Fig. 14. Vss pattern underneath mounted oscillator
20–68
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APPENDIX
Appendix 8. Examples of noise immunity improvement
5. Setup for I/O ports
Setup I/O ports by hardware and software as follows:
<Hardware protection>
● Connect a resistor of 100 ohms or more to an I/O port in series.
<Software protection>
● As for an input port, read data several times for checking whether input levels are equal or not.
● As for an output port, since the output data may reverse because of noise, rewrite data to its port Pi
register periodically.
● Rewrite data to port Pi direction registers periodically.
Data bus
Noise
Direction register
Port latch
Port
Fig. 15. Setup for I/O ports
7751 Group User’s Manual
20–69
APPENDIX
Appendix 8. Examples of noise immunity improvement
6. Reinforcement of the power source line
● For the Vss and Vcc lines, use thicker wiring than that of other signal lines.
● When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle
layers.
● The following is necessary for double-sided printed circuit boards:
On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around
it. The vacant area is filled with the Vss line.
On the opposite side, the Vcc line is wired the same as the Vss line.
The power source lines of external devices which are connected by bus to the microcomputer must be
connected to the microcomputer's power source lines with the shortest possible wiring.
Reasons: With external devices connected to the microcomputer, the levels of many of the signal lines
(total external address buses: 24 bits) may change simultaneously, causing noise on the power
source line.
20–70
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APPENDIX
Appendix 9. Q & A
Appendix 9. Q & A
Information which may be helpful in fully utilizing the 7751 Group is provided in
Q & A format.
In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each
page is a question, and a box below the question is its answer. (If a question or an answer extends to two
or more pages, there is a page number at the lower right corner.)
At the upper right corner of each page, the main function related to the contents of description in that page
is listed.
7751 Group User’s Manual
20–71
APPENDIX
Appendix 9. Q & A
Interrupt
Q
If an interrupt request (b) occurs while executing an interrupt routine (a), is the main routine is not
executed before the INTACK sequence for the next interrupt (b) is executed after the interrupt routine
(a) under execution is completed?
Sequence of
execution
?
RTI instruction
Interrupt routine (a)
INTACK sequence
for interrupt (b)
Main routine
Condition
● I is cleared to “0” with the RTI instruction.
● The interrupt priority level of the interrupt (b) is higher than the main routine IPL.
● The interrupt priority detection time is 2 cycles of φ.
A
Sampling for interrupt requests are performed by sampling pulses generated synchronously with the
CPU’s op-code fetch cycles.
(1) If the next interrupt request (b) occurs before the sampling pulse ( ➀ ) for the RTI instruction is
generated, the microcomputer executes the INTACK sequence for (b) without executing the main
routine (not even one instruction) because sampling is completed while executing the RTI
instruction.
Interrupt request (b)
➀
Sampling pulse
RTI instruction
Interrupt routine (a)
INTACK sequence for interrupt (b)
(2) If the next interrupt request (b) occurs immediately after generating of the sampling pulse ➀ , the
microcomputer executes one instruction of the main routine before executing the INTACK sequence for (b) because the interrupt request is sampled by the next sampling pulse ➁.
Interrupt request (b)
➁
➀
Sampling pulse
RTI instruction One instruction executed
Interrupt routine (a)
20–72
Main routine
7751 Group User’s Manual
INTACK sequence
for interrupt (b)
APPENDIX
Appendix 9. Q & A
Interrupt
Q
There is a routine where a certain interrupt request should not be accepted (with enabled acceptance
of all other interrupt requests). Accordingly, the program set the interrupt priority level select bits of
the interrupt to be not accepted to “0002” in order to disable it before executing the routine. However,
the interrupt request of that interrupt has been accepted immediately after the priority level had been
changed. Why did this occur and what can I do about it?
:
LDM #00H, XXXIC ; Writes “0002” to interrupt priority level select bits.
; Clears interrupt request bit to “0.”
LDA A,DATA
; Instruction at the beginning of the routine that
should not accept one certain interrupt request.
:
;
Interrupt request is
accepted in this
interval
A
When changing the interrupt priority level, the microcomputer can behave “as if the interrupt request
is accepted immediately after it is disabled ” if the next instruction (the LDA instruction in the above
case) is already stored in the BIU’s instruction queue buffer and conditions to accept the interrupt
request which should not be accepted are met immediately before executing the instruction which is
in that buffer.
When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the
CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into
the actual address. Detection of interrupt priority level is performed at the beginning of each instruction.
In the above case, in the interrupt priority detection which is performed simultaneously with the
execution of the next instruction, the interrupt priority level before changing it is detected and the
interrupt request is accepted. It is because the CPU executes the next instruction before the BIU
finishes changing the interrupt priority levels.
Interrupt request generated
Interrupt request accepted
Sequence of execution
Interrupt priority detection time
CPU operation
BIU operation
Previous instruction
executed
(Instruction prefetch)
LDM instruction
executed
LDA instruction
executed
Interrupt priority level select bits set
Change of interrupt priority levels
completed
(1/2)
7751 Group User’s Manual
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APPENDIX
Appendix 9. Q & A
Interrupt
A
To prevent this problem, use software to execute the routine that should not accept a certain interrupt
request after change of interrupt priority level is completed. The following shows a sample program.
[ Sample program]
After an instruction which writes “000 2 ” to the interrupt priority level select bits, fill the instruction queue buffer with the NOP instruction to make the next instruction not be executed before the
writing is completed.
:
LDM #00H, XXXIC
NOP
NOP
NOP
LDA A,DATA
; Sets the interrupt priority level select bits to “000 2.”
;
;
;
; Instruction at the beginning of the routine that should not accept a certain
interrupt request
(2/2)
20–74
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APPENDIX
Appendix 9. Q & A
Interrupt
Q
____
(1) Which timing of clock φ 1 is the external interrupts (input
signals to the INT i pin) detected?
____
(2) How can four or more external interrupt input pins (INT i) be used?
A
(1) In both the edge
sense and level sense, external interrupt requests occur when the input
____
signal to the INT i pin changes its level regardless of clock φ 1.
In the edge sense, the interrupt request bit is set to “1” at this time.
(2) There are two methods: one uses external interrupt’s level sense, and the other uses the
timer’s event counter mode.
➀ Using external interrupt’s level sense
____
In hardware, input a logical sum of multiple interrupt signals (e.g., ‘a’, ‘b’, and ‘c’) to the INTi
pin, and input each signal to each corresponding
port.
___
In software, check the port’s input levels in the INT i interrupt routine to determine that which
of the signals ‘a’, ‘b’, and ‘c’ is input.
M37751
Port
Port
Port
INTi
➁ Using timer’s event counter mode
In hardware, input interrupt signals to the TAi IN pins or TBi IN pins.
In software, set the timer’s operating mode to the event counter mode and a value “000016 ”
into the timer register to the effective edge.
The timer’s interrupt request occurs when an interrupt signal (selected effective edge) is input.
7751 Group User’s Manual
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APPENDIX
Appendix 9. Q & A
Serial I/O (UART mode)
Q
____
In the case selecting the CTS
function in UART (clock asynchronous serial I/O) mode, when the
____
transmitting side check the CTS input level ?
A
It is check near the middle of the stop bit (when two stop bits are selected, the second stop bit).
Input level to CTSi pin is checked near here.
Transmit data
..............
D6
D7
n
n
SP
n/2
..............
n/2
Input level to CTSi pin is checked near here.
Transmit data
..............
D6
D7
SP
n
n
n
n: 1-bit length
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7751 Group User’s Manual
SP
n/2
..............
n/2
APPENDIX
Appendix 9. Q & A
Hold function
Q
______
When “L” level is input to the HOLD pin, how long is the bus actually opened ?
A
The bus
is opened after 50 ns at maximum has passed from the rising edge of next clock φ1 when
____
the HLDA pin output becomes “L” level.
Clock
1
.......
HOLD
HLDA
Term where bus is open
tpxz(HOLD-PZ) : Maximum 50 ns
7751 Group User’s Manual
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APPENDIX
Appendix 9. Q & A
Processor mode
Q
If the processor mode is switched as described below by using the processor mode bits (bits 1
and 0 at address 5E 16) during program execution, is there any precaution in software?
● Single-chip mode → Microprocessor mode
● Memory expansion mode → Microprocessor mode
A
If the processor mode is switched as described above by using the processor mode bits, the
mode is switched simultaneously when the cycle to write to the processor mode bits is completed.
Then, the program counter indicates the address next to the address (address XXXX 16) that
contains the write instruction for the processor mode bits. Additionally, access to the internal
ROM area is disabled. However, since the instruction queue buffer can prefetch up to three
instructions, the address in the external ROM area and is accessed first after the mode is
switched is one of XXXX 16 + 1 to XXXX 16 + 4. The instructions at addresses XXXX 16 + 1 to
XXXX 16 + 3 in the internal ROM area can be executed. To prevent this problem, process the
following by software.
➀ Write the write instruction for the processor mode bits and next instructions (at least three
bytes) at the same addresses both in the internal ROM and external ROM areas. (See
below.)
Internal ROM area
XXXX16
:
:
LDM. B #00000010B, PMR
NOP
NOP
NOP
:
External ROM area
XXXX16
At least
three
bytes
:
:
LDM. B #00000010B, PMR
NOP
NOP
NOP
:
:
➁ Transfer the write instruction for the processor mode bits to an internal RAM area and make
a branch to there in order to execute the write instruction. After that, make a branch to the
program address in the external ROM area. (Contents of the instruction queue buffer is
initialized by a branch instruction.)
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APPENDIX
Appendix 9. Q & A
SFR
Q
Is there any SFR for which instructions that can be used to set registers or bits are limited?
A
Use the STA or LDM instruction to set the registers or the bits listed below. Do not use readmodify-write instructions (i.e., CLB, SEB, INC, DEC, ASL, ASR, LSR, ROL, and ROR).
UART0 baud rate register (address 3116)
UART1 baud rate register (address 3916)
UART0 transmit buffer register (addresses 3316, 3216)
UART1 transmit buffer register (addresses 3B16, 3A16)
Timer A4 two-phase pulse signal processing select bit (bit 7 at address 4416)
Timer A3 two-phase pulse signal processing select bit (bit 6 at address 4416)
Timer A2 two-phase pulse signal processing select bit (bit 5 at address 4416)
7751 Group User’s Manual
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APPENDIX
Appendix 9. Q & A
Clock
Q
Is there any precaution when f(X IN) > 25 MHz ?
A
Set the processor mode register 1 (address 5F 16) to the following.
b7
0 0
b0
0 0 0 0
Fix these bits to “0.”
Bus cycle when accessing external device
b5 b4
0 0 :
0 1 :
1 0 :
(1 1:
5φ
4φ
3φ
Not selected)
Fix these bits to “0.”
The microcomputer becomes the following state by the setting above.
● f4, f32, f128, or f1024 can be selected for the operating clock of internal peripheral devices such
as timer.
● SFR and internal ROM area are accessed at 3 φ bus cycle. Internal RAM area is accessed
at 2 φ bus cycle.
● 3φ, 4φ, or 5φ can be selected for the bus cycle when accessing an external device. 2φ cannot
be selected for the bus cycle.
20–80
7751 Group User’s Manual
APPENDIX
Appendix 9. Q & A
Clock
Q
Is there any precaution when f(X IN) ≤ 25 MHz ?
A
When setting the CPU running speed select bit (bit 3 at address 5F16) to “1,” SFR and internal
ROM access become faster than this bit is “0.” Accordingly, we recommend to set this bit to
“1.”
However, do not set bits 5 to 3 at address 5F 16 to “001 2.” When setting bit 3 at address 5F 16
to “1,” set bit 5, bit 4, or both bits 5 and 4 to “1” at the same time because bits 5 and 4 at
address 5F 16 become “00 2” at reset.
b7
0 0
b0
1
0 0
Fix these bits to “0.”
Clock source for peripheral devices
0 : φ divided by 2
1 : φ
Bus cycle when accessing external device
Set these bits to “01 2,” “10 2,” “11 2.”
(Not selected “002.”)
b5 b4
0 0 : 4φ
0 1 : 3φ
1 0 : 2φ
Fix these bits to “0.”
7751 Group User’s Manual
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APPENDIX
Appendix 9. Q & A
Substitute for 7700 Series/7750 Series
Q
Are there precautions when the 7751 Series substitutes for the 7700 Series or the 7750 Series?
A
The common precautions are described below. Refer to the relevant chapter for details.
•Fix the processor status register (PS) bits 15 to 11 to “0.” Do not set these bits to “1.”
•There are the structure differences in the processor mode register 0 (address 5E 16) and the
processor mode register 1 (address 5F16).
•The A-D conversion interrupt request bit (bit 3 at address 7016) is undefined at reset. Set this
bit to “0” by software before use.
•Clear the receive enable bit (bit 2 at addresses 3516, 3D16) to “0” when clearing the overrun error
flag (bit 4 at addresses 3516 , 3D 16) to “0.”
This is only method that the overrun error flag is cleared to “0”
•There are instructions of which number of the instruction cycle is decreased. Accordingly, it is
possible that the instruction execution timing become faster.
•Part of the electrical characteristics, Ready function, Hold function, and the bus timing are
different.
20–82
7751 Group User’s Manual
APPENDIX
Appendix 9. Q & A
Watchdog timer
Q
When detecting the software runaway by the watchdog timer, if not software reset but setting the
same value as the contents of the reset bector address to the watchdog timer interrupt bector
address is processed, how does it result in?
When branching to the reset branch address within the watchdog timer interrupt routine, how
does it result in?
A
The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly,
the user must perform the initial setting for these all by software.
The processor interrupt priority level (IPL) retains “7” of the watchdog timer interrupt priority
level, and that is not initialized. Consequently, all interrupt requests are not accepted.
When rewriting the IPL by software, save once the 16-bit immediate value to the stack area
and next restore that 16-bit immediate value to all bits of the processor status register (PS).
We recommend software reset in order to initialize the microcomputer for software runaway.
7751 Group User’s Manual
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APPENDIX
Appendix 9. Q & A
MEMORANDUM
20–84
7751 Group User’s Manual
GLOSSARY
GLOSSARY
This section briefly explains the terms used in this user’s manual. The terms defined here apply to this
manual only.
Term
Meaning
Relevant term
Access
Means performing read, write, or read and write.
Access space
An accessible memory space of up to 16 Mbytes.
Access
Access characteristics
Means whether accessible or not.
Access
Baud rate
Means a transfer rate of Serial I/O.
Branch
Bus control signal
Means moving the program’s execution
point__(= ____
address)_____
to another
location.
_ ____
_____
A generic name for ALE, E, BHE, R/W, RDY, HOLD, HLDA and
BYTE signals.
Count source
A signal that is counted by Timers A and B, the UARTi baud rate
register (BRGi) and Watchdog timer. That is f 2/f 4, f16/f 32, f 64/f 128,
f512/f 1024 selected by the count source select bits and others.
Down-count
External area
Means decreasing by 1 and counting.
Up-count
An accessible area for external devices connected in the memory Internal area
expansion or microprocessor mode. It is up to 16-Mbyte external
area.
External bus
A generic name for the external address bus and the data bus.
External device
Devices connected externally to the microcomputer. A generic
name for a memory, an I/O device and a peripheral IC.
An accessible internal area. A generic name for areas of the External area
internal RAM, internal ROM and the SFR.
Internal area
Interrupt routine
A routine that is automatically executed when an interrupt request
is accepted. Set the start address of this routine into the interrupt
vector address.
LSB first
Means a transfer data format of Serial I/O; LSB is transferred MSB first
first.
MSB first
Means a transfer data format of Serial I/O; MSB is transferred LSB first
first.
A state where the up-count resultant is greater than the counter Under flow
resolution.
Up-count
R e a d - m o d i f y - w r i t e An instruction that reads the memory contents, modifies them
and writes back to the same address. Relevant instructions are
instruction
the ASL, ASR, CLB, DEC, INC, LSR, ROL, ROR, SEB instructions.
Overflow
Signal required for access A generic name for bus control, address bus, and data bus signals. B u s c o n t r o l
to external device
signal
A state where the oscillation circuit halts and the program execution Wait mode
Stop mode
is stopped. By executing the STP instruction, the microcomputer
enters Stop mode.
UART
Under flow
2
Clock asynchronous serial I/O. When used to designate the name Clock
of a functional block, this term also means the serial I/O which synchronous
can be switched to the cock synchronous serial I/O.
serial I/O.
A state where the down-count resultant is greater than the counter Overflow
resolution.
Down-count
7751 Group User’s Manual
GLOSSARY
Term
Meaning
Relevant term
Up-count
Means increasing by 1 and counting.
Wait mode
A state where the oscillation circuit is operating, however, the Stop mode
program execution is stopped. By executing the WIT instruction,
the microcomputer enters Wait mode.
7751 Group User’s Manual
Down-count
3
GLOSSARY
MEMORANDUM
4
7751 Group User’s Manual
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
7751 Group
Jul. First Edition 1997
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1997 MITSUBISHI ELECTRIC CORPORATION