TC93P24FG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC93P24FG Single-Chip DTS Microcontroller (DTS-20) The TC93P24FG is a single-chip digital tuning system (DTS) microcontroller incorporating a 230 MHz prescaler, PLL, and LCD driver. In addition to a 20-bit IF counter, an 8-channel, 8-bit AD converter, two types of serial interface, and buzzer function, the TC9324FG offers a range of functions required for DTS, including an interrupt function, an 8-bit timer-counter, and an 8-bit pulse counter. In addition, the LCD driver features six modes combining 1/4, 1/3, and 1/2 duty and 1/2 and 1/3 bias. This product is suitable for use in a wide variety of DTS systems, from automobile to home audio, including compact stereo systems. Weight: 1.6 g (typ.) Features • • • • • • • • • • • • • • • • • • CMOS DTS microcontroller LSI with built-in 230 MHz prescaler, PLL, and LCD driver Operating voltage: PLL operating: VDD = 4.0 to 5.5 V (typ. 5.0 V) PLL off: VDD = 3.5 to 5.5 V (when CPU only operating) Crystal oscillator frequency: 4.5 MHz, 75 kHz Current dissipation: PLL operating: IDD = 3 mA (typ.) (crystal oscillator frequency 4.5 MHz, VHF mode) PLL off: IDD = 1 mA (typ.) (crystal oscillator frequency 4.5 MHz, CPU only operating) PLL off:IDD = 0.3 mA (typ.) (crystal oscillator frequency 75 kHz, CPU only operating) Operating temperature range: Ta = −40 to 85°C Program memory (ROM): 16 bits × 16,384 steps Data memory (RAM): 4 bits × 4,096 words Instruction execution time: 1.78 µs (crystal oscillator frequency 4.5 MHz) 40 µs (crystal oscillator frequency 75 kHz) Stack levels: 16 General-purpose IF counter: 20-bit (CMOS input supported) AD converter: 8 bits × 8 channels LCD driver: 1/4, 1/3, 1/2 duty, 1/2, 1/3 bias modes selectable, 136 segments maximum I/O ports: CMOS I/O ports: 40 Output-only ports: Up to 31. Input-only ports: Up to 5 Timer-counter: 8-bit (as timer clock: INTR1, INTR2, instruction cycle, 25kHz, or 1 kHz selectable) Pulse counter: 8-bit up/down counter (input from INTR2 pin) Buzzer: 0.625 to 3 kHz (8 settings) Four modes: Continuous, Single-Shot, 10-Hz Intermittent, 10-Hz Intermittent at 1-Hz Intervals Interrupts: 2 external, 4 internal (three types of serial interface, 8-bit timer) Package: QFP-100 (0.65-mm pitch) 1 2006-08-31 TC93P24FG P3-0 (ADIN5) P3-1 (ADIN6) P3-2 (ADIN7) P3-3 (ADIN8) GND2 VDD2 P4-0 P4-1 (SI1/SI2) P4-2 (SO1/SO2) P4-3 (SCK1/SCK2) P5-0 (BUZR) P5-1 (SI3/SI4) P5-2 (SO3/SO4) P5-3 (SCK3/SCK4) MUTE TEST HOLD INTR1 INTR2 (CTRIN) IFIN1 (IN1) IFIN2 (IN2) GND3 FMIN AMIN VDD3 VPLL DO1 DO2 (OUT) TEST2 P6-0 Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P6-1 81 P6-2 82 50 P2-3 (ADIN4) 49 P6-3 83 P2-2 (ADIN3) 58 P7-0 P2-1 (ADIN2) 84 47 P2-0 (ADIN1) P7-1 85 46 DCREF P7-2 86 45 P1-3 P7-3 87 44 P1-2 P8-0 88 43 P1-1 P8-1 89 42 P1-0 P8-2 90 41 GND1 P8-3 91 VCPU PLL Interrupt input SIO SIO I/O ports I/O ports AD converter (8 channels) I/O ports I/O ports QFP-100 (0.65-mm pitch) 40 RESET (VPP) 92 39 VDD1 GND4 93 38 P10-3 (S34) XOUT2 94 37 P10-2 (S33) XIN2 95 36 P10-1 (S32) VDD4 96 35 P10-0 (S31) XOUT1 97 34 P9-3 (S30) XIN1 98 33 P9-2 (S29) GND5 99 32 P9-1 (S28) 31 P9-0 (S27) I/O ports Oscillator 1 (4.5 MHz) LCD driver (1/4, 1/3, 1/2 duty, 1/2, 1/3 bias, 136 segments max) 2 OT30 (S26) OT29 (S25) OT28 (S24) OT27 (S23) OT26 (S22) OT25 (S21) OT9 (S5) OT24 (S20) OT8 (S4) OT23 (S19) OT7 (S3) OT22 (S18) OT6 (S2) OT21 (S17) OT5 (S1) OT20 (S16) OT4 (COM4/S35) OT19 (S15) OT3 (COM3/S36) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 OT18 (S14) 9 OT17 (S13) 8 OT16 (S12) 7 OT15 (S11) 6 OT14 (S10) 5 OT13 (S9) 4 OT12 (S8) 3 OT11 (S7) 2 OT10 (S6) 1 OT2 (COM2) 100 OT1 (COM1) VEE Oscillator 2 (75 kHz) 2006-08-31 TC93P24FG Block Diagram Serial Interface-2 Mute MUTE TEST R/W Buf. G-Reg. Timer P5-3 (SCK3/SCK4) P5-2 (SO3/SO4) HOLD Port5 INTR1 INTR2 (PCTRIN) P5-1 (SI3/SI4) Interrupt Control ALU RAM (4 × 4096 word) Up/Down Counter IFIN1 (IN1) IFIN2 (IN2) IF Counter Buzzer Serial Interface-1 Data Register (16 bit) GND3 FMIN P5-0 (BUZR) P4-3 (SCK1/SCK2) PLL P4-2 (SO1/SO2) AMIN Port4 P4-1 (SI1/SI2) VPLL VPLL P4-0 VDD3 DO1 Phase Comp. DO2 (OUT) VDD2 Instruction Decoder One Time PROM GND2 (16 × 16384 step) P3-3 (ADIN8) Port3 TEST2 P3-0 (ADIN5) P6-0 P2-3 (ADIN4) Port6 P7-0 Port7 Program Counter A/D Conv. Port8 Stack Register (16 level) Port1 P7-3 P8-0 Port2 VPP P6-3 P8-3 P2-0 (ADIN1) DCref P1-3 P1-0 GND1 VPP VCPU VCPU XOUT2 XIN2 75 kHz Oscilator XIN1 VDD1 CPU P10-3 (S34) Port10 OSC Cont. VDD4 XOUT1 RESET (VPP) Reset GND4 P10-0 (S31) Peripheral P9-3 (S30) 4.5 MHz Oscilator Port9 P9-0 (S27) GND5 LCD Driver VEE 3 OT30 (S26) OT29 (S25) OT28 (S24) OT27 (S23) OT26 (S22) OT25 (S21) OT24 (S20) OT23 (S19) OT22 (S18) OT21 (S17) OT20 (S16) OT19 (S15) OT12 (S8) OT11 (S7) OT9 (S5) OT10 (S6) OT8 (S4) OT7 (S3) OT6 (S2) OT5 (S1) OT4 (COM4/S35) OT2 (COM2) OT3 (COM3/S36) OT1 (COM1) Output Port 2006-08-31 TC93P24FG Pin No. Symbol 1 OT1/COM1 Pin Name Output port /LCD common output 2 OT2/COM2 3 OT3/COM3 /S36 4 OT4/COM4 /S35 OT5/S1 ~ 5~30 OT30/S26 P9-0/S27 ~ 31~34 P9-3/S30 P10-0/S31 ~ 35~38 P10-3/S34 40 RESET /VPP Output port /LCD common output /LCD segment output Output port /LCD segment output Function and Operation Remarks Output ports. Pins OT1 to OT20 can be incremented by software, allowing easy data access to external RAM/ROM. Can be set to LCD driver output by software. At 1/4 duty, controller can display up to 136 segments using a matrix consisting of COM1 to 4 and SEG1 to 34. At 1/3 duty, can display up to 105 segments using a matrix consisting of COM1 to 3 and SEG1 to 35. At 1/2 duty, can display up to 72 segments using a matrix consisting of COM1 to 2 and SEG1 to 36. Set to output ports after a system reset or clock stop. VDD VEEH /VEEM /VEEL 4-bit CMOS I/O ports. Input and output can be programmed I/O port 9 /LCD segment output in 1-bit units. These can be set bit by bit to LCD driver output by software. After a system reset, set to I/O port input. When a clock stop is executed, the I/O port 10 Input pins used as the LCD driver must be /LCD segment output set to output Low level (function as an instruction I/O port). Reset input /Program voltage supply Device’s system reset signal input pin. Setting RESET to Low level triggers a reset. When the pin is set to High, the program starts from address 0. Since system reset will start if a voltage beyond 0 V to 3.5 V is supplied to VDD pin, this pin is used by fixed at High level. This pin is used as program voltage supply for One Time PROM. In case of writing program into the internal PROM, 12.5 V is supplied to this pin. VDD VEEH /VEEL VDD 4-bit CMOS I/O port. Input and output can be programmed in 1-bit unit. VDD P1-0 ~ 42~45 I/O port 1 P1-3 Input instruction 4 2006-08-31 TC93P24FG Pin No. Symbol Pin Name 46 DCREF AD converter reference voltage input P2-0 /ADIN1 ~ 47~50 P2-3 /ADIN4 P3-0 /ADIN5 ~ 51~54 P3-3 /ADIN8 I/O port 2 /A/D analog voltage input I/O port 3 /A/D analog voltage input 57 P4-0 I/O port 4 58 P4-1 /SI1 /SI2 Serial data input 1 /Serial data input 2 P4-2 /SO1 /SO2 Serial data input/output 1 /Serial data input 2 59 60 P4-3 /SCK1 /SCK2 Serial clock input/output 1 /Serial clock input 2 Function and Operation Remarks AD converter reference voltage input pin. Normally apply VDD. 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units. Pins P2-0 to P3-3 are also used for the built-in 8-bit, 8-channel AD converter analog input. The built-in AD converter uses a successive comparison system. When using a 4.5 MHz oscillator, the conversion clock can be selected from among 900 kHz, 100 kHz, and 50 kHz. When using a 75 kHz oscillator, the conversion clock is set to 75 kHz. The conversion times are respectively 23, 192, 382, and 294 µs. The necessary pins can be programmed to A/D analog input in 1-bit units. Voltage up to the VDD can be input as the AD converter analog input voltage. Settings for the AD converter and its associated control can be performed by software. 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units. Pins P4-1 to P4-3 also input/output the two serial interface circuits (SIO1, SIO2). On the clock edge of the SCK1 pin, SIO1 can input 4-bit or 8-bit serial data to pin SI1 or input/output data to pin SO1. For the serial operation clock (SCK1), an internal (SCK = 37.5 kHz) or external clock can be selected. This design facilitates LSI control and communication between controllers. Enabling the SIO1 interrupt jumps the program to address 4 when SIO1 execution is complete. On the falling edge of the SCK2 pin, SIO2 can input 26-bit serial data to the SI2 pin. SIO2 incorporates a data detector. Enabling the SIO2 interrupt triggers the interrupt on the falling edge of the SCK2 pin and jumps the program to address 6. The SIO1 and SIO2 inputs all incorporate Schmitt circuits. SIO1 and SIO2 and their associated controls can be operated and set by software. 5 To AD converter VDD To AD converter Input instruction VDD Input instruction (P4-0) VDD Input instruction + SIOon (P4-1~P4-3) 2006-08-31 TC93P24FG Pin No. Symbol Pin Name I/O port 5 /buzzer output 61 P5-0/BUZR 62 P5-1 /SI3 /Serial data input 3 63 P5-2 /SO3 /SO4 /Serial data input/output 3 /Serial data input/output 4 64 P5-3 /SCK3 /SCK4 /Serial clock input/output 3 /Serial clock input/output 4 65 66 MUTE TEST Muting output port Test mode control input Function and Operation Remarks 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit unit. Pin 5-0 is also used to output a buzzer signal. Pins P5-1 to P5-3 are also VDD used to input/output the two serial interface circuits (SIO3, SIO4). The buzzer output can be selected from eight frequency settings (0.625 to 3 kHz), which can be output in four modes: Continuous, Single-Shot, 10 Hz-Intermittent, and 10-Hz Intermittent at 1-Hz Intervals. SIO3 is a serial interface supporting Input instruction three lines, while the SIO4 serial (P5-0) interface supports two lines. On the clock edge of the SCK3/SCK4 pin, SIO3/SIO4 can input 4- or 8-bit serial data to pin SI3 or output data to the SO3/SO4 pin. For the serial operating clock (SCK3/SCK4), an internal (450/225/150/75 kHz) clock or VDD external clock can be selected. Rising and falling shift can also be selected. The clock data output is N-channel open drain. This design facilitates LSI control and communication between controllers. Enabling the SIO3 or SIO4 interrupts triggers the interrupt and jumps the program to address 3 when interface Input instruction + SIOon SIO3 or SIO4 completes execution. (P5-1~P5-3) This is effective for high-speed serial communications. The SIO3 and SIO4 inputs all incorporate Schmitt circuits. SIO3, SIO4, and their associated controls can be used and set by software. 1-bit output port. Normally used as a muting control signal output. This pin can set the internal MUTE bit to 1 according to changes in the I/O port 8 input and HOLD input. The MUTE bit output logic can be changed. VDD Input pin for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). VDD RIN2 6 2006-08-31 TC93P24FG Pin No. 67 68 69 Symbol HOLD INTR1 INTR2 /PCTRin Pin Name Function and Operation Hold mode control input Input pin for requesting and releasing Hold mode. Normally used to input radio mode selection or battery detection signals. Hold mode includes Clock Stop mode (crystal oscillator stopped) and Wait mode (CPU stopped), which can be set by the CKSTP and WAIT instructions respectively. Clock Stop mode can be entered by software in one of two ways: on command or when Low level is detected on the HOLD pin. Clock Stop mode can be released when High level is detected on the HOLD pin or when the input changes. Executing the CKSTP instruction stops the clock generator and CPU, entering memory backup mode. In this state the device is set to low current dissipation (10 µA max). Wait mode is executed, regardless of the HOLD pin input state, and the device is set to low current dissipation. To set wait mode, specify by software either crystal oscillator only operating or CPU suspended. Wait mode is released when the HOLD pin input changes. External interrupt input /pulse count input External interrupt input pins. Enabling the interrupt function and inputting a pulse (of at least 1.11 to 3.33 µs when the 4.5 MHz clock is in use, or at least 13.3 to 40 µs when the 75 kHz clock used) to these input pins generates an interrupt (INTR1/2) and jumps the program to address 1/2. The input logic and the clock edge (rising/falling) can be individually selected for each interrupt input. The internal 8-bit timer clock can be selected as input to the pins. At the pulse count or when the count reaches a specified value, an interrupt can be generated (to address 5). These pins are also used to input an 8-bit pulse counter. This counter can be selected from either rising and falling edge input, or an up-counter and a down-counter. These pins are Schmitt inputs and can also be used as input ports. The pins can also be utilized as ports for inputting remote control signals or tape counts. 7 Remarks VDD VDD 2006-08-31 TC93P24FG Pin No. 70 71 73 74 75 Symbol IFIN1/IN1 IFIN2/IN2 FMIN AMIN VPLL Pin Name Function and Operation IF signal inputs /input port IF signal input pins for the IF counter to count the IF signals of the FM and AM bands and detect the automatic stop position. The input frequency is in the range 0.3 to 20 MHz. A built-in input amp and capacitive coupling support low-amplitude operation. The IF counter is a 20-bit counter with selectable gate times of 1, 4, 16, and 64 ms. 20 bits of data can be easily stored in memory. In Manual mode, the gates can be switched on and off by instruction. These input pins can also be programmed as an input port (IN port). In this case, they become CMOS inputs and the clocks of those inputs can be counted using the IF counter. Note: Pins set as IF input go Low in PLL Off mode. FM local oscillation signal input AM local oscillation signal input Remarks RFIN VDD Programmable counter input pins for the FM/AM band. Their input mode can be switched by software from either 1/2 + pulse swallow (VHF/FM) mode for FM input, or pulse swallow (HF) or direct division (LF) mode for AM input. The local oscillation output (voltage-controlled oscillator or VCO output) is normally input at the following frequencies: 50 to 230 MHz in VHF mode, 50 to 140 MHz in FM1 mode, 10 to 60 MHz in FM2 mode, 1 to 30 MHz in HF mode, and 0.5 to 20 MHz in LF mode. A built-in input amp and capacitive coupling support low-amplitude operation. Note: In PLL Off mode or when the pins are not set for input, the input goes to high impedance. Constant voltage output for the PLL. The PLL constant voltage is used as the power supply for the PLL and IF counter. In PLL On mode, the PLL constant voltage constant voltage power supply is 3.55 output V (typ.). In PLL Off mode, the VDD is output. Connecting a capacitor (0.1 µF, 10 µF typ.) stabilizes the power supply. 8 RFIN VDD RFIN VDD VPLL 2006-08-31 TC93P24FG Pin No. 77 78 79 Symbol DO1 DO2/OUT TEST2 Pin Name Function and Operation Phase comparator output /output port PLL phase comparator output pins. In tri-state output, when the programmable counter divider output is higher than the reference frequency, the pins output High level; when the output is lower than the reference frequency, the pins output Low level. When the outputs match, the pins go to high impedance. Because DO1 and DO2 are output in parallel, optimal filter constants can be designed for both the AM and FM bands. The DO2 pin can be programmed to high impedance or set as an output port (OUT). Therefore, lockup time can be improved using the DO1 and DO2 pins or the pins can be effectively used as output ports. Lock-up time can also be improved by using DO1 and DO2 together by setting the pins to High-Speed Lock mode when using a 4.5 MHz oscillator. When the phase difference equals or exceeds ±1.11 µs, DO1 and DO2 output the phase difference pulse. When the phase difference is less than ±1.11 µs, the DO2 output goes to high impedance and only DO1 outputs the phase difference pulse. Test mode control input 2 Remarks VDD Input pin for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). VDD RIN2 P6-0 ~ 80~83 I/O port 6 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units. VDD P6-3 P7-0 ~ 84~87 Input instruction I/O port 7 P7-3 P8-0 ~ 88~91 P8-3 I/O port 8 4-bit CMOS I/O port. Input and output can be programmed in 1-bit units. As the pins can be pulled up or pulled down by software they can be used as key input pins. When set to an I/O port input, that input can be varied to release Clock Stop or Wait modes or to set the MUTE bit of the MUTE pin to 1. VDD VDD VDD RIN1 9 2006-08-31 TC93P24FG Pin No. 92 94 Symbol VCPU Pin Name CPU constant voltage output XOUT2 75 kHz crystal oscillator pins 95 97 XIN2 XOUT1 Function and Operation Remarks Constant voltage output pin for the CPU or oscillators. In normal mode, a constant voltage power supply of 2.95 V (typ.) is output; in Clock Stop mode, VDD is output. Connecting a capacitor (0.1 µF, 10 µF typ.) stabilizes the power supply. Crystal oscillator pins. Connect a 4.5 MHz crystal (Ci = Co = 30 pF typ.) to XIN1 and XOUT1 and a 75 kHz crystal (Ci = Co = 30 pF typ.) to XIN2 and XOUT2. Two different types of crystal resonators (4.5 MHz and 75 kHz) can be connected, or simply connect one (either 4.5 MHz or 75 kHz). Note that if a 75 kHz crystal only is connected, XIN1 must be fixed to GND level. If a 4.5 MHz crystal only is connected, it is not necessary to fix the 75 kHz crystal oscillator pins. If both 4.5 MHz and 75 kHz crystal oscillators are connected, after a reset the CPU operates on the 4.5 MHz crystal oscillator clock. The clock can be readily switched by software between the CPU operating clock and the peripheral clock. Oscillation stops during execution of the CKSTP instruction. VCPU XOUT2 ROUT2 RfXT2 VDD XIN2 XOUT1 ROUT1 RfXT1 VDD 4.5 MHz crystal oscillator pins 98 XIN1 100 VEE 39 56 76 96 41 55 72 93 99 LCD driver bias voltage output pin This is the bias voltage output pin for the LCD driver. Power supply pins Pins used for supplying power. In PLL On mode, the pins supply VDD = 4.0 to 5.5 V; in PLL Off mode, the pins supply VDD = 3.5 to 5.5 V. In backup state (on execution of the CKSTP instruction), current dissipation becomes low (10 µA max), reducing the power supply voltage to 2.0 V. If 3.5 V or more is applied to these pins when the voltage is 0 V, a system reset is applied to the device and the program starts from address 0 (power-on reset). Note: To operate the power-on reset, allow 10 to 100 ms while the device power supply voltage rises. VDD1 VDD2 VDD3 VDD4 GND1 GND2 GND3 GND4 GND5 XIN1 10 ⎯ VDD GND 2006-08-31 TC93P24FG Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Power supply voltage VDD −0.3~6.0 V VPP Power supply voltage VPP −0.3~13.0 V Input voltage 1 VIN1 (*) −0.3~VCPU + 0.3 V Input voltage 2 VIN2 (*) −0.3~VPLL + 0.3 V Input voltage 3 VIN3 (*) −0.3~VDD + 0.3 V Power dissipation PD 400 mW Operating temperature Topr −40~85 °C Storage temperature Tstg −65~150 °C *: VIN1: Includes XIN1, XOUT1, XIN2, and XOUT2 pins VIN2: Includes AMin, FMin, IFin1, IFin2 (when IF input set) pins VIN3: Input pins, apart from VIN1 and VIN2 Electrical Characteristics (unless otherwise specified, Ta = −40~85°C, VDD = 3.5~5.5 V) Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit VDD1 ⎯ When CPU operating 3.5 ~ 5.5 VDD2 ⎯ When PLL operating 4.0 ~ 5.5 VHD ⎯ Crystal oscillation stopped (CKSTP instruction executed) 2.0 ~ 5.5 IDD1 ⎯ When PLL operating (VHF mode) and at FMin = 230 MHz input, Ta = 25°C ⎯ 3 5 IDD2 ⎯ When CPU only operating (4.5-MHz clock operating, 75-kHz oscillation stopped, PLL off, display lit), Ta = 25°C ⎯ 1.0 1.5 IDD3 ⎯ When CPU only operating (75-kHz clock operating, 4.5-MHz oscillation stopped, PLL off, display lit), Ta = 25°C ⎯ 0.3 0.5 IDD4 ⎯ In Hard Wait mode (4.5-MHz crystal only operating), Ta = 25°C ⎯ 200 ⎯ IDD5 ⎯ In Hard Wait mode (75-kHz crystal only operating), Ta = 25°C ⎯ 70 ⎯ IDD6 ⎯ When soft wait executed (PLL off, CPU operating intermittently on 4.5-MHz clock, display lit), Ta = 25°C ⎯ 350 ⎯ IDD7 ⎯ When soft wait executed (PLL off, CPU operating intermittently on 75-kHz clock, display lit), Ta = 25°C ⎯ 250 ⎯ IHD ⎯ Crystal oscillator stopped (CKSTP instruction executed) ⎯ 0.1 10 µA fXT1 ⎯ Crystal oscillator 1 (XIN1, XOUT1) ⎯ 4.5 ⎯ MHz fXT2 ⎯ Crystal oscillator 2 (XIN2, XOUT2) ⎯ 75 ⎯ kHz Crystal oscillation startup time tst ⎯ Crystal oscillator fXT2 = 75 kHz (XIN2, XOUT2) ⎯ ⎯ 1.0 s Constant voltage power supply voltage for CPU VCPU ⎯ GND reference (VCPU) 2.65 2.95 3.25 V Constant voltage power supply voltage for PLL VPLL ⎯ GND reference (VPLL), VDD = 4.0 to 5.5 V 3.15 3.55 3.95 V Low voltage detection voltage VSTOP ⎯ (VCPU), STOP F/F bit detected 2.15 2.40 2.65 V Operating power supply voltage range Memory hold voltage range Operating power supply current Memory hold current Crystal oscillator frequency 11 V V mA µA 2006-08-31 TC93P24FG Programmable Counter and IF Counter Operating Frequency Ranges Characteristics FMin (VHF mode) Symbol Test Circuit Test Condition Min Typ. Max fVHF ⎯ VIN = 0.2 Vp-p, VDD = 4.0~5.5 V 50 ~ 230 fFM1 ⎯ VIN = 0.1 Vp-p, VDD = 4.0~5.5 V 50 ~ 140 FMin (FM mode) fFM2 ⎯ VIN = 0.1 Vp-p, VDD = 4.0~5.5 V 10 ~ 60 AMin (HF mode) fHF ⎯ VIN = 0.1 Vp-p, VDD = 4.0~5.5 V 1.0 ~ 30 AMin (LF mode) fLF ⎯ VIN = 0.1 Vp-p, VDD = 4.0~5.5 V 0.5 ~ 20 IFIN1, IFIN2 fIF ⎯ VIN = 0.1 Vp-p, VDD = 4.0~5.5 V 0.3 ~ 20 Unit MHz Programmable Counter and IF Counter Input Oscillation Ranges Symbol Test Circuit FMin (VHF mode) VVHF FMin (FM mode) AMin (HF mode) Characteristics Test Condition Min Typ. Max ⎯ fVHF, VDD = 4.0~5.5 V 0.2 ~ 1.0 VFM ⎯ fFM1/fFM2, VDD = 4.0~5.5 V 0.1 ~ 1.0 VHF ⎯ fHF, VDD = 4.0~5.5 V 0.1 ~ 1.0 AMin (LF mode) VLF ⎯ fLF, VDD = 4.0~5.5 V 0.1 ~ 1.0 IFIN1, IFIN2 VIF ⎯ fIF, VDD = 4.0~5.5 V 0.1 ~ 1.0 Min Typ. Max Unit Vp-p LCD Common Outputs/Segment Outputs (COM~COM4, S1~S22) Symbol Test Circuit GND level VBS1 ⎯ VDD = 5 V, no load ⎯ 0.00 0.15 1/3 VDD level VBS2 ⎯ VDD = 5 V, no load 1.52 1.67 1.82 1/2 VDD level VBS3 ⎯ VDD = 5 V, no load 2.35 2.50 2.65 2/3 VDD level VBS4 ⎯ VDD = 5 V, no load 3.18 3.33 3.48 VDD level VBS5 ⎯ VDD = 5 V, no load 4.85 5.00 ⎯ Test Condition Min Typ. Max Characteristics Bias output voltage Test Condition Unit V Output Ports and I/O Ports (OT1~OT30, P1-0~P10-3) Symbol Test Circuit IOH1 ⎯ VDD = 5 V, VOH = VDD − 0.5 V −1.00 −2.50 ⎯ IOL1 ⎯ VDD = 5 V, VOL = 0.5 V, except for P5-1 to P5-3 1.00 2.50 ⎯ IOL2 ⎯ VDD = 5 V, VOL = 0.5V, P5-1~P5-3 4.00 10.00 ⎯ ILI ⎯ VIH = VDD, VIL = 0V (P1-0~P10-3) ⎯ ⎯ ±1.0 High level VIH ⎯ (P1-0~P10-3) VDD × 0.8 ~ VDD Low level VIL ⎯ (P1-0~P10-3) 0 ~ VDD × 0.2 RIN1 ⎯ When P8-0 to P8-3 pulled up/down 15 60 250 Characteristics High level Output current Low level Input leakage current Input voltage Input pulled-up/down resistor 12 Unit mA µA V kΩ 2006-08-31 TC93P24FG MUTE, DO1, DO2 Output Symbol Test Circuit Test Condition Min Typ. Max High level IOH1 ⎯ VDD = 5 V, VOH = VDD − 0.5 V −1.25 −2.50 ⎯ Low level IOL1 ⎯ VDD = 5 V, VOL = 0.5 V 1.25 2.50 ⎯ ITL ⎯ VDD = 5 V, VTLH = 5 V, VTLL = 0 V (DO1, DO2) ⎯ ⎯ ±100 nA Min Typ. Max Unit ⎯ ⎯ ±1.0 µA Characteristics Output current Output off leakage current Unit mA HOLD , INTR1/2, IN1/2 Input Ports, RESET Input Symbol Test Circuit ILI ⎯ High level VIH ⎯ ⎯ VDD × 0.8 ~ VDD Low level VIL ⎯ ⎯ 0 ~ VDD × 0.2 Symbol Test Circuit Test Condition Min Typ. Max Unit VAD ⎯ 0 ~ VDD V Resolution VRES ⎯ ⎯ ⎯ 8 ⎯ bit Linear error ⎯ ⎯ ⎯ ⎯ ±0.5 ±1.0 Conversion total error ⎯ ⎯ VDD = 5 V, DCREF = 5 V ⎯ ±3.0 ±8.0 Analog input leakage ILI ⎯ VDD = 5V, VIH = 5V, VIL = 0 V (ADin1~ADin8) ⎯ ⎯ ±1.0 µA IREF ⎯ VDD = 5V, DCREF = 5 V (DCREF) ⎯ 0.5 1.0 mA Symbol Test Circuit Min Typ. Max Unit XIN1 amp feedback resistance RfXT1 ⎯ (XIN1−XOUT1) 0.35 1.0 3.00 XIN2 amp feedback resistance RfXT2 ⎯ (XIN2−XOUT2) 3.5 10 30.0 XOUT1 output resistance ROUT1 ⎯ (XOUT1) 1.2 3.0 10.0 XOUT2 output resistance ROUT2 ⎯ (XOUT2) 1.5 4.0 15.0 Symbol Test Circuit Min Typ. Max Input pulled-down resistance RIN2 ⎯ (TEST) 15.0 60 250 Input amp feedback resistance RfIN ⎯ VPLL = 3.5 V (FMin, AMin, IFin1, IFin2) 350 800 3500 Characteristics Input leakage current Output current Test Condition VIH = VDD, VIL = 0 V V AD Converter (ADIN1~ADIN8, DCREF) Characteristics Analog input voltage range Reference voltage input current ADin1~ADin8 LSB Crystal Oscillators Characteristics Test Condition MΩ kΩ Others Characteristics Test Condition 13 Unit kΩ 2006-08-31 TC93P24FG Package Dimensions Weight: 1.6 g (typ.) Note: Lead type PD-Pff 14 2006-08-31 TC93P24FG RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E 15 2006-08-31