FAIRCHILD SG5842JADZ

SG5842A/SG5842JA — Highly Integrated Green-Mode
PWM Controller
Features
Description
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Green-Mode PWM Controller
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Peak-Current-Mode Control
The highly integrated SG5842A/JA series of PWM
controllers provides several features to enhance the
performance of flyback converters. To minimize standby
power consumption, a proprietary green-mode function
provides off-time modulation to continuously decrease
the switching frequency at light-load conditions. To
avoid acoustic-noise problems, the minimum PWM
frequency set above 22KHz. This green-mode function
enables the power supply to meet international power
conservation requirements. To further reduce power
consumption, SG5842A/JA is manufactured using the
BiCMOS process. This allows a low startup current,
around 14µA, and an operating current of only 4mA. As
a result, a large startup resistance can be used.
Low Startup Current: 14µA
Low Operating Current: 4mA
Programmable PWM Frequency with Hopping
(SG5842JA)
Cycle-by-Cycle Current Limiting
Synchronized Slope Compensation
Leading-Edge Blanking (LEB)
Constant Output Power Limit
Totem-Pole Output with Soft Driving
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Internal Latch Circuit (OTP, OVP)
Internal Open-Loop Protection
VDD Under-Voltage Lockout (UVLO)
GATE Output Maximum Voltage Clamp: 18V
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
ƒ
ƒ
Notebook Power Adapters
The
SG5842A/JA
built-in
synchronized
slope
compensation achieves stable peak-current-mode
control. SG5842JA integrates a frequency-hopping
function that helps reduce EMI emission of a power
supply with minimum line filters.
SG5842A/JA provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety should an
open-loop or output short-circuit failure occur. PWM
output is disabled until VDD drops below the UVLO lower
limit, then the controller starts again. As long as VDD
exceeds about 24V, the internal OVP circuit is triggered.
An external NTC thermistor can be applied for overtemperature protection.
SG5842A/JA is available in an 8-pin DIP or SOP
package.
Open-Frame SMPS
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
December 2009
Part Number
Operating
Temperature
Range
Eco
Status
Package
OTP
Latch
SG5842JASZ
-40°C to +105°C
RoHS
8-Pin Small Outline Package (SOP)
Yes
Yes
Yes
SG5842JADZ
-40°C to +105°C
RoHS
8-Pin Dual Inline Package (DIP)
Yes
Yes
Yes
SG5842JASY
-40°C to +105°C
Green
8-Pin Small Outline Package (SOP)
Yes
Yes
Yes
SG5842ASZ
(Preliminary)
-40°C to +105°C
RoHS
8-Pin Small Outline Package (SOP)
Yes
Yes
No
SG5842ASY
(Preliminary)
-40°C to +105°C
Green
8-Pin Small Outline Package (SOP)
Yes
Yes
No
OVP Frequency
Latch Hopping
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Application Diagram
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Ordering Information
Figure 1. Application Diagram
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
2
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Block Diagram
Figure 2. Function Block Diagram
Marking Information
H: J = with Frequency Hopping
Null = without Frequency
Hopping
T: D = DIP, S = SOP
P: Z = Lead Free
Null = Regular Package
XXXXXXXX: Wafer Lot
Y: Year; WW: Week
V: Assembly Location
SG5842HATP
XXXXXXXXYWWV
Marking for SG5842JASZ (pb-free)
Marking for SG5842JADZ (pb-free)
Marking for SG5842ASZ (pb-free)
Marking for SG5842ADZ (pb-free)
ZXYTT
SG5842HA
TPM
Marking for SG5842JASY (green-compound)
Marking for SG5842ASY (green-compound)
F- Fairchild Logo
Z- Plant Code
X- 1 Digit Year Code
Y- 1 Digit week Code
TT: 2 Digits Die Run Code
T: Package Type (S=SOP, D=DIP)
P: Y: Green Package
M: Manufacture Flow Code
Figure 3. Top Mark
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
3
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
GND
2
FB
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal from this pin and the current-sense signal from Pin 6. If FB
voltage exceeds the threshold, the internal protection circuit disables PWM output after a
predetermined delay time.
3
VIN
For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since the startup
current requirement is very small, a large startup resistance can be used to minimize power loss.
4
RI
A resistor connected from the RI pin to GND provides a constant current source. This determines
the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ
resistor results in a 65KHz center PWM frequency.
5
RT
For over-temperature protection. An external NTC thermistor is connected from this pin to the
GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the
RT pin drops below a fixed limit, PWM output is latched off.
6
SENSE
7
VDD
8
GATE
Ground
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Pin Configuration
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
Power supply. The internal protection circuit disables PWM output if VDD is over-voltage.
The totem-pole output driver for the power MOSFET, which is internally clamped below 18V.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
(1)
Max.
Unit
30
V
VVDD
Supply Voltage
VVIN
Input Terminal
30
V
VFB
Input Voltage to FB Pin
-0.3
7.0
V
Input Voltage to SENSE Pin
-0.3
7.0
V
VSENSE
VRT
Input Voltage to RT Pin
-0.3
7.0
V
VRI
Input Voltage to RI Pin
-0.3
7.0
V
PD
Power Dissipation (TA < 50°C )
ΘJA
Thermal Resistance (Junction-to-Air)
TJ
Operating Junction Temperature
-40
DIP
800
SOP
400
DIP
82.5
SOP
141
+125
Storage Temperature Range
-55
+150
°C
+260
°C
TSTG
TL
ESD
Lead Temperature (Wave Soldering or Infrared, 10 Seconds)
Electrostatic Discharge Capability
Human Body Model,
JESD22-A114
3
Charged Device
Model, JESD22-C101
1
mW
°C/W
°C
KV
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
Min.
Max.
Unit
-20
+85
°C
www.fairchildsemi.com
5
VDD=15V and TJ=TA= -40~125°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
20
V
V
VDD Section
VDD-OP
Continuously Operating Voltage
VDD-ON
Start Threshold Voltage
VDD-OFF
Minimum Operation Voltage
15.5
16.5
17.5
9.5
10.5
11.5
V
IDD-ST
Startup Current
VDD=VDD-ON–0.16V
14
30
µA
IDD-OP
Operating Supply Current
VDD=15V, RI=26KΩ,
GATE=OPEN
4
5
mA
24.2
25.2
V
VDD-OVP
VDD Over-Voltage Protection
23.2
tD-OVP
VDD Over-Voltage Protection
Debounce Time
RI=26KΩ
IDD-H
Holding Current After OVP/OTP
Latchup
VDD=5V
100
40.0
52.5
µs
65.0
µA
36.0
KΩ
RI Section
RINOR
RI Operating Range
15.5
RIMAX
Maximum RI Value for Protection
230
KΩ
RIMIN
Minimum RI Value for Protection
10
KΩ
Oscillator Section
Center
Frequency
RI=26KΩ
Hopping Range
62
65
68
RI=26KΩ
SG5842JA Only
±3.7
±4.2
±4.7
Hopping Period
RI=26KΩ
SG5842JA Only
3.9
4.4
4.9
ms
Green-Mode Minimum Frequency
RI=26KΩ
18
22
25
KHz
fDV
Frequency Variation vs. VDD
Deviation
VDD=11.5V to 20V
5
%
fDT
Frequency Variation vs.
Temperature Deviation
TA=-20 to 85°C
5
%
1/3.5
V/V
7
KΩ
fOSC
tHOP
fOSC-G
Normal PWM
Frequency
KHz
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
Feedback Input Section
AV
FB Input to Current Comparator
Attenuation
ZFB
Input Impedance
VFB-OPEN
VFB-OLP
Output High Voltage
1/4.5
1/4.0
4
FB Pin Open
FB Open-Loop Trigger Level
5.5
V
5.4
V
tD-OLP
FB Open-Loop Protection Delay
RI=26KΩ
5.0
50
56
62
ms
VFB-N
Green-Mode Entry FB Voltage
RI=26KΩ
1.9
2.1
2.3
V
VFB-G
Green-Mode Ending FB Voltage
RI=26KΩ
VFB-N-0.5
V
Continued on the following page…
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
www.fairchildsemi.com
6
VDD= 15V and TJ=TA= -40~125°C, unless otherwise noted.
Figure 5. VFB vs. PWM Frequency
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Current Sense Section
ZSENSE
Input Impedance
VSTHFL
Current Limit Flatten Threshold
Voltage
VSTHVA
Current Limit Valley Threshold
Voltage
DCYSAW
12
0.85
VSTHFL–VSTHVA
0.90
KΩ
0.95
0.22
V
V
Duty Cycle of SAW Limit
Maximum Duty Cycle
45
tPD
Propagation Delay to GATE Output
RI=26KΩ
150
200
ns
%
tLEB
Leading-Edge Blanking Time
RI=26KΩ
200
270
350
ns
60
65
70
%
1.5
V
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
GATE Section
DCYMAX
Maximum Duty Cycle
VGATE-L
Output Voltage Low
VDD=15V, IO=50mA
VGATE-H
Output Voltage High
VDD=12.5V, IO=-50mA
7.5
tr
Rising Time
VDD=15V, CL=1nF
150
250
350
tf
Falling Time
VDD=15V, CL=1nF
30
50
90
IO
Peak Output Current
VDD=15V, GATE=6V
230
Gate Output Clamping Voltage
VDD=20V
Output Current of RT Pin
RT Section
RI=26KΩ
VGATECLAMP
IRT
VRTTH
Over-Temperature Protection
Threshold Voltage
tD-OTP
Over-Temperature Debounce
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
RI=26KΩ
V
ns
ns
mA
18
19
V
67
70
73
µA
1.015
1.050
1.085
V
60
100
140
µs
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7
5.0
26
4.5
22
4.0
IDD-OP (mA)
IDD-ST (µA)
30
18
14
10
3.5
3.0
2.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature °C
Figure 6. Startup Current (IDD-ST) vs. Temperature
35
50
65
80
95
110
125
Figure 7. Operating Supply Current (IDD-OP)
vs. Temperature
15
17.5
12
17.0
VDD-ON (V)
IDD-OP (mA)
20
Temperature °C
9
GATE=1000pF
6
16.5
16.0
3
GATE=OPEN
15.5
0
12
13
14
15
16
17
18
19
20
21
22
23
-40
24
-25
-10
5
20
35
50
65
80
95
110
125
Temperature °C
VDD Voltage (V)
Figure 8. Operation Current (IDD-OP) vs. VDD
Operation
Figure 9. Start Threshold (VDD-ON) vs. Temperature
11.5
68
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Performance Characteristics
67
fOSC (Khz)
VDD-OFF (V)
11.0
10.5
66
65
64
10.0
63
9.5
-40
-25
-10
5
20
35
50
65
80
95
110
62
125
-40
Temperature °C
-10
5
20
35
50
65
80
95
110
125
Temperature °C
Figure 10. Minimum Operating Voltage (VDD-OFF)
vs. Temperature
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
-25
Figure 11. PWM Frequency (fOSC) vs. Temperature
www.fairchildsemi.com
8
1.085
70
1.075
68
VRTTH (V)
DCYmax (%)
1.065
66
64
62
1.055
1.045
1.035
1.025
1.015
60
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
-25
-10
5
20
Figure 12. Maximum Duty Cycle (DCYmax)
vs. Temperature
Figure 13.
IRT (µA)
72
71
70
69
68
67
-25
-10
5
20
35
50
65
80
95
110
125
Temperature °C
Figure 14. Output Current of RT Pin (IRT) vs. Temperature
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
50
65
80
95
110
Trigger Voltage for Over-Temperature
Protection (VRTTH) vs. Temperature
73
-40
35
Temperature °C
Temperature °C
125
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Performance Characteristics (Continued)
www.fairchildsemi.com
9
Startup Current
Under-Voltage Lockout (UVLO)
The typical startup current is only 14µA, which allows a
high-resistance, low-wattage startup resistor to be used to
minimize power loss. A 1.5MΩ/0.25W startup resistor and
a 10µF/25V VDD hold-up capacitor are sufficient for an
AC/DC adapter with a universal input range.
The turn-on/turn-off thresholds are fixed internally at
16.5V/10.5V. To enable a SG5842A/JA controller during
startup, the hold-up capacitor must first be charged to
16.5V through the startup resistor.
The required operating current has been reduced to
4mA. This results in higher efficiency and reduces the
VDD hold-up capacitance requirement.
The hold-up capacitor continues to supply VDD before
energy can be delivered from the auxiliary winding of
the main transformer. VDD must not drop below 10.5V
during this startup process. This UVLO hysteresis
window ensures that the hold-up capacitor can
adequately supply VDD during startup.
Green-Mode Operation
Gate Output / Soft Driving
Operating Current
The proprietary green-mode function provides off-time
modulation to continuously decrease the PWM
frequency under light-load conditions. To avoid acoustic
noise problems, the minimum PWM frequency is set
above 22KHz. This green-mode function dramatically
reduces power consumption under light-load and zeroload conditions. Power supplies using this controller can
meet even the strictest international standby power
regulations.
The SG5842A/JA BiCMOS output stage is a fast totempole gate driver. Cross-conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect the power MOSFET
transistors from harmful over-voltage gate signals. A
soft-driving waveform is implemented to minimize EMI.
Slope Compensation
The sensed voltage across the current sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. The built-in slope compensation
function improves power supply stability and prevents
peak-current-mode control from causing sub-harmonic
oscillations. Within every switching cycle, the
SG5842A/JA controller produces a positively sloped,
synchronized ramp signal.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the controller.
This current is used to determine the center PWM
frequency. Increasing the resistance reduces PWM
frequency. Using a 26KΩ resistor, RI, results in a
corresponding 65KHz PWM frequency. The relationship
between RI and the switching frequency is:
fPWM =
1690
(KHz)
RI (KΩ )
Constant Output Power Limit
(1)
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage, around 0.85V; the
output GATE drive is turned off after a small delay, tPD.
This delay introduces additional current proportional to
tPD • VIN / LP. The delay is nearly constant regardless of
the input voltage VIN. Higher input voltage results in a
larger additional current and the output power limit is
higher than under low input line voltage. To compensate
this variation for a wide AC input range, a sawtooth
power-limiter (saw limiter) is designed to solve the
unequal power-limit problem. The saw limiter is
designed as a positive ramp signal (VLIMIT_RAMP) fed to
the inverting input of the OCP comparator. This results
in a lower current limit at high-line inputs than at lowline inputs.
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
SG5842JA also integrates a frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency hopping function helps reduce EMI emission
of a power supply with minimum line filters.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Functional Description
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection is built in to prevent
damage due to abnormal conditions. Once the VDD
voltage is over the VDD over-voltage protection voltage
(VDD-OVP) and lasts for tD-OVP, the PWM pulse is latched
off. The PWM pulses stay latched off until the power
supply is unplugged from the mains outlet.
www.fairchildsemi.com
10
Limited Power Control
Thermal Protection
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold longer than tDOLP, PWM output is turned off. As PWM output is turned
off, the supply voltage VDD begins decreasing.
An external NTC thermistor can be connected from the
RT pin to ground. A fixed current, IRT, is sourced from
the RT pin. Because the impedance of the NTC
decreases at high temperatures, when the voltage of
the RT pin drops below 1.05V, PWM output is latched
off. The RT pin output current is related to the PWM
frequency programming resistor RI.
t D - OLP (ms) = 2 . 154 × R I (K Ω )
(2)
When VDD goes below the turn-off threshold (eg.
10.5V), the controller is totally shut down. VDD is
charged up to the turn-on threshold voltage of 16.5V
through the startup resistor until PWM output is
restarted. This protection feature remains activated as
long as the overloading condition persists. This
prevents the power supply from overheating due to
overloading conditions.
Noise Immunity
Noise from the current sense or the control signal may
cause significant pulse width jitter, particularly in
continuous-conduction mode. Slope compensation
helps alleviate this problem. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads. Compensation and filter
components should be located near the SG5842A/JA.
Increasing the power-MOS gate resistance is advised.
Protection Latch Circuit
The built-in latch function provides a versatile protection
feature that does not require external components (see
ordering information for a detailed description). To reset
the latch circuit, disconnect the AC line voltage of the
power supply.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Functional Description (Continued)
www.fairchildsemi.com
11
2
Q1
BD1
CN1
4
L2
C1
VZ1
C2
4
L3
1
2
Vo+
2
C6
3
1
3
+ C8
R2
R7
D2
2
2
R5
2
1
1
C5
R1
D3
C7 +
R4
1
1
3
1
C3
+
D1
R3
2
2
3
C4
TR1
2
T1
1
1
L1
2
1
2
3
4
2
1
Q2
U1
VIN SENSE
4
R9
RI
RT
R12
R16
6
5
R11
R10
SG5842A/JA
C11
+
R8
4
THER2
C9
1
3
VDD
7
3
FB
1
8
2
GND GATE
2
1
1
1
2
D4
U2
K 2
3
R13
C10
R14
R
U3
VO+
A
R15
Figure 15. Reference Circuit
BOM
Reference
Component
Reference
Component
BD1
BD 4A/600V
Q2
MOS 7A/600V
C1
XC 0.68µF/300V
R1, R2, R5, R7
R 470KΩ 1/4W
C2
XC 0.1µF/300V
R3
R 100KΩ 1/2W
C3
CC 0.01µF/500V
R4
R 47Ω 1/4W
C4
EC 120µ/400V
R6
R 2KΩ 1/8W
C5
YC 222p/250V
R8
R 0.3Ω 2W
C6
CC 1000pF/100V
R9
R 33KΩ 1/8W
C7
EC 1000µF/25V
R10
R 4.7KΩ 1/8W
C8
EC 470µF/25V
R11
R 470Ω 1/8W
R 0Ω 1/8W
C9
EC 10µF/50V
R12
C10
CC 222pF/50V
R13
R 4.7KΩ 1/8W
C11
CC 470pF/50V
R14
R 154KΩ 1/8W 1%
D1
LED
R15
R 39KΩ 1/8W 1%
D2
Diode BYV95C
R16
R 100Ωm 1/8W
D3
TVS P6KE16A
D4
Diode FR103
THER2
Thermistor TTC104
T1
Transformer (600µH-PQ2620)
F1
FUSE 4A/250V
U1
IC SG5842A/JA
L1
Choke (900µH)
U2
IC PC817
L2
Choke (10mH)
U3
IC TL431
L3
Inductor (2µH)
VZ1
VZ 9G
Q1
Diode 20A/100V
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
R6
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
Reference Circuit
www.fairchildsemi.com
12
5.00
4.80
A
0.65
3.81
5
8
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
R0.10
0.10
0.51
0.33
0.50 x 45°
0.25
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
8°
0°
0.90
0.406
0.25
0.19
C
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
Physical Dimensions
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 16.
8-Pin, Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
13
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
Physical Dimensions (Continued)
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
5.08 MAX
7.62
0.33 MIN
3.60
3.00
(0.56)
2.54
0.56
0.355
0.356
0.20
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 17.
8-Pin, Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
14
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com
15