FAIRCHILD FAN6753

FAN6753
Highly Integrated Green-Mode PWM Controller
Features
Description
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The highly integrated FAN6753 PWM controller
provides several features to enhance the performance
of flyback converters.
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High-Voltage Startup
Low Operating Current: 2.7mA
Adaptive Decreasing PWM Frequency to 22KHz
Built-in Full-Range Frequency Hopping to Reduce
EMI Emission
Fixed PWM Frequency: 65KHz
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Internal Auto-Recovery Open-Loop Protection
GATE Output Maximum Voltage Clamp: 18V
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP),
Auto Recovery / Latch for Option
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Internal Auto-Recovery Sense Short-Circuit
Protection for Option
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Constant Power Limit (Full AC Input Range)
To minimize standby power consumption, a proprietary
adaptive green-mode function provides frequency
modulation at light-load conditions. To avoid acousticnoise problems, the minimum PWM frequency is set
above 22KHz. This green-mode function enables the
power supply to meet international power conservation
requirements. With the internal high-voltage startup
circuitry, the power loss due to bleeding resistors is also
eliminated. To further reduce power consumption,
FAN6753 is manufactured using the BiCMOS process,
which allows an operating current of only 2.7mA.
FAN6753 integrates a full-range frequency-hopping
function internally that helps reduce EMI emission of a
power supply with minimum line filters. Its built-in
synchronized slope compensation achieves stable
peak-current-mode control. The proprietary internal line
compensation ensures constant output power limit over
a wide AC input voltage range, from 90VAC to 264VAC.
FAN6753 provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety should an
open-loop or output short-circuit failure occur. PWM
output is disabled until VDD drops below the UVLO lower
limit, when the controller starts up again. As long as VDD
exceeds ~26V, the internal OVP circuit is triggered.
Internal OTP Sensor with Hysteresis
Built-in 5ms Soft-Start Function
Built-in LATCH Pin Pull HIGH (> 5.2V)
Latch Function
FAN6753 is available in an 8-pin SOP package.
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
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Power Adapters
Open-Frame SMPS
Ordering Information
Part Number
Operating
Temperature Range
FAN6753MY
-40°C to +105°C
Eco Status
Green
Package
Packing Method
8-Lead, Small Outline Package
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
FAN6753 — Highly Integrated Green-Mode PWM Controller
July 2009
FAN6753 — Highly Integrated Green-Mode PWM Controller
Marking Information
F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M:SOP)
P: Y=Green Package
M: Manufacture Flow Code
ZXYTT
6753
TPM
Figure 1. Top Mark
Pin Configuration
SOP-8
LATCH
1
8
HV
FB
2
7
NC
SENSE
3
6
VDD
GND
4
5
GATE
Figure 2. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
1
LATCH
2
FB
3
SENSE
Description
For external latch circuit used. When VLATCHth > 5.2V and after 100µs, IC is latched off.
10KΩ to GND is recommended. Internal has a sourcing current of 100µA (ILATCH), 100µA
×10KΩ. The voltage on this pin is 1V (under VLATCHth=5.2V).
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
4
GND
Ground.
5
GATE
The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.
6
VDD
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
7
NC
No connection.
8
HV
For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
2
Figure 3. Typical Application
Internal Block Diagram
FAN6753 — Highly Integrated Green-Mode PWM Controller
Application Diagram
Figure 4. Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
VFB
Parameter
DC Supply Voltage
Min.
(1, 2)
Max.
Unit
30
V
FB Pin Input Voltage
-0.3
7.0
V
VSENSE
SENSE Pin Input Voltage
-0.3
7.0
V
VLATCH
LATCH Pin Input Voltage
-0.3
7.0
V
VHV
HV Pin Input Voltage
500
V
PD
Power Dissipation (TA＜50°C)
400
mW
Thermal Resistance (Junction-to-Air)
141
°C/W
+125
°C
θ JA
TJ
TSTG
TL
ESD
Operating Junction Temperature
-40
Storage Temperature Range
-55
+150
°C
+260
°C
Human Body Model,
JEDEC:JESD22-A114
5.5
kV
Charged Device Model,
JEDEC:JESD22-C101
1500
V
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Electrostatic Discharge Capability
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
FAN6753 — Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
4
VDD=15V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
VDD Section
VOP
Continuously Operating Voltage
22
V
VDD-ON
Start Threshold Voltage
14.5
15.5
16.5
V
VDD-OFF
Minimum Operating Voltage
8.5
9.5
10.5
V
30
µA
IDD-ST
Startup Current
VDD-ON – 0.16V
IDD-OP
Operating Supply Current
VDD=15V, GATE Open
IDD-OLP
Internal Sink Current
VTH-OLP+0.1V
2.7
3.7
mA
30
60
90
µA
VTH-OLP
IDD-OLP Off Voltage
6.5
7.5
8.0
V
VDD-OVP
VDD Over-Voltage Protection
25
26
27
V
tD-VDDOVP
VDD Over-Voltage Protection Debounce Time
75
125
200
µs
2.0
3.5
5.0
mA
1
20
µA
65
68
HV Section
IHV
IHV-LC
Supply Current Drawn from HV Pin
VAC=90V (VDC=120V),
VDD=0V
Leakage Current after Startup
HV=500V,
VDD=VDD-OFF+1V
Oscillator Section
62
Center Frequency
fOSC
Frequency in Nominal Mode
KHz
Hopping Range
tH-OP
Hopping Period
fOSC-G
Green-Mode Frequency
±3.7
±4.2
±4.7
4.4
18
22
FAN6753 — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
ms
26
KHz
fDV
Frequency Variation vs. VDD Deviation
VDD=11V to 22V
5
%
fDT
Frequency Variation vs. Temperature
Deviation
TA=-20 to 85°C
5
%
Continued on the following page…
PWM Frequency
fOSC
fOSC-G
VFB-G
VFB-N
VFB
Figure 5. VFB vs. PWM Frequency
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
5
VDD=15V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
LATCH Section
VLATCHth
Latch-Off Threshold Voltage
VLATCHth > 5.2V, after
100µs Latch Off
5.0
5.3
5.6
V
tD-LATCH
Latch-Off De-bounce Time
VLATCH< VLATCHth
40
100
160
µs
92
100
108
µA
1/4.5
1/4.0
1/3.5
V/V
7
kΩ
V
ILATCH
Output Current from LATCH Pin
Feedback Input Section
AV
Input Voltage to Current-Sense Attenuation
ZFB
Input Impedance
VFB-OPEN
VFB-OLP
4
Output High Voltage
FB Pin Open
5.0
5.3
5.6
FB Open-Loop Trigger Level
4.6
4.8
5.0
V
tD-OLP
Delay Time of FB Pin Open-Loop Protection
50
56
62
ms
VFB-N
Green-Mode Entry FB Voltage
2.8
3.0
3.2
V
VFB-G
Green-Mode Ending FB Voltage
2.2
2.4
2.6
V
IFB-ZDC
Zero Duty-Cycle FB Current
1.5
mA
Current-Sense Section
ZSENSE
Input Impedance
12
VSTHFL
Current Limit Flatten Threshold Voltage
Duty>40%
0.87
0.90
0.93
V
VSTHVA
Current Limit Valley Threshold Voltage
VSTHFL–VSTHVA
Duty=0%
0.30
0.34
0.38
V
100
200
ns
100
140
180
ns
4.3
5.0
5.7
ms
60
65
70
%
1.5
V
tPD
Delay to Output
tLEB
Leading-Edge Blanking Time
TSS
Period During Soft-Startup Time
Startup Time
KΩ
FAN6753 — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
GATE Section
DCYMAX
Maximum Duty Cycle
VGATE-L
Gate Low Voltage
VDD=15V, IO=50mA
VGATE-H
Gate High Voltage
VDD=12V, IO=50mA
tr
Gate Rising Time
VDD=15V, CL=1nF
150
250
350
ns
tf
Gate Falling Time
VDD=15V, CL=1nF
30
50
90
ns
IGATE-SOURCE Gate Source Current
VDD=15V, GATE=6V
250
VGATE-CLAMP Gate Output Clamping Voltage
VDD=22V
8
V
mA
18
V
Over-Temperature Protection Section (OTP)
TOTP
TRestart
Protection Junction Temperature
Restart Junction Temperature
(3)
(4)
+135
°C
TOTP25
°C
Notes:
3. When activated, the output is disabled and the latch is turned off.
4. The threshold temperature for enabling the output again and resetting the latch, after over-temperature
protection has been activated.
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
6
5
20
4
IDD-OP (mA)
IDD_ST (μA)
25
15
10
5
3
2
1
0
-40
-30
-15
0
25
50
75
85
100
0
-40
125
-30
-15
0
Temperature (℃)
50
75
85
100
125
Figure 7. Operation Supply Current (IDD-OP)
vs. Temperature
Figure 6. Startup Current (IDD-ST) vs. Temperature
18
12
17
11
16
VDD-OFF (V)
VDD-ON (V)
25
Temperature (℃)
15
14
10
9
8
13
7
-40℃
-30℃
-15℃
0℃
25℃
50℃
75℃
85℃
100℃
125℃
-40℃
-30℃
-15℃
0℃
Temperature (℃)
25℃
50℃
75℃
85℃
100℃
125℃
Temperature (℃)
Figure 8. Start Threshold Voltage (VDD-ON)
vs. Temperature
Figure 9. Minimum Operating Voltage (VDD-OFF)
vs. Temperature
FAN6753 — Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
10
7
6
8
IHV-LC (μA)
IHV (mA)
5
4
3
6
4
2
2
1
0
-40
-30
-15
0
25
50
75
85
100
0
-40
125
-30
-15
0
Temperature (℃)
50
75
85
100
125
Figure 11. HV Pin Leakage Current After Startup
(IHV-LC) vs. Temperature
70
72
68
70
DCYMAX (%)
FOSC (kHz)
Figure 10. Supply Current Drawn from HV Pin (IHV)
vs. Temperature
66
64
62
60
-40
25
Temperature (℃ )
68
66
64
-30
-15
0
25
50
75
85
100
62
-40
125
Temperature (℃ )
-15
0
25
50
75
85
100
125
Temperature (℃ )
Figure 12. Frequency in Normal Mode (fOSC)
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
-30
Figure 13. Maximum Duty Cycle (DCYMAX)
vs. Temperature
www.fairchildsemi.com
7
62
7
60
58
TLPS (ms)
VFB_OLP (V)
6
5
56
54
52
4
50
48
3
-40℃
-30℃
-15℃
0℃
25℃
50℃
75℃
85℃
100℃
-40℃
125℃
-30℃
-15℃
0℃
25℃
50℃
75℃
85℃
100℃
125℃
Temperature (℃)
Temperature (℃)
Figure 14. FB Open-Loop Trigger Level (VFB-OLP)
vs. Temperature
Figure 15. Delay Time of FB Pin Open-Loop
Protection (tD-OLP) vs. Temperature
Figure 16. Output Current from LATCH Pin (ILATCH)
vs. Temperature
Figure 17. Latch-Off Threshold Voltage (VLATCHth)
vs. Temperature
FAN6753 — Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
28
VDD_OVP (V)
27.5
27
26.5
26
25.5
25
-40℃
-30℃
-15℃
0℃
25℃
50℃
75℃
85℃
100℃
125℃
Temperature (℃)
Figure 18. VDD Over-Voltage Protection (VDD-OVP)
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
8
Startup Current
Gate Output / Soft Driving
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
RHV, (1N4007 / 100KΩ recommended). Typical startup
current drawn from the HV pin is 3.5mA and charges
the hold-up capacitor through the diode and resistor.
When the VDD capacitor level reaches VDD-ON, the
startup current switches off. At this moment, the VDD
capacitor only supplies the FAN6753 before the
auxiliary winding of the main transformer provides the
operating current. For higher than 6KV surge test, RHV
of 100KΩ or above is recommended.
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Operating Current
Operating current is around 2.7mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6753 inserts a synchronized, positive-going ramp at
every switching cycle.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to reduce the switching frequency in lightload and no-load conditions. The on time is limited for
better abnormal or brownout protection. VFB, which is
derived from the voltage feedback loop, is taken as the
reference. Once VFB is lower than the threshold voltage,
the switching frequency is continuously decreased to
the minimum green-mode frequency of around 22KHz.
Constant Output Power Limit
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current-sense signal and VFB, the feedback voltage.
When the voltage on the SENSE pin reaches around
VCOMP=(VFB–0.6)/4, the switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
voltage around 0.9V for output power limit.
When the SENSE voltage across sense resistor RS
reaches the threshold voltage, around 0.9V, the output
GATE drive is turned off after a small delay, tPD. This
delay introduces an additional current proportional to
tPD • VIN / LP. Since the delay is nearly constant
regardless of the input voltage VIN, higher input voltage
results in a larger additional current and the output
power limit is higher than under low input line voltage.
To compensate this variation for a wide AC input range,
a sawtooth power-limiter is designed to solve the
unequal power-limit problem. The power limiter is
designed as a positive ramp signal fed to the inverting
input of the OCP comparator. This results in a lower
current limit at high-line inputs than at low-line inputs.
Leading-Edge Blanking (LEB)
VDD Over-Voltage Protection (OVP)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
VDD over-voltage protection is built in to prevent
damage due to abnormal conditions. If the VDD voltage
is over the over-voltage protection voltage (VDD-OVP) and
lasts for tD-VDDOVP, the PWM pulses are disabled until
the VDD voltage drops below the UVLO, then starts
again. Over-voltage conditions are usually caused by
open feedback loops.
Current Sensing / PWM Current Limiting
Under-Voltage Lockout (UVLO)
External Latch Function (LATCH Pin)
The turn-on and turn-off thresholds are fixed internally
at 15.5V and 9.5V, respectively. During startup, the
hold-up capacitor must be charged to 15.5V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 9.5V during startup. This
UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during startup.
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
FAN6753 — Highly Integrated Green-Mode PWM Controller
Functional Description
The LATCH pin can be used to control the FAN6753
entering latch mode by pulling this pin over 5.2V for
100µs. If floating, the LATCH pin is internally pulled
HIGH to 3.5V. It is not recommended to float or short
the LATCH pin to GND. This pin also includes a test
mode to disable the jitter function. LATCH pin internally
sources 100µA, so place a resistor in series to GND. Do
not let this voltage exceed 5.2V for the FAN6753 to
function normally.
www.fairchildsemi.com
9
Limited Power Control
Noise Immunity
The feedback (FB) voltage increases every time the
output of the power supply is shorted or overloaded. If
the FB voltage remains higher than a built-in threshold
for longer than tD-OLP, PWM output is turned off. As
PWM output is turned off, VDD begins decreasing.
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the FAN6753, and increasing the
power MOS gate resistance also improve performance.
When VDD goes below the turn-off threshold (~9.5V),
the controller is totally shut down. VDD is charged up to
the turn-on threshold voltage of 15.5V through the
startup resistor until PWM output is restarted. This
protection feature continues as long as the overloading
condition persists.
Over-Temperature Protection
(Internal OTP)
The built-in temperature-sensing circuit shuts down
PWM output once the junction temperature exceeds
135°C. While PWM output is shut down, VDD gradually
drops to the UVLO voltage (around 7.5V). Then VDD
charges up to the startup threshold voltage of 15.5V
through the startup resistor until PWM output is
restarted. This “hiccup” mode protection occurs
repeatedly as long as the temperature remains above
130°C. The temperature hysteresis window for the OTP
circuit is 25°C.
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
FAN6753 — Highly Integrated Green-Mode PWM Controller
Functional Description (Continued)
www.fairchildsemi.com
10
5.00
4.80
A
0.65
3.81
8
5
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
FAN6753 — Highly Integrated Green-Mode PWM Controller
Physical Dimensions
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 19. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
11
FAN6753 — Highly Integrated Green-Mode PWM Controller
© 2009 Fairchild Semiconductor Corporation
FAN6753 • Rev. 1.0.1
www.fairchildsemi.com
12