INTEGRATED CIRCUITS DATA SHEET TDA8755 YUV 8-bit video low-power analog-to-digital interface Product specification Supersedes data of June 1994 File under Integrated Circuits, IC02 Philips Semiconductors 1995 Mar 09 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 FEATURES APPLICATIONS • 8-bit resolution • High speed analog-to-digital conversion for video signal digitizing • Sampling rate up to 20 MHz • 100 Hz improved definition TV (IDTV). • TTL compatible digital inputs • 3-state TTL outputs • U, V two's complement outputs GENERAL DESCRIPTION • Y binary output The TDA8755 is a bipolar 8-bit video low-power analog-to-digital conversion (ADC) interface for YUV signals. The device converts the YUV analog input signal into 8-bit coded digital words in a 4 : 1 : 1 format at a sampling rate of 20 MHz. The U/V signals are converted in a multiplexed manner. All analog signal inputs are digitally clamped and a fast precharge is provided for start-up. All digital inputs and outputs are TTL compatible. Frame synchronization is supported in a multiplexed manner. • Power dissipation of 550 mW (typical) • Low analog input capacitance, no buffer amplifier required • High signal-to-noise ratio over a large analog input frequency range • Track-and-hold included • Clamp functions included • UV multiplexed ADC • 4 : 1 : 1 output data encoder • Stable voltage regulator included. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 46 55 mA ICCD digital supply current − 55 66 mA ICCO output stages supply current − 9 12 mA INL DC integral non-linearity fclk = 2 MHz − ±0.4 ±1 LSB DNL DC differential non-linearity fclk = 2 MHz − ±0.3 ±0.5 LSB EB effective bits − 7.1 − bits fclk(max) maximum clock frequency 20 − − MHz Ptot total power dissipation − 550 700 mW ORDERING INFORMATION PACKAGE TYPE NUMBER TDA8755T 1995 Mar 09 PINS PIN POSITION MATERIAL CODE 32 SO32L plastic SOT287-1 2 3 INV CLPV CLPU INU CLP CLPY INY 9 12 11 7 15 5 3 32 6 23 VCCO 10 AGND CLAMP V CLAMP U TRACK AND HOLD TRACK AND HOLD DIGITAL MULTIPLEXER CLAMP LOGIC SUPPLY AND REFERENCE VOLTAGE REGULATOR VCCD 8 8-BIT ADC 8 8 21 22 19 20 16 14 17 31 24 MLA734 - 1 TTL I/O TTL I/O 13 REG3 TDA8755 U AND V DATA ENCODER 4 REG2 8-BIT PIPELINE TIMING GENERATOR 8-BIT ADC COMPARATOR 128 TRACK AND HOLD TRACK AND HOLD 2 REG1 D'3 2 D'0 D'1 2 D'2 HREF CE CLK 8 D0 D7 U V Y YUV 8-bit video low-power analog-to-digital interface Fig.1 Block diagram. 1 n.c. COMPARATOR 16 CLAMP Y 8 SDN ANALOG MULTIPLEXER 18 DGND handbook, full pagewidth 1995 Mar 09 VCCA Philips Semiconductors Product specification TDA8755 BLOCK DIAGRAM Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 PINNING SYMBOL PIN DESCRIPTION n.c. 1 not connected REG1 2 decoupling input (internal stabilization loop decoupling) INY 3 Y analog voltage input REG2 4 decoupling input (internal stabilization loop decoupling) CLPY 5 Y clamp capacitor connection VCCA 6 analog positive supply voltage (+5 V) INU 7 U analog voltage input SDN 8 stabilizer decoupling node and analog reference voltage (+3.35 V) INV 9 V analog voltage input AGND 10 analog ground CLPU 11 handbook, halfpage n.c. 1 32 VCCD REG1 2 31 D7 INY 3 30 D6 REG2 4 29 D5 U clamp capacitor connection CLPY 5 28 D4 6 27 D3 26 D2 CLPV 12 V clamp capacitor connection VCCA REG3 13 decoupling input (internal stabilization loop decoupling) INU 7 CE 14 chip enable input (TTL level input active LOW) SDN 8 25 D1 TDA8755 INV 24 D0 9 CLP 15 clamp control input AGND 10 23 V CCO HREF 16 horizontal reference signal CLPU 11 22 D'3 CLK 17 clock input CLPV 12 21 D'2 DGND 18 digital ground REG3 13 20 D'1 D'0 19 V data output; bit 0 (n−1) D'1 20 V data output; bit 1 (n) D'2 21 U data output; bit 0 (n−1) D'3 22 U data output; bit 1 (n) VCCO 23 positive supply voltage for output stages (+5 V) D0 24 Y data output; bit 0 (LSB) D1 25 Y data output; bit 1 D2 26 Y data output; bit 2 D3 27 Y data output; bit 3 D4 28 Y data output; bit 4 D5 29 Y data output; bit 5 D6 30 Y data output; bit 6 D7 31 Y data output; bit 7 (MSB) VCCD 32 digital positive supply voltage (+5 V) 1995 Mar 09 19 CE 14 D'0 18 DGND CLP 15 HREF 16 17 CLK MLA728 - 1 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage −0.3 +7.0 V VCCD digital supply voltage −0.3 +7.0 V VCCO output stages supply voltage −0.3 +7.0 V ∆VCC supply voltage difference between VCCA and VCCD −1.0 +1.0 V supply voltage difference between VCCO and VCCD −1.0 +1.0 V supply voltage difference between VCCA and VCCO −1.0 +1.0 V V VI input voltage referenced to AGND − +5.0 Vclk(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V IO output current − +6 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C Tj junction temperature − +150 °C HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1995 Mar 09 PARAMETER thermal resistance from junction to ambient in free air 5 VALUE UNIT 70 K/W Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 CHARACTERISTICS VCCA = V6 to V10 = 4.75 to 5.25 V; VCCD = V32 to V18 = 4.75 to 5.25 V; VCCO = V23 to V18 = 4.75 to 5.25 V; AGND and DGND shorted together; VCCA to VCCD = −0.25 to +0.25 V; VCCO to VCCD = −0.25 to +0.25 V; VCCA to VCCO = −0.25 to +0.25 V; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 46 55 mA ICCD digital supply current − 55 66 mA ICCO output stages supply current − 9 12 mA VIL LOW level input voltage 0 − 0.8 V Inputs CLK (PIN 17) VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current Vclk = 0.4 V −400 − − µA IIH HIGH level input current Vclk = 2.7 V − − 100 µA ZI input impedance fclk = 20 MHz − 4 − kΩ CI input capacitance fclk = 20 MHz − 4.5 − pF CE, CLP AND HREF (PINS 14 TO 16) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current Vclk = 0.4 V −400 − − µA IIH HIGH level input current Vclk = 2.7 V − − 100 µA CLPY (PIN 5) V5 clamp voltage for 16 output code − 3.725 − V I5 clamp output current − ±50 − µA CLPU AND CLPV (PINS 11 AND 12) V11, 12 clamp voltage for 128 output code − 3.30 − V I11, 12 clamp output current − ±50 − µA INY (PIN 3) VI(p-p) input voltage, full range (peak-to-peak value) fi = 4.43 MHz 0.93 1.0 1.07 V ZI input impedance fi = 6 MHz − 30 − kΩ CI input capacitance fi = 6 MHz − 1 − pF 1995 Mar 09 6 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface SYMBOL PARAMETER TDA8755 CONDITIONS MIN. TYP. MAX. UNIT INU AND INV (PINS 7 AND 9) VI(p-p) input voltage, full range (peak-to-peak value) fi = 1.5 MHz 0.93 1.03 1.13 V ZI input impedance fi = 2 MHz − 30 − kΩ CI input capacitance fi = 2 MHz − 1 − pF crosstalk between Y, U and V − −55 −50 dB Vref reference voltage − 3.32 − V VREG line regulation − 4.0 − mV IL load current −2 − − mA IO = 0.4 mA 0 − 0.4 V IO = 1.5 mA 0 − 0.5 V INPUTS ISOLATION αct Outputs SDN (PIN 8) 4.75 V ≤ VCCA ≤ 5.25 V DIGITAL OUTPUTS D0 TO D7 AND D’0 TO D’3 (PINS 24 TO 31 AND 19 TO 22) VOL LOW level output voltage VOH HIGH level output voltage IO = −0.4 mA 2.4 − VCCD V IOZ output current in 3-state mode 0.4 V < VO < VCCD −20 − +20 µA Switching characteristics fclk(max) maximum clock frequency 20 − − MHz fclk(min) minimum clock frequency − − 2.0 MHz tCPH clock pulse width HIGH 20 − − ns tCPL clock pulse width LOW 20 − − ns Analog signal processing (fclk = 20 MHz; 50% clock duty factor) Gdiff differential gain note 1; see Fig.8 − 2 − % ϕdiff differential phase note 1; see Fig.8 − 3 − deg f1 fundamental harmonics (full-scale) note 2 − − 0 dB fall harmonics (full-scale), all components note 2; see Fig.10 − −54 − dB SVRR1 supply voltage ripple rejection 1 note 3 − −40 − dB SVRR2 supply voltage ripple rejection 2 note 3 − 1.0 − %/V fclk = 2 MHz − ±0.4 ±1.0 LSB Transfer function (50% clock duty factor) INL DC integral non-linearity DNL DC differential non-linearity fclk = 2 MHz − ±0.3 ±0.5 LSB AILE AC integral non-linearity note 4 − ±1.0 ±2.0 LSB EB effective bits note 5; Fig.10 − 7.1 − bits 1995 Mar 09 7 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface SYMBOL PARAMETER TDA8755 CONDITIONS MIN. TYP. MAX. UNIT Timing (fclk = 20 MHz); note 6; see Figs 3 to 7 tds sampling delay time − 1 − ns th output hold time 7 − − ns td output delay time − 33 42 ns tdZH 3-state output delay time enable-to-HIGH − 10 14 ns tdZL 3-state output delay time enable-to-LOW − 10 14 ns tdHZ 3-state output delay time disable-to-HIGH − 8 11 ns tdLZ 3-state output delay time disable-to-LOW − 4 6 ns tr clock rise time 3 5 − ns tf clock fall time 3 5 − ns tsu HREF set-up time 7 − − ns th HREF hold time 3 − − ns tr data output rise time − 12 − ns tf data output fall time − 16 − ns tCLP minimum time for active clamp 3 − − µs note 7; see Fig.9 Notes 1. Low frequency ramp signal (VI(p-p) = full-scale and 64 µs period) combined with a sinewave input voltage (VI(p-p) = 0.25 full-scale, fi = maximum permitted frequency) at the input. 2. The input conditions are related as follows: a) Y channel: VI(p-p) = 1.0 V; fi = 4.43 MHz b) U/V channel: VI(p-p) = 1.0 V; fi = 1.5 MHz. 3. Supply voltage ripple rejection: a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation of 0.5 V: ∆V I ( 127 ) SVRR1 = 20 log ---------------------∆V CCA b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V: ∆ ( V I ( 0 ) – V I ( 255 ) ) 1 SVVR2 = ------------------------------------------------ × -----------------V I ( 0 ) – V I ( 255 ) ∆V CCA 4. Full-scale sinewave (fi = 4.43 MHz for Y and fi = 1.5 MHz for U and V; fclk = 20 MHz). 5. The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform (FFT) treatment taking 4 × Tclk (clock periods) acquisition points per period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 6. Output data acquisition is available after the maximum delay time of td. 7. U and V output data is not valid during tCLP. 1995 Mar 09 8 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface Table 1 Table 2 TDA8755 Mode selection CE D7 TO D0; D’3 TO D’0 1 high impedance 0 active; binary Output data coding OUTPUT PORT BIT Y D7 Y07 Y17 Y27 Y37 D6 Y06 Y16 Y26 Y36 D5 Y05 Y15 Y25 Y35 D4 Y04 Y14 Y24 Y34 D3 Y03 Y13 Y23 Y33 D2 Y02 Y12 Y22 Y32 D1 Y01 Y11 Y21 Y31 D0 Y00 Y10 Y20 Y30 U V t CPH OUTPUT DATA D’3 U07 U05 U03 U 01 D’2 U06 U04 U02 U 00 D’1 V07 V05 V03 V01 D’0 V06 V04 V02 V00 t CPL andbook, full pagewidth 1.4 V CLK sample N V sample N 1 sample N 2 sample N 3 sample N 4 sample N 5 l th t ds 2.4 V D0 to D7 DATA N 4 DATA N 3 DATA N 2 DATA N 1 DATA N DATA N 1 1.4 V 0.4 V td Fig.3 Timing diagram (INY signal). 1995 Mar 09 9 MSA646 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 V CCD andbook, full pagewidth 50 % CE t dHZ t dZH HIGH 90 % output data 50 % t dLZ LOW t dZL HIGH output data 50 % LOW TEST 10 % V CCD 3.3 kΩ S1 TDA8755 15 pF tdLZ VCCD tdZL VCCD tdHZ GND tdZH GND MBD874 CE fCE = 100 kHz. Fig.4 Timing diagram and test conditions of 3-state output delay time. handbook, halfpage TDA8755 test probe TEK P6201 D0 to D7 15 pF MLA733 - 1 Fig.5 1995 Mar 09 Load circuit for the 3-state output timing measurement. 10 S1 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface handbook, full pagewidth TDA8755 sample N CLK 1 sample N 4 2 4 3 5 HREF sample N output data valid t su output data N 4 N 3 N 2 N 1 th MLA732 - 1 N The output data is valid 4 clock periods after HREF goes HIGH. Fig.6 Timing definition for set-up and hold times (HREF signal). 4 clock periods (Tclk ) handbook, full pagewidth sample N sample N 4 x T clk CLK HREF sample N 4 (Tclk 1) output data valid output data N 4 N 3 N 3 MLA731 - 1 When the HREF period is a multiple of 4 clock periods, the output data is valid without any clock delay. The internal circuit always gives an internal delay of 4 clock periods as illustrated in Fig.6. Fig.7 Timing diagram (HREF signal). 1995 Mar 09 11 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 handbook, full pagewidth 0.3 V Y, U and V channel 1.2 V 0.3 V 64 µs MSA644 Y channel = 4.43 MHz sinewave. U, V channel = 1.5 MHz sinewave. Fig.8 Input test signal for differential gain and phase measurements. handbook, full pagewidthdigital MSA645 output level 255 black-level clamping Y : 16 U,V : 128 0 time t CLP CLP Fig.9 Clamping control timing. 1995 Mar 09 12 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 MBD873 0 handbook, full pagewidth amplitude (dB) 20 40 60 80 100 120 0 1.25 2.50 3.75 5.00 6.25 7.50 Effective bits: 7.30; THD = −53.35 dB. Harmonic levels (dB): 2nd = −58.38; 3rd = −60.03; 4th = −57.30; 5th = −69.38; 6th = −67.09. Fig.10 Fast Fourier Transform (fclk = 20 MHz; fi = 4.43 MHz). 1995 Mar 09 13 8.75 f (MHz) 10.00 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 APPLICATION INFORMATION n.c. andbook, full pagewidth 10 nF AGND 1 32 VCCD 5V 10 nF REG1 2 31 3 30 4 29 5 28 6 27 7 26 8 25 D7 DGND INY (3) D6 4.7 µF REG2 AGND D5 220 nF AGND CLPY (1) VCCA 5V D4 D3 10 nF INU (3) 4.7 µF SDN + 3.35 V (2) 10 nF D1 TDA8755 INV (3) D2 9 24 10 23 4.7 µF AGND D0 VCCO 5V 10 nF AGND CLPU (1) 11 22 D'3 DGND CLPV AGND (1) REG3 AGND 12 21 13 20 14 19 15 18 16 17 D'2 D'1 220 nF CE CLP HREF D'0 DGND CLK MLA735 - 1 The analog and digital supplies should be separated and decoupled. (1) Clamp capacitors must be determined in accordance with the application; recommended values are CLPY = 18 nF, CLPU and CLPV = 33 nF. (2) It is possible to use the reference output voltage pin SDN to drive other analog circuits under the limits indicated in Chapter “Characteristics”. (3) Input signal pins have a high bandwidth. It is necessary to take special care on PCB layout to avoid any interaction from other signals (digital clocks for example). Fig.11 Application diagram. 1995 Mar 09 14 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 andbook, full pagewidth Y 12 U VDRAM 1 x TMS4C2970 12 NOISE REDUCTION INCLUDING CROSS-COLOUR REDUCTION TDA8755 VDRAM 1 x TMS4C2970 V 12 SAA4940 12 SAA7158 Y U 12 VIDEO ENHANCEMENT, LFR PROCESSING V AND DACs 2 to video processor 2 12 12/13.5/16/18 MHz VCO1 control 32/36 MHz VCO2A MEMORY CONTROLLER SAA4951 VSYNC 27 MHz SC1 control I2 C H2, V2 (32 kHz/100 Hz) 2 VCO2B data 8 MICROCONTROLLER PCB83C652 2 µC bus MSA642 Fig.12 Block diagram of a full-options Improved Picture Quality (IPQ) module. 1995 Mar 09 15 to deflection processor Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 andbook, full pagewidth Y U VDRAM 1x TMS4C2970 12 TDA8755 V 12 Y VIDEO ENHANCEMENT AND DACs U SAA7165 V to video processor 2 2 I C bus 12/13.5/16/18 MHz VCO1 control 32/36 MHz VCO2A MEMORY CONTROLLER SAA4951 VSYNC 27 MHz SC1 control I2 C H2, V2 (32 kHz/100 Hz) 2 data 8 VCO2B MSA643 MICROCONTROLLER PCB83C652 Fig.13 Block diagram of an economic Improved Picture Quality (IPQ) module. 1995 Mar 09 16 to deflection processor Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 PACKAGE OUTLINE handbook, plastic full pagewidth SO32: small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.2 1.0 0.25 0.25 0.1 0.95 0.55 inches 0.10 0.012 0.096 0.004 0.086 0.01 0.02 0.01 0.011 0.007 0.81 0.80 0.30 0.29 0.050 0.42 0.39 0.055 0.043 0.016 0.047 0.039 0.01 0.01 0.004 0.037 0.022 θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-01-25 SOT287-1 1995 Mar 09 EUROPEAN PROJECTION 17 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Plastic small outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C. Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.) A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Mar 09 18 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 NOTES 1995 Mar 09 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 15/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)480 6960/480 6009 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. 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(022)74 8341 Philips Semiconductors Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. 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Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD38 © Philips Electronics N.V. 1995 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 533061/30/03/pp20 Document order number: Date of release: 1995 Mar 09 9397 750 00027