INTEGRATED CIRCUITS DATA SHEET TDA8761A 9-bit analog-to-digital converter for digital video Product specification Supersedes data of 1997 Aug 21 File under Integrated Circuits, IC02 1998 Nov 03 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A FEATURES APPLICATIONS • 9-bit resolution Analog-to-digital conversion for: • Sampling rate up to 40 MHz • Video data digitizing • DC sampling allowed • Digital Video Broadcasting (DVB) • One clock cycle conversion only • Cable TV. • High signal-to-noise ratio over a large analog input frequency range (8.2 effective bits at 10 MHz full-scale input at fclk = 30 MHz) GENERAL DESCRIPTION The TDA8761A is a 9-bit Analog-to-Digital Converter (ADC) for professional video and digital video set box applications. It converts the analog input signal into 9-bit binary-coded digital words at a maximum sampling rate of 40 MHz. Its linearity performance ensures the required conversion accuracy in the event of 256-QAM demodulator concept and for all symbol frequencies. All digital inputs and outputs are TTL and CMOS compatible, although a low-level sine wave clock input signal is allowed. • No missing codes guaranteed • In Range (IR) CMOS output • Levels TTL and CMOS compatible digital inputs • 3 to 5 V CMOS digital outputs • Low-level AC clock input signal allowed • External reference voltage regulator • Power dissipation only 158 mW (typical) • Low analog input capacitance, no buffer amplifier required • No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 3.0 3.3 5.25 V ICCA analog supply current − 18 24 mA ICCD digital supply current − 13 18 mA ICCO output stages supply current fclk = 30 MHz; ramp input − 1 2 mA INL integral non-linearity fclk = 30 MHz; ramp input − ±0.8 ±1.6 LSB AINL AC integral non-linearity full-scale input sine wave; note 1 − ±0.75 0.9 LSB 50% full-scale input sine wave; note 1 − ±0.5 ±0.75 LSB DNL differential non-linearity fclk = 30 MHz; ramp input − ±0.3 ±0.7 LSB ADNL AC differential non-linearity full-scale input sine wave; note 1 − ±0.5 ±0.75 LSB 50% full-scale input sine wave; note 1 − ±0.3 ±0.5 LSB fclk(max) maximum clock frequency 40 − − MHz Ptot total power dissipation − 158 173 mW Note 1. fi = 10 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz. 1998 Nov 03 2 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A ORDERING INFORMATION PACKAGE TYPE NUMBER TDA8761AM NAME DESCRIPTION VERSION SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 BLOCK DIAGRAM handbook, full pagewidth V CCA CLK VCCD2 OE 3 1 11 10 2 CLOCK DRIVER VRT TC TDA8761A 9 25 D8 MSB 24 D7 23 D6 RLAD analog voltage input VI VRM 8 22 D5 ANALOG -TO - DIGITAL CONVERTER 21 D4 CMOS OUTPUTS LATCHES data outputs 20 D3 19 D2 7 18 D1 17 D0 13 VRB 6 LSB VCCO 28 VCCD1 IN RANGE LATCH 4 AGND 12 27 DGND2 DGND1 analog ground CMOS OUTPUT 14 OGND output ground digital grounds Fig.1 Block diagram. 1998 Nov 03 3 26 MBG910 IR output Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A PINNING SYMBOL PIN DESCRIPTION CLK 1 clock input TC 2 two’s complement input (active LOW) VCCA 3 analog supply voltage (5 V) AGND 4 analog ground n.c. 5 not connected VRB 6 reference voltage BOTTOM input VRM 7 reference voltage MIDDLE VI 8 analog input voltage VRT 9 reference voltage TOP input OE 10 output enable input (CMOS level input, active LOW) VCCD2 11 digital supply voltage 2 (5 V) DGND2 12 digital ground 2 VCCO 13 supply voltage for output stages (3 to 5 V) OGND 14 output ground n.c. 15 not connected n.c. 16 not connected D0 17 data output; bit 0 (LSB) D1 18 data output; bit 1 D2 19 data output; bit 2 D3 20 data output; bit 3 D4 21 data output; bit 4 D5 22 data output; bit 5 D6 23 data output; bit 6 D7 24 data output; bit 7 D8 25 data output; bit 8 (MSB) IR 26 in range data output DGND1 27 digital ground 1 VCCD1 28 digital supply voltage 1 (5 V) 1998 Nov 03 handbook, halfpage CLK 1 28 VCCD1 TC 2 27 DGND1 VCCA 3 26 IR AGND 4 25 D8 n.c. 5 24 D7 VRB 6 23 D6 VRM 7 VI 8 21 D4 VRT 9 20 D3 22 D5 TDA8761A OE 10 19 D2 VCCD2 11 18 D1 DGND2 12 17 D0 V CCO 13 16 n.c. OGND 14 15 n.c. MBG909 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage differences between VCCA and VCCD −1.0 +1.0 V VCCD and VCCO −1.0 +4.0 V −1.0 +4.0 V VI input voltage referenced to AGND −0.3 +7.0 V Vi(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C Tj junction temperature − +150 °C VCCA and VCCO Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage differences ∆VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1998 Nov 03 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 5 VALUE UNIT 110 K/W Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A CHARACTERISTICS VCCA = V3 to V4 = 4.75 to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; Vi(p-p) = 1.8 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 3.0 3.3 5.25 V ∆VCC supply voltage differences between VCCA and VCCD −0.2 − +0.2 V VCCA and VCCO −0.2 − +2.25 V VCCD and VCCO −0.2 − +2.25 V − 18 24 mA ICCA analog supply current ICCD digital supply current ICCO output stages supply current − 13 18 mA 1 2 mA 0 − 0.8 V fclk = 30 MHz; ramp input − Inputs CLOCK INPUT CLK (REFERENCED TO DGND); note 1 VIL LOW-level input voltage VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current Vclk = 0.8 V −1 0 +1 µA IIH HIGH-level input current Vclk = 2 V − 2 10 µA Zi input impedance fclk = 30 MHz − 2 − kΩ Ci input capacitance − 2 − pF INPUTS OE AND TC (REFERENCED TO DGND); see Table 2 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current VIL = 0.8 V −1 − − µA IIH HIGH-level input current VIH = 2.0 V − − 1 µA − 17 − µA VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) IIL LOW-level input current VI = VRB = 1.3 V IIH HIGH-level input current VI = VRT = 3.43 V − 35 − µA Zi input impedance fi = 10 MHz − 8 − kΩ Ci input capacitance − 5 − pF 1998 Nov 03 6 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video SYMBOL PARAMETER TDA8761A CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder; see Table 1 VRB reference voltage BOTTOM 1.2 1.3 2.45 VRT reference voltage TOP 3.2 3.43 VCCA − 0.8 V Vdiff differential reference voltage VRT − VRB 2 2.13 3.0 Iref reference current − 8.7 − mA RLAD resistor ladder − 245 − Ω TCRLAD temperature coefficient of the resistor ladder − 1860 − ppm − 456 − mΩ/K VosB offset voltage BOTTOM note 2 − 160 − mV VosT offset voltage TOP note 2 − 160 − mV Vi(p-p) analog input voltage (peak-to-peak value) note 3 1.7 1.81 2.55 V − VRT − VRB = 2.13 V V V Outputs DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND) VOL LOW-level output voltage IOL = 1 mA 0 0.5 V VOH HIGH-level output voltage IOH = −1 mA VCCO − 0.5 − VCCO V IOZ output current in 3-state mode 0.5 V < VO < VCCO −20 − +20 µA Switching characteristics CLOCK INPUT CLK; see Fig.4; note 1 fclk(max) maximum clock frequency 40 − − MHz tCPH clock pulse width HIGH 10 − − ns tCPL clock pulse width LOW 10 − − ns ±0.4 ±1 LSB Analog signal processing LINEARITY INL integral non-linearity fclk = 30 MHz; ramp input − AINL AC integral non-linearity full-scale input sine wave; note 4 − ±0.75 ±0.9 LSB 50% full-scale input sine wave; note 4 − ±0.5 ±0.75 LSB DNL differential non-linearity fclk = 30 MHz; ramp input − ±0.3 ±0.7 LSB ADNL AC differential non-linearity full-scale input sine wave; note 4 − ±0.5 ±0.75 LSB 50% full-scale input sine wave; note 4 − ±0.3 ±0.5 LSB OFER offset error middle code; VRB = 1.3 V; VRT = 3.43 V − ±1 − LSB GER gain error (from device to device) VRB = 1.3 V; VRT = 3.43 V; note 5 − ±0.1 − % 1998 Nov 03 7 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video SYMBOL PARAMETER TDA8761A CONDITIONS MIN. TYP. MAX. UNIT BANDWIDTH (fclk = 30 MHZ) B analog bandwidth − 15 − MHz 75% full-scale sine wave; − note 6 20 − MHz small signal at mid-scale; − VI = ±10 LSB at code 256; note 6 350 − MHz full-scale sine wave; note 6 tSTLH analog input settling time LOW-to-HIGH full-scale square wave; Fig.6; note 7 − 1.5 3.0 ns tSTHL analog input settling time HIGH-to-LOW full-scale square wave; Fig.6; note 7 − 1.5 3.0 ns fi = 10 MHz − −56 − dB 53 55 − dB fi = 4.43 MHz − 8.8 − bits fi = 10 MHz − 8.2 − bits fclk = 30 MHz − −56 − dB fclk = 30 MHz; fi = 10 MHz; VI = ±16 LSB at code 256 − 10−13 − times/ sample fclk = 30 MHz; PAL modulated ramp − 0.5 − % fclk = 30 MHz; PAL modulated ramp − 0.3 − °C HARMONICS (fclk = 30 MHZ); see Figs 7 and 8 THD total harmonic distortion SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 8 SNR signal-to-noise ratio (full scale) without harmonics; fclk = 30 MHz; fi = 10 MHz EFFECTIVE BITS; see Figs 7 and 8; note 8 ENOB effective bits fclk = 30 MHz TWO-TONE; note 9 TTIR two-tone intermodulation rejection BIT ERROR RATE BER bit error rate DIFFERENTIAL GAIN; note 10 Gdiff differential gain DIFFERENTIAL PHASE; note 10 ϕdiff differential phase 1998 Nov 03 8 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video SYMBOL PARAMETER TDA8761A CONDITIONS MIN. TYP. MAX. UNIT Timing (fclk = 30 MHz; CL = 15 pF); see Fig.4; note 11 tds sampling delay time th output hold time td output delay time 3 − ns 4 − − ns VCCO = 4.75 V − 10 13 ns VCCO = 3.15 V − 12 15 ns − − 15 pF digital output load CL − 3-state output delay times; see Fig.5 tdZH enable HIGH − 5.5 8.5 ns tdZL enable LOW − 12 15 ns tdHZ disable HIGH − 19 24 ns tdLZ disable LOW − 12 15 ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. Analog input voltages producing code 0 up to and including code 511: a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 °C. b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to code 511 at Tamb = 25 °C. 3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3. V RT – V RB a) The current flowing into the resistor ladder is I L = ----------------------------------------- and the full-scale input range at the converter, R OB + R L + R OT RL ˙ 852 × ( V to cover code 0 to code 511, is V I = R L × I L = ----------------------------------------- × ( V RT – V RB ) = 0. RT – V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ------------------------------------------ will be kept reasonably constant from device to device. Consequently variation of the output R OB + R L + R OT codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. fi = 10 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz. 5. ( V 511 – V 0 ) – V i(p-p) GER = ---------------------------------------------------- × 100 V i(p-p) 6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal. 7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. 1998 Nov 03 9 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A 8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = ENOB × 6.02 + 1.76 dB. 9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 and 10.10 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. 11. Output data acquisition: the output data is available after the maximum delay time of td. handbook, halfpage VRT 9 ROT VRM code 511 RL 7 RLAD IL code 0 ROB VRB 6 MGD233 Fig.3 Explanation of note 3. 1998 Nov 03 10 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video Table 1 TDA8761A Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.43 V) BINARY OUTPUT BITS STEP VI(p-p) TWO’S COMPLEMENT OUTPUT BITS IR D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 U/F <1.46 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1.46 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 . 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 . 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 511 3.27 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 O/F >3.27 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 Table 2 Mode selection TC OE D8 to D0 IR X 1 high impedance high impedance 0 0 active; two’s complement active 1 0 active; binary active t CPL handbook, full pagewidth t CPH VCCD 50% CLK 0V sample N sample N + 1 sample N + 2 Vl t ds DATA D0 to D8 th VCCO DATA N-2 DATA N-1 DATA N DATA N+1 50% 0V td MBG908 Fig.4 Timing diagram. 1998 Nov 03 11 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video ndbook, full pagewidth TDA8761A V CCD 50 % OE t dHZ t dZH HIGH 90 % output data 50 % t dLZ LOW t dZL HIGH output data 50 % LOW 10 % V CCD 3.3 kΩ S1 TDA8761A 15 pF TEST S1 t dLZ t dZL VCCD VCCD t dHZ DGND t dZH DGND OE MBG907 fOE = 100 kHz. Fig.5 Timing diagram and test conditions of 3-state output delay time. t STHL t STLH handbook, full pagewidth code 511 VI 50 % 50 % code 0 2 ns 2 ns CLK MGC359 50 % 50 % 0.5 ns Fig.6 Analog input settling-time diagram. 1998 Nov 03 12 0.5 ns Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A MBG912 0 handbook, full pagewidth amplitude (dB) 20 40 60 80 100 120 0 1.25 2.50 3.76 5.01 6.26 7.51 8.77 f (MHz) 10.0 Effective bits: 8.70; THD = −68.68 dB. Harmonic levels (dB): 2nd = −78.40; 3rd = −72.08; 4th = −75.85 dB; 5th = −76.26; 6th = −80.23. Fig.7 Typical Fast Fourier Transform (fclk = 30 MHz; fi = 4.43 MHz). MBG911 0 handbook, full pagewidth amplitude (dB) 20 40 60 80 100 120 0 1.87 3.75 5.62 7.50 9.37 11.2 Effective bits: 8.25; THD = −56.72 dB. Harmonic levels (dB): 2nd = −62.21; 3rd = −58.58; 4th = −80.29; 5th = −71.71; 6th = −72.04. Fig.8 Typical Fast Fourier Transform (fclk = 30 MHz; fi = 10 MHz). 1998 Nov 03 13 13.1 f (MHz) 15.0 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A FCE166 1 handbook, full pagewidth LSB 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 100 200 300 400 Code 500 Fig.9 Typical AC INL (fclk = 30 MHz; fi = 10 MHz). FCE165 1 handbook, full pagewidth LSB 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 100 200 300 Fig.10 Typical AC DNL (fclk = 30 MHz; fi = 10 MHz). 1998 Nov 03 14 400 Code 500 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A INTERNAL PIN CONFIGURATIONS handbook, halfpage handbook, halfpage VCCO V CCA D8 to D0 IR VI OGND AGND MGD231 MGC040 - 1 Fig.11 CMOS data and in range outputs. Fig.12 Analog inputs. handbook, halfpage VCCA handbook, halfpage V CCO VRT VRM OE R LAD VRB (TC) OGND AGND MBE557 MGD232 Fig.13 OE (TC) input. 1998 Nov 03 Fig.14 VRB, VRM and VRT inputs. 15 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A handbook, halfpage VCCD 1.5 V CLK DGND MBE559 - 1 Fig.15 CLK input. 1998 Nov 03 16 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A APPLICATION INFORMATION handbook, halfpage CLK TC VCCA AGND n.c. V CCD1 1 28 2 27 3 26 4 25 5 24 6 23 D6 7 22 DGND1 IR D8 D7 (1) V RB 100 nF (1) V RM AGND VI 100 nF D5 TDA8761A 8 21 9 20 10 19 11 18 12 17 13 16 14 15 D4 (1) V RT AGND D3 100 nF OE D2 AGND V CCD2 DGND2 V CCO D1 D0 (2) n.c. (2) OGND n.c. MBG906 The analog and digital supplies should be separated and decoupled. The external voltage regulator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VCCA supply through a resistor bridge and a decoupled capacitor. (1) VRB, VRM and VRT are decoupled to AGND. (2) Pins 15 and 16 may be connected to DGND in order to prevent noise influence. Fig.16 Application diagram. 1998 Nov 03 17 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1998 Nov 03 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 18 o Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1998 Nov 03 19 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Nov 03 20 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A NOTES 1998 Nov 03 21 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A NOTES 1998 Nov 03 22 Philips Semiconductors Product specification 9-bit analog-to-digital converter for digital video TDA8761A NOTES 1998 Nov 03 23 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/750/03/pp24 Date of release: 1998 Nov 03 Document order number: 9397 750 04668